TWI501327B - 三維積體電路及其製造方法 - Google Patents

三維積體電路及其製造方法 Download PDF

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TWI501327B
TWI501327B TW101140247A TW101140247A TWI501327B TW I501327 B TWI501327 B TW I501327B TW 101140247 A TW101140247 A TW 101140247A TW 101140247 A TW101140247 A TW 101140247A TW I501327 B TWI501327 B TW I501327B
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integrated circuit
layer
package component
dimensional integrated
redistribution layer
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TW201344814A (zh
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Kuo Chung Yee
Chun Hui Yu
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Taiwan Semiconductor Mfg Co Ltd
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Description

三維積體電路及其製造方法
本發明係有關於半導體元件，特別有關於三維積體電路及其製造方法。
從積體電路發展至今，由於各種電子元件，例如電晶體、二極體、電阻器、電容器等在集成密度上的持續改進，半導體工業經歷了持續快速的成長。在集成密度上的改進大多數來自於最小特徵尺寸的重複縮減，藉此可讓更多的元件被整合在特定的面積內。近年來隨著對更小的電子裝置之需求的成長，對於半導體晶片更需要更小且更創新的封裝技術。
隨著半導體技術的發展，三維(three dimensional：3D)積體電路已成為進一步降低半導體晶片的物理尺寸的有效選擇。在三維積體電路中，主動電路例如邏輯、記憶體、處理器電路以及類似的電路是在不同的晶圓上製造，並利用捉取與放置(pick-and-place)技術將每個晶圓上的晶片堆疊在封裝元件的頂端，藉由三維積體電路的實施，可以達到更高的密度。總而言之，三維積體電路可以達到更小的外觀尺寸(form factors)，具有成本效應、增加效能以及較低的能源耗損。
三維積體電路可包括積體電路晶片、中介層(interposer)以及封裝基底，積體電路晶片經由複數個焊錫凸塊附著在中介層的第一側上，利用焊錫凸塊提供積體電路晶片與中 介層之間的電性連接，中介層的第二側則藉由複數個互連凸塊附著至封裝基底上，互連凸塊例如為錫球，其可提供中介層與封裝基底之間的電性連接，再經由複數個封裝導線可依序讓電性連接至印刷電路板。
為了降低積體電路晶片與封裝基底之間因為熱應力而造成的潛在焊錫失效，使用中介層提供對積體電路晶片的熱膨脹係數之匹配，中介層也可以在具有間距縮減的較小接觸墊之積體電路晶片與具有間距增加的較大接觸墊之封裝基底之間提供適應性的變化。此外，中介層還可以包括各種電路元件，這些電路元件可以是主動、被動或主動與被動元件的組合。
三維積體電路具有一些優點，垂直地封裝多個半導體晶片的三維封裝技術的一個有利特徵為可降低製造成本，三維半導體元件的另一個有利特徵為藉由各種互連凸塊的使用而降低了寄生損失(parasitic losses)。
依據一實施例，提供三維積體電路的製造方法，此方法包括：在封裝元件的第一側上形成重分佈層；在重分佈層內形成容納腔室；將積體電路晶片附著至封裝元件的第一側上，其中積體電路晶片的互連凸塊嵌入容納腔室內；對積體電路晶片和封裝元件施加回焊製程；以及在封裝元件上形成封裝層。
依據一實施例，提供三維積體電路的製造方法，此方法包括：在封裝元件的第一側上形成第一光阻層；將第一 光阻層圖案化，形成具有容納結構的第一重分佈層；將積體電路晶片附著至封裝元件的第一側上，其中積體電路晶片的互連凸塊嵌入容納結構內；對積體電路晶片和封裝元件施加回焊製程；以及在封裝元件上形成封裝層。
依據一實施例，提供三維積體電路，包括：半導體晶片堆疊在封裝元件上；第一重分佈層設置在封裝元件的第一側上，其中第一重分佈層包括：空穴，其係配置成容納半導體晶片之對應的互連凸塊；以及溝槽，其與空穴連接；以及封裝層設置在封裝元件上，其中半導體晶片包埋在封裝層內。
為了讓本發明之上述目的、特徵、及優點能更明顯易懂，以下配合所附圖式，作詳細說明如下：
除非特別指明，在不同圖式中相對應的標號及符號表示相對應的組件，為了清楚地顯示與各種實施例有關的概念，這些圖式可以不需要按比例繪製。
以下詳述各實施例的製造與使用，然而，可以理解的是，本揭示提供許多可應用的發明概念，其可以在各種不同的特定領域中實施，在此所討論的特定實施例僅用於說明製造與使用本揭示的實施例之特定方式，並非限定本揭示的範圍。
本揭示所描述的實施例雖然是應用在三維積體電路的特定背景中，但是在此所揭示的實施例也可以應用在各種半導體元件上，各實施例配合所附圖式詳細說明如後。
第1圖顯示依據一實施例，三維積體電路的剖面示意圖，三維積體電路100可包括積體電路晶片102堆疊在封裝元件106上，如第1圖所示，積體電路晶片102經由複數個包含金屬柱凸塊(metal pillar bumps)122、微凸塊(micro bumps)120以及重分佈層(redistribution layers)124的內連線元件(interconnect components)附著在封裝元件106的第一側上。此外，封裝層(encapsulation layer)104可在封裝元件106的頂端上形成，積體電路晶片102和內連線元件例如微凸塊120與重分佈層124包埋在封裝層104內。
依據一實施例，封裝元件106可以是中介層(interposer)，為了簡化說明，在全篇描述中，封裝元件106可以選擇地稱為中介層106。中介層106可由矽、玻璃以及/或類似的材料製成，如第1圖所示，中介層106可包括複數個導通孔(vias)116包埋在中介層106中，中介層106還可包括第一側的重分佈層124在位於中介層106的第一側上方的晶種層(seed layer)118的頂端上形成。在積體電路晶片102接合至中介層106上之後，積體電路晶片102的主動電路經由晶種層118、重分佈層124、微凸塊120以及金屬柱凸塊122形成的導電通道耦接至中介層106的導通孔。
中介層106的第二側可藉由複數個互連凸塊(interconnect bumps)110附著至封裝基底(未繪出)，依據一實施例，這些互連凸塊110可以是焊料球(solder balls)。如第1圖所示，重分佈層124經由晶種層118連接至對應的貫穿導通孔(through via)116，此外，貫穿導通孔116經由 重分佈層114和凸塊下金屬化結構(under bump metallization structure)112連接至對應的互連凸塊110。金屬柱凸塊122、微凸塊120、重分佈層124、晶種層118、貫穿導通孔116、重分佈層114、凸塊下金屬化結構112以及互連凸塊110可以在積體電路晶片102的主動電路與封裝基底(未繪出)之間形成導電路徑，其依序經由複數個封裝導線電性連接至印刷電路板。
第2-13圖為依據一實施例，製造三維積體電路的中間階段的剖面示意圖，第2圖顯示依據一實施例，在載體上放置中介層的剖面示意圖，如第2圖所示，中介層106的第二側固定在載體202上，特別是中介層106的第二側藉由黏著劑204的實施而黏著在載體202的頂端，依據一實施例，黏著劑204可以是環氧樹脂以及/或類似的材料。
載體202可由各種材料形成，包括玻璃、矽、陶瓷、高分子以及/或類似的材料。
第3圖顯示依據一實施例，在介電層128內形成複數個開口302的剖面示意圖，介電層128在中介層106的頂端上形成，介電材料可包括聚苯噁唑(polybenzoxazole；PBO)、SU-8感光環氧樹脂、膜狀高分子材料以及/或類似的材料。考量電性與熱的需求，將介電層128選擇性的區域暴露於光線下，以形成各種開口(例如開口302)，開口例如介電層128內的開口302之形成包含微影技術的操作，其為習知技術，在此不再詳述。
第4圖顯示依據一實施例，在第3圖所示之半導體元件的介電層頂端上形成晶種層之後的剖面示意圖，為了對 後續巨塊金屬的沈積提供成核位置，在介電層128上沈積薄的晶種層402，薄的晶種層402可包括銅，可藉由適當的製程技術，例如物理氣相沈積(physical vapor deposition；PVD)、化學氣相沈積(chemical vapor deposition；CVD)或類似的技術形成薄的晶種層402。
第5圖顯示依據一實施例，在光阻層內形成複數個開口的剖面示意圖，在薄的晶種層402頂端上形成光阻層502，光阻層502可包括SU-8感光環氧樹脂、膜狀高分子材料以及/或類似的材料。考量電性的需求，將光阻層502選擇性的區域暴露於光線下，以形成各種開口(例如開口504)。
第6圖顯示依據一實施例，在第5圖所示之半導體元件的晶種層頂端上形成重分佈層之後的剖面示意圖，如第6圖所示，導電材料填充開口(例如開口504)而形成重分佈層124，導電材料可以是銅，但也可以是任何合適的導電材料，例如銅合金、鋁、鎢、銀以及前述之組合，重分佈層124可藉由適當的技術例如電化學電鍍製程形成。
第7圖顯示依據一實施例，在第6圖所示之半導體元件的光阻層移除之後的剖面示意圖，可使用適當的光阻剝離技術例如電漿灰化(plasma ashing)、乾式剝離(dry stripping)以及/或類似的技術移除第6圖中所示之殘留的光阻層502，光阻剝離技術為習知技術，在此不再詳述。
依據一實施例，可在薄的晶種層402暴露出來的部分上施加適當的蝕刻技術，例如濕蝕刻或乾蝕刻，使得薄的晶種層402暴露出來的部分被移除，濕蝕刻製程或乾蝕刻 製程的詳細操作為習知技術，在此不再詳述。
雖然第7圖中顯示中介層106具有單一層的重分佈層，然而中介層106也可以容納任何數量的重分佈層，在此所示之重分佈層的數量僅為了讓各種實施例的發明概念之說明得以簡化，本揭示並不限定於重分佈層的任何特定的數量。
第8A圖顯示依據一實施例，重分佈層的局部平面示意圖，重分佈層804可包括用於容納在後續製程中形成的微凸塊之容納結構(holding structure)，依據一實施例，容納結構包含容納腔室(holding chamber)802以及溝槽(trench)801，容納腔室802可以是圓形的空穴，其讓微凸塊可以安裝在容納腔室802內。
雖然空穴(例如容納腔室802)的形狀大抵上是如第8A圖中所示之圓形，但是在不脫離各種實施例的範圍與精神內，空穴也包括其他形狀，例如，但不限於橢圓形、正方形、長方形以及類似的形狀。
容納腔室802和溝槽801都可以藉由實施適當的圖案化技術而形成，再參閱第5圖，為了形成溝槽801和容納腔室802，在圖案化製程之後，光阻材料可以覆蓋容納腔室和溝槽所在的區域，藉此在第6圖所示之重分佈層的製程步驟期間，讓金屬材料無法填充容納腔室和溝槽，於光阻剝離製程之後，在容納腔室和溝槽內殘留的光阻材料會被移除，以形成容納腔室802和溝槽801。
第8B圖顯示依據一實施例，將微凸塊放置在容納結構內的立體示意圖，微凸塊806具有球形的端子，重分佈層 804的空穴可以容納微凸塊806的球形端子，因此當具有微凸塊的積體電路晶片接合在中介層上時，微凸塊可以被重分佈層的空穴托住而不需接合墊。此外，溝槽801的使用則提供了通道，經由此通道可以讓焊料和助焊劑氣體在第9圖所示之後續的回焊製程期間得以流動。
具有如第8B圖所示之容納結構的一個優點特徵為容納結構可以讓相鄰的內連線之間的微細間距成為可能，此外，藉由使用無接合墊的容納結構，可以達到較小的排除區域(keep-out zone)，藉此降低了凸塊對凸塊間隙(bump-to-bump clearance)。
第9圖顯示依據一實施例，將積體電路晶片接合至第7圖所示之半導體元件的中介層上之後的剖面示意圖，積體電路晶片102固定在中介層106上，更特別的是，積體電路晶片102的每個微凸塊嵌入重分佈層內對應的容納腔室中(此圖未繪出，但是在第8B圖中顯示)。進行回焊製程，使得積體電路晶片102經由金屬微凸塊連接至中介層106。另外，在中介層106的頂端上形成封裝層104，以保護重分佈層的頂端表面避免被侵蝕。此外，封裝層104的厚度足夠厚，藉此在後續的製程步驟中機械性地支撐積體電路晶片102，因此，三維積體電路可以從載體202分離。
第9圖雖然未詳細繪出積體電路晶片102的細節，但是積體電路晶片102可包括基本的半導體層，例如主動電路層、基底層、層間介電層(inter-layer dielectric；ILD)以及金屬間介電層(inter-metal dielectric；IMD)(未繪出)。積體電路晶片102可包括矽基底；另外，積體電路晶片102 可包括絕緣層上的矽基底(silicon-on-insulator substrate)。積體電路晶片102還可包括各種電子電路(未繪出)，在積體電路晶片102內形成的電子電路可以是適合於特定應用的任何種類的電路。
依據一實施例，電子電路可包含各種n型金氧半導體(n-type metal-oxide semiconductor；NMOS)以及/或p型金氧半導體(p-type metal-oxide semiconductor；PMOS)元件，例如電晶體、電容器、電阻器、二極體、光電二極體、電熔線以及類似的元件。電子電路可以互相連接，以執行一個或更多的功能，這些功能可包含記憶體結構、處理器結構、感測器、放大器、電力分配、輸入/輸出電路以及類似的功能。在此技術領域中具有通常知識者當可瞭解，上述例子的提供僅用於進一步說明本揭示之應用，並非將本揭示限定於任何方式。
封裝層104可由底部填膠(underfill)材料形成，依據一實施例，底部填膠材料可以是環氧樹脂，其塗佈在中介層106與積體電路晶片102之間的空隙，環氧樹脂可以用液體形式施加，並且可在固化製程之後硬化。依據另一實施例，封裝層104可以由可固化的材料形成，例如以高分子為基礎的材料、以樹脂為基礎的材料、聚亞醯胺(polyimide)、環氧樹脂(epoxy)以及前述材料的任何組合，可藉由旋轉塗佈製程、乾膜壓膜(dry film lamination)製程以及/或類似的製程形成封裝層104。
另外，封裝層104可以是形成在晶圓堆疊的頂端上的模塑料化合物層(molding compound layer)，模塑料化合物 層可以由可固化的材料形成，例如以高分子為基礎的材料、以樹脂為基礎的材料、聚亞醯胺(polyimide)、環氧樹脂(epoxy)以及前述材料的任何組合，可藉由旋轉塗佈製程、射出成型(injection molding)製程以及/或類似的製程形成模塑料化合物層。為了在後續的製程步驟期間，例如中介層106的背面製程期間，讓積體電路晶片102可靠地固定在中介層106的頂端上，使用模塑料化合物層讓中介層106以及在中介層106頂端上的積體電路晶片102不會發生裂解、彎曲、變形以及/或類似的現象。
第10圖顯示從第9圖所示之半導體元件移除載體的製程，依據一實施例，載體202可以從包含積體電路晶片102和中介層106的三維積體電路分離，可使用各種分離製程讓三維積體電路從載體202分開，各種分離製程可包括使用化學溶劑、紫外線曝光以及類似的製程。
第11圖顯示在第10圖所示之半導體元件的中介層的第二側上形成重分佈層之後的剖面示意圖，重分佈層114由導電材料形成，例如銅、銅合金、鋁、鎢、銀以及前述之組合，重分佈層114的形成可參閱上述第5-7圖的說明，在此不再詳述。
第12圖顯示依據一實施例，在第11圖所示之半導體元件形成複數個凸塊下金屬化結構之後的剖面示意圖，可以在重分佈層114的頂端上形成複數個凸塊下金屬化結構112，凸塊下金屬化結構112有助於避免互連凸塊110與中介層106之間發生擴散現象，藉此提供低阻抗的電性連接。
在凸塊下金屬化結構112上形成複數個互連凸塊 110，互連凸塊110提供有效的方式來連接三維積體電路與外部電路(未繪出)，依據一實施例，互連凸塊110可以是複數個焊料球，此外，互連凸塊110可以是複數個平面閘型陣列墊(land grid array(LGA)pads)。
第13圖顯示使用切割製程將第12圖所示之半導體元件分割成個別的晶片封裝1302和1304的製程，切割製程為習知技術，在此不再詳述。
雖然本發明已揭露較佳實施例如上，然其並非用以限定本發明，在此技術領域中具有通常知識者當可瞭解，在不脫離本發明之精神和範圍內，當可做些許更動與潤飾。因此，本發明之保護範圍當視後附之申請專利範圍所界定為準。
100‧‧‧三維積體電路
102‧‧‧積體電路晶片
104‧‧‧封裝層
106‧‧‧封裝元件(中介層)
110‧‧‧互連凸塊
112‧‧‧凸塊下金屬化結構
114、124、804‧‧‧重分佈層
116‧‧‧貫穿導通孔
118‧‧‧晶種層
120、806‧‧‧微凸塊
122‧‧‧金屬柱凸塊
128‧‧‧介電層
202‧‧‧載體
204‧‧‧黏著劑
302、504‧‧‧開口
402‧‧‧薄的晶種層
502‧‧‧光阻層
801‧‧‧溝槽
802‧‧‧容納腔室
1302、1304‧‧‧個別的晶片封裝
第1圖顯示依據一實施例，三維積體電路的剖面示意圖；第2圖顯示依據一實施例，在載體上放置中介層的剖面示意圖；第3圖顯示依據一實施例，在介電層內形成複數個開口的剖面示意圖；第4圖顯示依據一實施例，在第3圖之半導體元件的介電層頂端上形成晶種層之後的剖面示意圖；第5圖顯示依據一實施例，在光阻層內形成複數個開口的剖面示意圖； 第6圖顯示依據一實施例，在第5圖之半導體元件的晶種層頂端上形成重分佈層之後的剖面示意圖；第7圖顯示依據一實施例，將第6圖之半導體元件的光阻層移除之後的剖面示意圖；第8A圖顯示依據一實施例，重分佈層的局部平面示意圖；第8B圖顯示依據一實施例，將微凸塊放置在容納結構內的立體示意圖；第9圖顯示依據一實施例，將積體電路晶片接合至第7圖之半導體元件的中介層上之後的剖面示意圖；第10圖顯示從第9圖的半導體元件中移除載體的製程；第11圖顯示在第10圖之半導體元件的中介層的第二側上形成重分佈層之後的剖面示意圖；第12圖顯示依據一實施例，在第11圖之半導體元件形成複數個凸塊下金屬化結構之後的剖面示意圖；以及第13圖顯示使用切割製程將第12圖之半導體元件分割成個別的晶片封裝的製程。
100‧‧‧三維積體電路
102‧‧‧積體電路晶片
104‧‧‧封裝層
106‧‧‧封裝元件(中介層)
110‧‧‧互連凸塊
112‧‧‧凸塊下金屬化結構
114、124‧‧‧重分佈層
116‧‧‧貫穿的導通孔
118‧‧‧晶種層
120‧‧‧微凸塊
122‧‧‧金屬柱凸塊
128‧‧‧介電層

Claims (11)

  1. 一種三維積體電路的製造方法，包括：在一封裝元件的一第一側上形成一第一重分佈層；在該第一重分佈層內形成一容納腔室；形成具有該容納腔室和一溝槽的一容納結構；將一積體電路晶片附著至該封裝元件的該第一側上，其中該積體電路晶片的一互連凸塊嵌入該容納腔室內；對該積體電路晶片和該封裝元件施加一回焊製程；以及在該封裝元件上形成一封裝層。
  2. 如申請專利範圍第1項所述之三維積體電路的製造方法，更包括：將形成在該封裝元件的該第一側上的一介電層圖案化；在該介電層上沈積一晶種層；將形成在該晶種層上的一光阻層圖案化；以及使用一電化學電鍍製程在該晶種層上形成具有該容納結構的該第一重分佈層。
  3. 如申請專利範圍第2項所述之三維積體電路的製造方法，更包括：其中該容納腔室為圓形或橢圓形。
  4. 如申請專利範圍第2項所述之三維積體電路的製造方法，更包括：對該光阻層施加一光阻剝離製程；以及對該晶種層施加一蝕刻製程。
  5. 如申請專利範圍第1項所述之三維積體電路的製造方法，更包括：在該封裝元件上形成該封裝層，其中該積體電路晶片包埋在該封裝層內。
  6. 如申請專利範圍第1項所述之三維積體電路的製造方法，更包括：在該封裝元件的一第二側上形成一第二重分佈層；在該第二重分佈層上形成一凸塊下金屬化結構；以及在該凸塊下金屬化結構上形成一互連凸塊；其中該封裝元件為一中介層。
  7. 一種三維積體電路，包括：一半導體晶片，堆疊在一封裝元件上；一第一重分佈層，設置在該封裝元件的一第一側上，其中該第一重分佈層包括：一空穴，其係配置成容納該半導體晶片的一對應的互連凸塊；以及一溝槽，連接至該空穴；以及一封裝層，設置在該封裝元件上，其中該半導體晶片包埋在該封裝層內。
  8. 如申請專利範圍第7項所述之三維積體電路，更包括：一第二重分佈層，設置在該封裝元件的一第二側上；一凸塊下金屬化結構，設置在該第二重分佈層上；以及一第二互連凸塊，設置在該凸塊下金屬化結構上； 其中該封裝元件為一中介層，包括一導通孔耦接在該第一重分佈層與該第二重分佈層之間。
  9. 如申請專利範圍第7項所述之三維積體電路，更包括：一金屬柱凸塊，設置在該半導體晶片上；以及一第一互連凸塊，設置在該金屬柱凸塊上。
  10. 如申請專利範圍第7項所述之三維積體電路，更包括：一介電層，設置在該封裝元件的該第一側上；以及一晶種層，設置在該第一重分佈層與該介電層之間。
  11. 如申請專利範圍第7項所述之三維積體電路，其中該空穴為圓形或橢圓形。
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