TWI664683B - 半導體封裝件的製造方法 - Google Patents

半導體封裝件的製造方法 Download PDF

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Publication number
TWI664683B
TWI664683B TW106108726A TW106108726A TWI664683B TW I664683 B TWI664683 B TW I664683B TW 106108726 A TW106108726 A TW 106108726A TW 106108726 A TW106108726 A TW 106108726A TW I664683 B TWI664683 B TW I664683B
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Taiwan
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die
size
manufacturing
semiconductor package
standard size
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TW106108726A
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English (en)
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TW201836024A (zh
Inventor
彭昱銘
徐竹君
柯泓昇
葉秀倫
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佳邦科技股份有限公司
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Priority to TW106108726A priority Critical patent/TWI664683B/zh
Priority to US15/660,248 priority patent/US10468378B2/en
Publication of TW201836024A publication Critical patent/TW201836024A/zh
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Publication of TWI664683B publication Critical patent/TWI664683B/zh

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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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Abstract

一種半導體封裝件的製造方法，包括：提供一晶圓；在該晶圓中及在該晶圓上形成具有小於一標準尺寸0201的二分之一的一晶粒；藉由切割該晶圓獲得該晶粒；以及將該晶粒單粒化為一封裝，其中該封裝的尺寸等同或大於該標準尺寸0201。

Description

半導體封裝件的製造方法
本發明所揭露的實施例係涉及一種半導體封裝件的製造方法，尤指一種將小於一標準尺寸的晶粒單粒化為等於該標準尺寸的一封裝的半導體封裝件的製造方法。
隨著電子產業的蓬勃發展，電子產品亦逐漸進入多功能、高性能的研發方向。為滿足半導體封裝件高積集度(integration)以及微型化(miniaturization)的封裝要求，提供多數主被動元件及線路連接之電路板，亦逐漸由單層板演變成多層板，以使在有限的空間下，藉由層間連接技術(interlayer connection)擴大電路板上可利用的佈線面積而配合高電子密度之積體電路(integrated circuit)需求。
此“背景技術之討論”章節僅為提供背景技術資料。於此“背景技術之討論”中的陳述並非承認於此“背景技術”章節中揭示之標的構成本揭露之先前技術，且此“背景技術”章節沒有任何部分可用於作為承認本申請案的任何部分，包括此“背景技術”章節，構成本揭露之先前技術。
在本揭露的一實施例中，提供一種半導體封裝件的製造方法。該半導體封裝件的製造方法包括提供一晶圓；在該晶圓中及在該晶圓上形成具 有小於一標準尺寸0201的二分之一的一晶粒；藉由切割該晶圓獲得該晶粒；以及將該晶粒單粒化為一封裝，其中該封裝的尺寸等同或大於該標準尺寸0201。
在本揭露的一實施例中，該晶粒的尺寸為標準尺寸01005。
在本揭露的一實施例中，該封裝的尺寸等同或大於一標準尺寸0402及一標準尺寸DFN 10的一者。
在本揭露的一實施例中，該半導體封裝件的製造方法更包括提供一載體基板；形成一導電部件在該載體基板上；接合該晶粒至該導電部件上；以及囊封該晶粒，其中該晶粒的該單粒化包括：將該晶粒囊封後的一結果結構單粒化為該封裝，該封裝的尺寸等同或大於該標準尺寸0201。
在本揭露的一實施例中，該晶粒的該囊封包括：利用一保護材料囊封該晶粒。
在本揭露的一實施例中，該保護材料包括聚醯亞胺(polyimide)、環氧樹脂(epoxy resin)、苯並環丁烯樹脂(BCB)或高分子聚合物(polymer)的一者。
在本揭露的一實施例中，該載體基板包括一導電載板及一非導電載板的一者。
在本揭露的一實施例中，該導電載板包括一印刷電路板(printed circuit board，PCB)。
在本揭露的一實施例中，該導電部件在該載體基板上的該形成包括利用鋼板或網版印刷製程的一者形成該導電部件。
在本揭露的一實施例中，在鋼板或網版印刷製程的該者中，採用的材料包括銀或錫的一者。
在本揭露的一實施例中，該晶粒透過該導電部件而免於透過一導線與該載體基板電性連接。
在本揭露中，在囊封晶粒時，不係採用介電係數相對高的封裝膠體，而是採用乾膜製程中的保護材料，或是採用介電係數小於封裝膠體的封裝材料。據此，寄生效應相對不嚴重。此外，本發明係藉由非導電線的導電部件進行晶粒與載體基板間的電性連接，因此相對不容易引起寄生效應。是故，當晶粒操作在高頻時，晶粒受到寄生效應的影響相對小，進而使得晶粒電氣效能能相對得到提昇。再者，即使想要的封裝件的尺寸為標準尺寸的0201，或大於標準尺寸0201的標準尺寸0402及DFN 10，藉由本揭露的製造半導體封裝件的方法，能夠在晶圓的有限面積中，提供更多的晶粒，而該些晶粒在後續的單粒化過程中同樣能夠被單粒化為符合想要的封裝件的尺寸為標準尺寸的0201、0402或DFN 10。有鑑於此，本揭露的製造半導體封裝件的方法能使得成本效率相對提昇。
相對的，在一些相關的封裝件製造方法中，係利用封裝膠體進行囊封。然而，由於封裝膠體的介電係數相對高，封裝膠體可能引起相對嚴重的寄生效應(例如寄生電容或寄生電阻)。此外，晶粒係透過金屬導線與載體基板進行電性連接。因此，金屬導線的相對較長的長度也容易引起寄生效應。是故，當晶粒操作在高頻時，晶粒可能受到寄生效應的影響而使得晶粒電氣效能無法提昇。另外，封裝件的封裝可能需要多次的連接介面，相對地增加製程之複雜度。此外，晶粒的封裝除了需要黏晶(die bonding)製程、銲線(wire bonding)製程及封膠(molding)製程等繁複製程才能完成，還需要使用導線架或電路板之基板才能承載晶粒。如此一來，成本無法有效降低。
10‧‧‧晶圓
12‧‧‧晶粒
20‧‧‧半導體封裝件
21‧‧‧黏膠
22‧‧‧基板
23‧‧‧導通柱
24‧‧‧銲墊
26‧‧‧封裝膠體
28‧‧‧金屬導線
30‧‧‧晶圓
32‧‧‧晶粒
34‧‧‧接合墊
36‧‧‧接合墊
50‧‧‧載體基板
51‧‧‧導通柱
52‧‧‧接合墊
53‧‧‧導通柱
54‧‧‧接合墊
56‧‧‧接合墊
58‧‧‧接合墊
60‧‧‧導電部件
62‧‧‧導電部件
80‧‧‧囊封件
90‧‧‧結果結構
92‧‧‧經單粒化囊封件
94‧‧‧經單粒化基板
100‧‧‧方法
102-116‧‧‧操作
W1‧‧‧寬度
W2‧‧‧寬度
對於本揭露的更完整理解係可藉由參考詳細說明及申請專利範圍而結合附圖考慮時衍生，其中在整個附圖中，類似參考編號指代類似的元件。
圖1為在相關技術領域中的晶圓的示意圖。
圖2為在相關技術領域中的圖1的晶粒的半導體封裝件的示意圖。
圖3至9為根據本發明的製造半導體封裝件的方法的製造過程的剖面圖。
圖10為根據本發明的製造半導體封裝件的方法的流程圖。
現在使用特定語言描述圖式中所繪示之本揭露之實施例、或實例。然而應當理解的是，不意圖藉此限制本揭露的範疇。將在所述實施例中的任何變更及修改，以及描述在此文件中原理的任何進一步應用視為本揭露相關之所屬技術領域具有通常知識者正常會想到者。可能遍及實施例重複參考編號，但這並不是說一定需要將一個實施例的該(等)特徵施用到另一個實施例，即使它們共享相同的參考編號。將理解，當一元件被稱作“連接至”另一元件或“與另一元件耦合”時，其可以是直接連接至或耦合至另一元件、或者可出現中介元件。
再者，空間相關詞彙，諸如“在...之下”、“下面”、“下”、“上面”、“上”和類似詞彙，可為了使說明書便於描述如圖式繪示的一個元件或特徵與另一個(或多個)元件或特徵的相對關係而使用於本文中。除了圖式中所畫的方位外，這些空間相對詞彙也意圖用來涵蓋裝置在使用中或操作時的不同方位。該設備可以其他方式定向(旋轉90度或於其它方位)，據此在 本文中所使用的這些空間相關說明符可以類似方式加以解釋。
圖1為在相關技術領域中的晶圓10的示意圖。參照圖1，晶圓10包括複數個晶粒12。通常來說，晶粒的尺寸係按照該晶粒經過封裝以後所得到的封裝件所需要符合的規格記載的尺寸來決定。據此，當規格所記載的封裝件的尺寸為標準尺寸的0201時，晶粒的尺寸將本質上等於標準尺寸的0201時，晶粒的尺寸將本質上等於標準尺寸的0201，其中標準尺寸的0201指的是長為600微米(μm)、寬為300μm、高為300μm，其中長、寬、高各自可具有±100μm的偏差值。同理，當規格所記載的封裝件的尺寸為標準尺寸的0402時，晶粒的尺寸將本質上等於標準尺寸的0402，其中標準尺寸的0402指的是長為1000μm、寬為500μm、高為500μm，其中長、寬、高各自可具有±200μm的偏差值。又，當規格所記載的封裝件的尺寸為標準尺寸的DFN 10時，晶粒的尺寸將本質上等於標準尺寸的DFN 10時，晶粒的尺寸將本質上等於標準尺寸的DFN 10，其中標準尺寸的DFN 10指的是長為2500μm、寬為1000μm、高為500μm，其中長、寬、高各自可具有±200μm的偏差值。在實施上，由於在封裝中會加入其他額外元件，晶粒的尺寸會稍微小於標準尺寸的0402，但本質上相同於標準尺寸的0402。由於標準尺寸的0201及0402的尺寸相對大，因此晶粒12的尺寸也相對大。在晶圓10的給定面積下，由於晶粒12的尺寸相對大，一片晶圓10能夠包括的晶粒12的數量相對有限。
圖2為在相關技術領域中的圖1的晶粒12的半導體封裝件20的示意圖。參照圖2，除了晶粒12外，半導體封裝件20包括一基板22、複數個金屬導線28及一封裝膠體26。晶粒12係藉由一黏膠21固定於基板22的表面，又藉由複數個金屬導線28分別電性連接至基板22上複數個銲墊24。 基板22包括複數個導通柱23，因此複數個銲墊24可藉由複數個導通柱23與基板22底部之複數個接墊26電性連接。又，複數個接墊26可以與錫球(圖未示)結合，如此可以形成球柵陣列(ball grid array,BGA)封裝件。為能保護晶粒12及複數個金屬導線28不受損壞，封裝膠體26將晶粒12及複數個金屬導線28包覆以隔絕環境之影響。另，接續於圖1中所說明的，從圖2可看出晶粒12的尺寸，例如寬度W1，與封裝件20的尺寸，例如寬度W2，本質上相同。
簡言之，在圖2的封裝件20的結構中，係將晶粒12黏貼於基板22頂面。接著，進行打線接合(wire bonding)製程。此外，再於基板12之背面(接墊26所在的面)植以焊錫球以進行與外部電子元件之電性連接。在此情況下，通常來說，封裝膠體26的介電係數相對高，封裝膠體26可能引起相對嚴重的寄生效應(例如寄生電容或寄生電阻)。此外，金屬導線28的相對較長的長度也容易引起寄生效應。因此，當晶粒12操作在高頻時，晶粒12可能受到寄生效應的影響而使得晶粒12電氣效能無法提昇。另外，封裝件20的封裝可能需要多次的連接介面，相對地增加製程之複雜度。此外，晶粒12的封裝除了需要黏晶(die bonding)製程、銲線(wire bonding)製程及封膠(molding)製程等繁複製程才能完成，還需要使用導線架或電路板之基板才能承載晶粒12。如此一來，成本無法有效降低。
圖3至9為根據本發明的製造半導體封裝件的方法的製造過程的剖面圖。參照圖3，提供一晶圓30。此外，在晶圓30中及在晶圓30上形成具有遠小於標準尺寸0201的尺寸的晶粒32，其中標準尺寸的0201指的是長為600μm、寬為300μm、高為300μm，其中長、寬、高各自可具有±100μm的偏差值。或者，晶粒32的尺寸遠小於標準尺寸的0402，標準尺寸的 0402指的是長為1000微米(μm)、寬為500μm、高為500μm，其中長、寬、高各自可具有±200μm的偏差值。又，或者，晶粒32的尺寸遠小於標準尺寸的DFN 10，標準尺寸的DFN 10指的是長為2500μm、寬為1000μm、高為500μm，其中長、寬、高各自可具有±200μm的偏差值。在一實施例中，晶粒32的尺寸小於標準尺寸0201的二分之一。在一些實施例中，晶粒32的尺寸小於標準尺寸0201的約3%。在另一實施例中，晶粒32的尺寸小於標準尺寸0201的該一者的三分之一。在，又另一實施例中，晶粒32尺寸為標準尺寸的01005，其中標準尺寸的01005指的是，長為300微米(μm)、寬為160μm、高為100μm。接著，在晶粒32上形成接合墊34及36。在一實施例中，晶粒32的尺寸包括4密爾(mil)、6 mil及8 mil的一者。為了圖式簡潔，僅在一個晶粒32上繪製接合墊34及36。參照圖4，藉由切割晶圓30獲得晶粒32。換言之，各個晶粒32經由該切割操作彼此實體分離。
在一實施例中，晶粒32為一暫態電壓抑制器(transient voltage suppressor，TVS)。在另一些實施例中，晶粒32可以是邏輯晶粒(如，中央處理單元、微控制器、等)、記憶體晶粒(如，動態隨機存取記憶體(dynamic random access memory，DRAM)晶粒、靜態隨機存取記憶體(static random access memory，SRAM)晶粒、等)、功率管理晶粒(如，功率管理積體電路(power management integrated circuit，PMIC)晶粒)、射頻(radio frequency，RF)晶粒、感測器晶粒、微機電系統(micro-electro-mechanical-system，MEMS)晶粒、訊號處理晶粒(如，數位訊號處理(digital signal processing，DSP)晶粒)、前端晶粒(如，類比前端(analog front-end，AFE)晶粒)、類似物、或其組合。亦，在一些實施例 中，晶粒32可有不同尺寸，以及在其它實施例中，晶粒32可有相同尺寸，但都遠小於標準尺寸0201。
參照圖5，提供一載體基板50。載體基板50的第一面上設置有接合墊52及54，接合墊52及54用以電氣連接。載體基板50的第二面上設置有接合墊56及58，接合墊56及58用以電氣連接，其中第一面對立於第二面。載體基板50內設有導通柱51及53，導通柱51用以電氣連接接合墊52及56，而導通柱53用以電氣連接接合墊54及58。載體基板50包括一導電載板及一非導電載板的一者。在一實施例中，該導電載板包括一印刷電路板(printed circuit board，PCB)。在另一些實施例中，載體基板50可以是玻璃載體基板、陶瓷載體基板、或類似物。在一些實施例中，載體基板50不是半導體基板。更明確來說，載體基板50不是經摻雜或未經摻雜之矽、或絕緣體上半導體(semiconductor-on-insulator，SOI)基板。
參照圖6，形成導電部件60及62在載體基板50上。更具體來說，分別形成導電部件60及62在載體基板50的接合墊52及54上。在一實施例中，利用鋼板或網版印刷製程的一者形成導電部件60及62。在一實施例中，在鋼板或網版印刷製程的該者中，採用的材料包括銀或錫的一者。在一實施例中，採用的材料包括導電膠材，例如透明導電氧化物(transparent conducting oxide，TCO)、石墨烯、或其他適合的材料。在一實施例中，可採用沖壓(stamping)製程或點膠製程。在一實施例中，導電部件60及62包括植球、銀膠或錫膏。在本實施例中，導電部件60及62分別位於接合墊52及54的中央，但本發明不限定於此。導電部60可位於接合墊52上靠近接合墊54的端部，導電部62可位於接合墊54上靠近接合墊52的端部。據此，即使晶粒32的體積進一步縮小使得晶粒32的接合墊34及36間 的距離變小，也無需改變基板50上的接合墊52及54的設計，(例如，無需修改接合墊52及54的設計，以使接合墊52及54更為靠近)，依然能夠搭配相對小的晶粒32。如此一來，製程步驟能夠相對簡單。
參照圖7，將晶粒32接合至導電部件60及62上。更具體來說，將晶粒32的接合墊34及36分別對準導電部件60及62，並將晶粒32的接合墊34及36分別接合至導電部件60及62上。晶粒32透過導電部件60及62而免於透過一導線(例如，圖2的金屬導線28)與載體基板50電性連接。
參照圖8，將晶粒32囊封。更具體來說，藉由一囊封件80將晶粒32、接合墊34及36、導電部件60及62，以及接合墊52及54囊封於囊封件80中。更詳細來說，在實務操作上，圖8所示的結果結構不只包含一個晶粒32，係包含了複數個晶粒32。為了圖式清楚，於圖8僅顯示單一個晶粒32。在一實施例中，不同於圖2的封裝件20係利用封膠(molding)製程囊封晶粒12，該實施例係在，例如一乾膜製程中，利用一保護材料囊封晶粒12。經由一熱處理(curing)程序可以使晶粒32與囊封件80結合，囊封件80則可用來保護基板50，防止基板50發生破片的情況。在一實施例中，保護材料包括聚醯亞胺(polyimide)、環氧樹脂(epoxy resin)、苯並環丁烯樹脂(BCB)或高分子聚合物(polymer)的一者，或者任何合適的材料。在一實施例中，保護材料包括液態光阻。
參照圖9，將晶粒32囊封後的結果結構90(如圖8所示的整個結構)單粒化為一封裝件90。換言之，一個封裝件90含有一個晶粒32。基板50經單粒化後變為經單粒化基板94，而囊封件80經單粒化後變為經單粒化囊封件92。封裝件90的尺寸等同標準尺寸0201。在一些實施例中，封裝件90的尺寸等同標準尺寸0402。在另一些實施例中，封裝件90的尺寸等 同標準尺寸DFN 10。晶粒32的尺寸，例如寬度W3，係遠小於封裝件90的尺寸，例如寬度W3。封裝件90的尺寸，例如寬度W4，本質上等同於標準尺寸的0201。在本發明中，即使想要的封裝件的尺寸為標準尺寸的0201(標準尺寸0402，或標準尺寸DFN 10)，藉由本揭露的製造半導體封裝件的方法，能夠在晶圓的有限面積中，提供更多的晶粒，而該些晶粒在後續的單粒化過程中同樣能夠被單粒化為符合想要的封裝件的尺寸為標準尺寸的0201。有鑑於此，本揭露的製造半導體封裝件的方法能使得成本效率相對提昇。
圖10為根據本發明的製造半導體封裝件的方法100的流程圖。參照圖10，方法100開始於操作102，在操作102中，提供晶圓。方法100接續於操作104，在操作104中，在該晶圓中及在該晶圓上形成具有小於一標準尺寸0201的二分之一的一晶粒。接著，方法100接續於操作106，在操作106中，藉由切割晶圓獲得晶粒。方法100接續於操作108，在操作108中，提供載體基板。方法100接續於操作110，在操作110中，形成導電部件在載體基板上。方法100接續於操作112，在操作112中，接合晶粒至導電部件上。方法100接續於操作114，在操作114中，囊封晶粒。方法100接續於操作116，在操作116中，將晶粒囊封後的結果結構單粒化為封裝，封裝的尺寸等同或大於該標準尺寸0201。
在本揭露中，在囊封晶粒時，不係採用介電係數相對高的封裝膠體，而是採用乾膜製程中的保護材料，或是採用介電係數小於封裝膠體的封裝材料。據此，寄生效應相對不嚴重。此外，本發明係藉由非導電線的導電部件進行晶粒與載體基板間的電性連接，因此相對不容易引起寄生效應。是故，當晶粒操作在高頻時，晶粒受到寄生效應的影響相對小，進而 使得晶粒電氣效能能相對得到提昇。再者，即使想要的封裝件的尺寸為標準尺寸的0201(標準尺寸0402，或標準尺寸DFN 10)，藉由本揭露的製造半導體封裝件的方法，能夠在晶圓的有限面積中，提供更多的晶粒，而該些晶粒在後續的單粒化過程中同樣能夠被單粒化為符合想要的封裝件的尺寸為標準尺寸0201。有鑑於此，本揭露的製造半導體封裝件的方法能使得成本效率相對提昇。
相對的，在一些相關的封裝件製造方法中，係利用封裝膠體進行囊封。然而，由於封裝膠體的介電係數相對高，封裝膠體可能引起相對嚴重的寄生效應(例如寄生電容或寄生電阻)。此外，晶粒系透過金屬導線與載體基板進行電性連接。因此，金屬導線的相對較長的長度也容易引起寄生效應。是故，當晶粒操作在高頻時，晶粒可能受到寄生效應的影響而使得晶粒電氣效能無法提昇。另外，封裝件的封裝可能需要多次的連接介面，相對地增加製程之複雜度。此外，晶粒的封裝除了需要黏晶(die bonding)製程、銲線(wire bonding)製程及封膠(molding)製程等繁複製程才能完成，還需要使用導線架或電路板之基板才能承載晶粒。如此一來，成本無法有效降低。
在一些實施例中，提供一種半導體封裝件的製造方法。該半導體封裝件的製造方法包括提供一晶圓；在該晶圓中及在該晶圓上形成具有小於一標準尺寸0201的二分之一的一晶粒；藉由切割該晶圓獲得該晶粒；以及將該晶粒單粒化為一封裝，其中該封裝的尺寸等同或大於該標準尺寸0201。
雖然本發明已經結合一些實施例進行了說明，但本發明並不限定於此說明書中的特定形式闡述。相反地，本發明的範圍僅受到所附的權利要 求限定。此外，雖然發明特徵可能係結合特定實施例來描述，但本領域的技術人員應當理解所描述的實施例的各種特徵可以根據本發明進行組合。在權利要求中，術語“包含”不排除其他元件或步驟的存在。
此外，儘管複數個手段、元件或方法係被單獨列出，但應可利用例如單一單元、處理器或是控制器來實現。另外，儘管各個特徵可以被包含在不同的權利要求中，但應可被有利地組合，且包含在不同權利要求中並不意味著特徵的組合是不可行的及/或有利的。另外，在一類權利要求中所包含的特徵不意味著限於該類別，而是表示該特徵同樣適用於其它權利要求類別。
此外，特徵在權利要求中的順序並不意味著必須執行的任何特定順序，且方法權利要求中各個步驟的順序並不意味著這些步驟必須按照該順序來執行。相反地，可以以任何合適的順序來執行這些步驟。此外，單數引用不排除多個。因此，「一」、「第一」、「第二」等用語並不排除多個。
本揭露之技術內容及技術特點雖然已揭示如上，然而本揭露所屬技術領域中具有通常知識者應瞭解，在不背離後附申請專利範圍所界定之本揭露精神和範圍內，本揭露之教示及揭示可作種種之替換及修飾。例如，上文揭示之許多裝置或結構可以不同之方法實施或以其它結構予以取代，或者採用上述二種方式之組合。

Claims (11)

  1. 一種半導體封裝件的製造方法，包括： 提供一晶圓； 在該晶圓中及在該晶圓上形成具有小於一標準尺寸0201的二分之一的一晶粒； 藉由切割該晶圓獲得該晶粒；以及 將該晶粒單粒化為一封裝，其中該封裝的尺寸等同或大於該標準尺寸0201。
  2. 如請求項1所述的半導體封裝件的製造方法，其中該晶粒的尺寸為標準尺寸01005。
  3. 如請求項1所述的半導體封裝件的製造方法，其中該封裝的尺寸等同或大於一標準尺寸0402及一標準尺寸DFN 10的一者。
  4. 如請求項1所述的半導體封裝件的製造方法，更包括： 提供一載體基板； 形成一導電部件在該載體基板上； 接合該晶粒至該導電部件上；以及 囊封該晶粒， 其中該晶粒的該單粒化包括：將該晶粒囊封後的一結果結構單粒化為該封裝，該封裝的尺寸等同或大於該標準尺寸0201。
  5. 如請求項4所述的半導體封裝件的製造方法，其中該晶粒的該囊封包括：利用一保護材料囊封該晶粒。
  6. 如請求項5所述的半導體封裝件的製造方法，其中該保護材料包括聚醯亞胺(polyimide)、環氧樹脂(epoxy resin)、苯並環丁烯樹脂(BCB)或高分子聚合物(polymer)的一者。
  7. 如請求項5所述的半導體封裝件的製造方法，其中該載體基板包括一導電載板及一非導電載板的一者。
  8. 如請求項7所述的半導體封裝件的製造方法，其中該導電載板包括一印刷電路板（printed circuit board，PCB）。
  9. 如請求項5所述的半導體封裝件的製造方法，其中該導電部件在該載體基板上的該形成包括利用鋼板或網版印刷製程的一者形成該導電部件。
  10. 如請求項9所述的半導體封裝件的製造方法，其中在鋼板或網版印刷製程的該者中，採用的材料包括銀或錫的一者。
  11. 如請求項5所述的半導體封裝件的製造方法，其中該晶粒透過該導電部件免於透過一導線與該載體基板電性連接。
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