CN107452634B - 封装件结构及其形成方法 - Google Patents

封装件结构及其形成方法 Download PDF

Info

Publication number
CN107452634B
CN107452634B CN201710344109.0A CN201710344109A CN107452634B CN 107452634 B CN107452634 B CN 107452634B CN 201710344109 A CN201710344109 A CN 201710344109A CN 107452634 B CN107452634 B CN 107452634B
Authority
CN
China
Prior art keywords
layer
die
forming
package
redistribution layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201710344109.0A
Other languages
English (en)
Other versions
CN107452634A (zh
Inventor
李孟灿
吴伟诚
林宗澍
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN107452634A publication Critical patent/CN107452634A/zh
Application granted granted Critical
Publication of CN107452634B publication Critical patent/CN107452634B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657Stacked arrangements of devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565Moulds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481Internal lead connections, e.g. via connections, feedthrough structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/03Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19Manufacturing methods of high density interconnect preforms
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20Structure, shape, material or disposition of high density interconnect preforms
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0231Manufacturing methods of the redistribution layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0233Structure of the redistribution layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0237Disposition of the redistribution layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/0502Disposition
    • H01L2224/05024Disposition the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1302Disposition
    • H01L2224/13022Disposition the bump connector being at least partially embedded in the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111Tin [Sn] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/13124Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139Silver [Ag] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155Nickel [Ni] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13164Palladium [Pd] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354Coating
    • H01L2224/13599Material
    • H01L2224/136Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13601Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13609Indium [In] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354Coating
    • H01L2224/13599Material
    • H01L2224/136Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13601Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13611Tin [Sn] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354Coating
    • H01L2224/13599Material
    • H01L2224/136Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13601Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13616Lead [Pb] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354Coating
    • H01L2224/13599Material
    • H01L2224/136Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13639Silver [Ag] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354Coating
    • H01L2224/13599Material
    • H01L2224/136Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13644Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354Coating
    • H01L2224/13599Material
    • H01L2224/136Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13655Nickel [Ni] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354Coating
    • H01L2224/13599Material
    • H01L2224/136Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13663Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13664Palladium [Pd] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/2919Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48105Connecting bonding areas at different heights
    • H01L2224/48106Connecting bonding areas at different heights the connector being orthogonal to a side surface of the semiconductor or solid-state body, e.g. parallel layout
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73257Bump and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73267Layer and HDI connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/0651Wire or wire-like electrical connections from device to substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06517Bump or bump-like direct electrical connections from device to substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06548Conductive via connections through the substrate, container, or encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06555Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06572Auxiliary carrier between devices, the carrier having an electrical connection structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047Details of electrical connections between containers
    • H01L2225/1058Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92Specific sequence of method steps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01022Titanium [Ti]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01074Tungsten [W]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/10251Elemental semiconductors, i.e. Group IV
    • H01L2924/10252Germanium [Ge]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/10251Elemental semiconductors, i.e. Group IV
    • H01L2924/10253Silicon [Si]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/1026Compound semiconductors
    • H01L2924/1027IV
    • H01L2924/10271Silicon-germanium [SiGe]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/1026Compound semiconductors
    • H01L2924/1027IV
    • H01L2924/10272Silicon Carbide [SiC]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/1026Compound semiconductors
    • H01L2924/1032III-V
    • H01L2924/10329Gallium arsenide [GaAs]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/1026Compound semiconductors
    • H01L2924/1032III-V
    • H01L2924/10331Gallium phosphide [GaP]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/1026Compound semiconductors
    • H01L2924/1032III-V
    • H01L2924/10332Indium antimonide [InSb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/1026Compound semiconductors
    • H01L2924/1032III-V
    • H01L2924/10333Indium arsenide [InAs]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/1026Compound semiconductors
    • H01L2924/1032III-V
    • H01L2924/10335Indium phosphide [InP]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/1026Compound semiconductors
    • H01L2924/1032III-V
    • H01L2924/10336Aluminium gallium arsenide [AlGaAs]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/1026Compound semiconductors
    • H01L2924/1032III-V
    • H01L2924/10337Indium gallium arsenide [InGaAs]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/1026Compound semiconductors
    • H01L2924/1032III-V
    • H01L2924/10338Indium gallium phosphide [InGaP]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/1026Compound semiconductors
    • H01L2924/1032III-V
    • H01L2924/10339Aluminium indium arsenide [AlInAs]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/1026Compound semiconductors
    • H01L2924/1032III-V
    • H01L2924/10342Gallium arsenide phosphide [GaAsP]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/1026Compound semiconductors
    • H01L2924/1032III-V
    • H01L2924/10351Indium gallium arsenide phosphide [InGaAsP]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • H01L2924/141Analog devices
    • H01L2924/142HF devices
    • H01L2924/1421RF devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • H01L2924/143Digital devices
    • H01L2924/1431Logic devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • H01L2924/143Digital devices
    • H01L2924/1432Central processing unit [CPU]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • H01L2924/143Digital devices
    • H01L2924/14335Digital signal processor [DSP]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • H01L2924/143Digital devices
    • H01L2924/1434Memory
    • H01L2924/1435Random access memory [RAM]
    • H01L2924/1436Dynamic random-access memory [DRAM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • H01L2924/143Digital devices
    • H01L2924/1434Memory
    • H01L2924/1435Random access memory [RAM]
    • H01L2924/1437Static random-access memory [SRAM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/146Mixed devices
    • H01L2924/1461MEMS
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

凸块下冶金(UBM)和再分布层(RDL)布线结构包括形成在管芯上方的RDL。RDL包括第一导电部分和第二导电部分。在RDL中第一导电部分和第二导电部分处于相同水平。RDL的第一导电部分通过RDL的绝缘材料与RDL的第二导电部分分离。UBM层形成在RDL上方。UBM层包括导电UBM迹线和导电UBM焊盘。UBM迹线将RDL的第一导电部分电连接至RDL的第二导电部分。UBM焊盘电连接至RDL的第二导电部分。导电连接器形成在UBM焊盘上方并且电连接至UBM焊盘。本发明实施例提供一种形成封装件的方法。

Description

封装件结构及其形成方法
技术领域
本发明实施例涉及半导体领域,具体涉及封装件结构及其形成方法。
背景技术
由于各种电子组件(例如,晶体管、二极管、电阻器、电容器等)的集成度不断提高,半导体工业已经经历了快速的发展。对于大部分而言,这种集成密度的改进来自于最小部件尺寸的反复减小,这使得更多的组件集成到给定的区域。关于已经增长的用于缩小电子设备的需求,已经出现更小并且更有创意半导体管芯的封装技术需求。这种封装系统的一个实例是堆叠封装(PoP)技术。在PoP器件中,在底部半导体封装件的顶部上堆叠顶部半导体封装件以提供高水平的集成和组件密度。PoP技术通常能够在生产半导体器件,在印刷电路板(PCB)上PoP技术具有增强的功能和小的占位面积。
发明内容
根据本发明的一个方面,提供一种方法,包括:在第一管芯的第一侧上方形成再分布层(RDL),所述第一管芯具有与所述第一侧相对的第二侧,所述RDL包括第一部分和第二部分,所述第一部分通过所述RDL的绝缘材料与所述第二部分分离开,在所述RDL中所述第一部分和所述第二部分处于相同水平;在所述RDL上方形成凸块下冶金(UBM),所述UBM层包括UBM迹线和UBM焊盘,所述UBM迹线将所述第一部分电连接至所述第二部分,所述UBM焊盘电连接至所述第二部分;以及在所述UBM焊盘上方形成第一导电连接器并且所述第一导电连接器电连接至所述UBM焊盘。
根据本发明的另一方面,提供一种方法,包括:通过以下方法形成第一封装件:使用模制化合物横向地封装第一管芯和第一电连接器,所述第一电连接器相邻于所述第一管芯,所述第一管芯具有第一侧和第二侧,所述第二侧与所述第一侧相对;在所述第一管芯的所述第一侧和所述模制化合物上方形成第一绝缘层;在所述第一绝缘层中形成金属化图案;在所述金属化图案上方形成凸块下冶金(UBM)层;在所述UBM层上方形成第二绝缘层;以及在所述UBM层的第一部分上方形成第一导电连接器,所述UBM层包括通过所述第二绝缘层的第一绝缘区与所述第一部分分离开的第二部分,所述金属化图案包括第三部分,所述第三部分电连接所述UBM层的所述第一部分和所述第二部分,所述第一部分、所述第二部分以及所述第三部分电连接至所述第一导电连接器,并且第二绝缘区插入所述金属化图案的所述第三部分和所述第一绝缘区之间,其中,所述第一绝缘区相比所述第二绝缘区是不同的材料层。
根据本发明的另一方面,提供一种封装件结构,包括:第一封装件,包括:模制化合物,所述模制化合物横向地封装管芯和电连接器,所述电连接器相邻于所述管芯,所述管芯具有第一侧和与所述第一侧相对的第二侧;位于所述管芯的所述第一侧和所述模制化合物上方的再分布层(RDL);位于所述RDL上方的凸块下冶金(UBM);位于所述UBM层上方的绝缘层;以及位于所述UBM层的第一部分上方的第一导电连接器;其中:所述UBM层包括第二部分,所述第二部分通过所述绝缘层的第一绝缘材料与所述第一部分分离开;所述RDL包括第三部分,所述第三部分设置在所述UBM层的所述第一部分和所述第二部分下方并且电连接至所述第一部分和所述第二部分;所述第一部分、所述第二部分以及所述第三部分电连接至所述第一导电连接器;以及插入所述RDL的所述第三部分和所述第一绝缘材料之间的第二绝缘材料,所述第一绝缘材料与所述第二绝缘材料在不同的材料层中。
附图说明
当结合附图进行阅读时,根据下面详细的描述可以最佳地理解本发明的各个方面。应该注意,根据工业中的标准实践,各个部件没有按比例绘制。实际上,为了清楚的讨论,各个部件的尺寸可以任意增加或减少。
图1至图15示出了根据一些实施例的在形成第一封装件结构的工艺期间的中间步骤的截面图。
图16a、图16b以及图16c示出了根据一些实施例的第一封装件结构的各个凸块下冶金(UBM)和再分布层(RDL)布线特点的截面图。
图17示出了根据一些实施例的堆叠封装(POP)结构的截面图。
图18a和图18b是根据一些实施例描述封装和UBM/RDL制造方法的流程图。
具体实施方式
以下公开内容提供了多种不同实施例或实例,以实现本发明的不同特征。下面描述组件和布置的具体实例以简化本发明。当然,这些仅是实例并且不意欲限制本发明。例如,在以下描述中,在第二部件上方或上形成第一部件可包括第一部件和第二部件直接接触的实施例,也可包括形成在第一部件和第二部件之间的附加部件,使得第一部件和第二部件不直接接触的实施例。此外,本发明可以在各个实例中重复参考标号和/或字符。这种重复是为了简化和清楚的目的,并且其本身并不表示所讨论的实施例和/或配置之间的关系。
此外,为了便于描述,本文中可以使用诸如“在...下方”,“在...下面”,“下部”,“在...上面”,“上部”等空间关系术语以便描述如图所示的一个元件或部件与一个或多个其它元件或部件的关系。除了图中所示的方位外,空间关系术语旨在包括在使用或操作过程中器件的不同方位。装置可以以其它方式定位(旋转90度或在其它方位),并且在本文中使用的空间关系描述符可以同样地作相应地解释。
本文描述的实施例可以在一个特定的上下文中进行讨论,即在封装器件中用于凸块下冶金(UBM)和再分布层(RDL)的电气布线。例如,封装件结构的代表性实施方案可包括多输出封装件。本文公开的代表性实施例应用于包括一个或多个集成电路管芯的任何封装件结构。其他实施例预期其它应用,诸如对阅读本发明之后的本领域普通技术人员将显而易见的不同封装件类型和/或不同配置。应该注意,本文讨论的实施例不必示出可能存在于特定结构中的每一个元件或部件。例如,各个组件可以从图中省略,诸如当一个或多个其它组件的论述可以足以描述特定的实施例。
代表性的实施方案的UBM/RDL布线设计改进有关电迁移、敏感性下降损坏,以及热循环完整性的稳定性的相关注意事项。因此,改进的UBM/RDL布线结构是期望提供坚固和可靠的器件封装件结构。
图1至图15示出了根据代表性实施例的在形成第一封装件结构的工艺期间的中间步骤的截面图。图1示出了载体衬底100和在载体衬底100上形成的释放层110。分别示出用于形成第一封装件和第二封装件的第一封装件区800a和第二封装件区800b。
载体衬底100可以是玻璃载体衬底、陶瓷载体衬底等。载体衬底100可以是晶圆,从而使得多个封装件可以基本同时形成在载体衬底100上。释放层110可以由聚合物基材料形成,释放层可以与载体衬底100一起被从在随后步骤中形成的上面的结构中去除。在一些实施例中,释放层110可包括诸如光热转换(LTHC)释放涂层的环氧基热释放材料,当加热时环氧基释放材料失去其粘合性。在其它实施例中,释放层110可包括紫外线(UV)胶,其在暴露于UV光时丧失它的粘合性。释放层110可以作为液体进行分配并且被固化,释放层110可以是层压在载体衬底100上的层压膜等。释放层110的顶面可以是水平或其它处理工艺,以提供可接受的平面特性。
绝缘层120形成在释放层110上。绝缘层120的底面可以与释放层110的顶面接触。在一些实施例中,绝缘层120由聚合物形成,聚合物诸如聚苯并恶唑(PBO),聚酰亚胺,苯并环丁烯(BCB)等。在其它实施例中,绝缘层120由诸如氮化物(例如,氮化硅)、诸如氧化物(例如,氧化硅)、玻璃(例如,磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG))等形成。绝缘材料120可以通过可接受的沉积工艺形成,可接受的沉积工艺诸如旋涂、化学汽相沉积(CVD)、层压等或它们的组合。
如图2中代表性示出的,在绝缘层120上方形成电连接器200a、200a′、200b、200b′。电连接器200a、200a′形成在第一封装区800a中。电连接器200b、200b′形成在第二封装区800b中。如用以形成电连接器200a、200a′、200b、200b′的代表性实例中,在绝缘层120上方形成晶种层(未示出)。在一些实施例中,晶种层包括金属层,晶种层可以是单层或包括由不同的材料形成的多个子层的复合层。在一些实施例中,晶种层包括钛层和位于钛层上方的铜层。例如,可以使用PVD等形成晶种层。在晶种层上形成并且图案化光刻胶。可通过旋转涂布等形成光刻胶并且可将光刻胶暴露于光用于图案化。光刻胶的图案对应于随后形成的电连接器200a、200a′、200b、200b′。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中形成导电材料并且在晶种层的暴露部分上形成导电材料。可通过诸如电镀或化学镀等的镀形成导电材料。导电材料可包括金属,例如,金属是铜、钛、钨、铝等。在光刻胶和晶种层上未形成导电材料的部分去除光刻胶和晶种层。例如,可以通过使用氧等离子体等的可接受的灰化或剥离工艺去除光刻胶。一旦去除光刻胶,诸如通过使用可接受的蚀刻工艺(例如,通过湿法蚀刻或干法蚀刻)去除晶种层的暴露部分。晶种层的剩余部分和导电材料形成电连接器200a、200a′、200b、200b′。
如图3中代表性示出的,集成电路(IC)管芯300a、300b分别通过粘合剂310a、310b粘合至绝缘层120。IC管芯300a、300b分别粘合在第一封装区800a和第二封装区800b中。在其它实施例中,或多或少的IC管芯可以粘合在每个区中。IC管芯300a、300b可包括逻辑管芯(例如,中央处理单元,微控制器等),存储器管芯(例如,动态随机存取存储器(DRAM),静态随机存取存储器(SRAM)等),电源管理管芯(例如,电源管理集成电路(PMIC)),射频(RF)管芯,传感器管芯,微机电系统(MEMS)管芯,信号处理管芯(例如,数字信号处理器(DSP)),前端管芯(例如,模拟前端末端(AFE)管芯),或类似物,或它们的组合。在代表性实施例中,IC管芯300a、300b可以是不同尺寸。在其它实施例中,IC管芯300a、300b可以基本上相同的尺寸。
如提供的,IC管芯300a可包括在IC管芯300a上覆盖的电接触部件320a、320a′(例如,一个或多个接触焊盘)、金属化部件330a,330a′(例如,一个或多个金属化层)、钝化部件340a(例如,一个或多个钝化层)、绝缘部件350a(例如,一个或多个介电层)等,或它们的组合。如提供的,IC管芯300b可包括在IC管芯300a上覆盖的电接触部件320b、320b′、金属化部件330b,330b′、钝化部件340b、绝缘部件350b等,或它们的组合。在代表性实施例中,IC管芯300a、300b的多个金属化部件和绝缘部件可包括一个或多个RDL。
电接触部件320a、320a′、320b、320b′可包括可以外部连接的焊盘,焊盘诸如铝焊盘。焊盘可设置在被称为IC管芯300a、300b的相应的有源侧上。在IC管芯300a、300b上和在部分的焊盘上钝化部件340a、340b可包括钝化膜。形成的开口穿过钝化膜至焊盘。金属化部件330a、330a′、330b、330b′可包括管芯连接件,管芯连接器诸如导电柱(例如,包括诸如铜的金属),在开口中管芯连接器穿过钝化膜并且管芯连接器可机械和电连接至相应的焊盘。例如,可以通过镀等形成管芯连接器。管芯连接器提供电连接至相应的IC管芯300a、300b的集成电路。
绝缘部件350a、350b可包括设置在IC管芯300a、300b的有源侧上的绝缘材料,在IC管芯300a、300b的有源侧上诸如在钝化膜和管芯连接器上。绝缘材料可以横向密封管芯连接器并且绝缘材料横向上与相应的IC管芯300a、300b的横向延伸可基本上具有共同末端。绝缘材料可以是聚合物(例如,PBO、聚酰亚胺、BCB等)、氮化物(诸如氮化硅等)、氧化物(诸如氧化硅、PSG、BSG、BPSG等),或它们的组合,并且,例如,可以通过旋涂、层压、CVD等形成绝缘材料。
在被粘合至绝缘层120之前,可根据可应用的制造工艺对IC管芯300a、300b的加工以在IC管芯300a、300b中形成集成电路。例如,每个IC管芯300a、300b可包括半导体衬底,半导体衬底诸如硅(掺杂或未掺杂)或绝缘体上半导体(SOI)衬底的有源层。半导体衬底可包括:其它半导体材料(诸如锗)、化合物半导体(例如,碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟)、合金半导体(包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP)等。也可以使用诸如多层或梯度衬底的其它衬底。诸如晶体管、二极管、电容器、电阻器、电感器等的器件可以形成在半导体衬底中和/或上并且可以通过互连结构互连以形成集成电路,例如,通过位于半导体衬底上的一个或多个绝缘层中的金属化图案来形成互连结构。
粘合剂310a、310b设置在IC管芯300a、300b的相应的后侧表面上,并且将IC管芯300a、300b粘合至绝缘层120(或在本文中稍后描述的替代实施例中,相应的后侧再分配结构)。粘合剂310a、310b可以是环氧树脂,管芯粘结膜(DAF)等的任何合适的粘合剂。在管芯布置之前可将粘合剂310a、310b应用于IC管芯300a、300b的后侧(诸如应用于相应的半导体晶圆的后侧)。随后可以单独化(例如,诸如通过锯切或切片)IC管芯300a、300b,同时例通过使用粘合剂310a、310b粘合至绝缘层120。
如图4中代表性示出的,在各个组件之间并且在各个组件上形成密封剂400。密封剂400至少可以横向密封IC管芯300a、300b和电连接器200a、200a′、200b、200b′。密封剂400可以是模制化合物、环氧树脂等,并且可以通过压缩模塑、传递模塑等来应用密封剂400。在固化后,密封剂400可以经受研磨或其它平坦化工艺以暴露电连接器200a、200a′、200b、200b′和管芯连接器330a、330a′、330b、330b′。在平坦化工艺后,电连接器200a、200a′、200b、200b′、管芯连接器330a、330a′、330b、330b′,以及密封剂400的顶面可以基本上处于同一平面(或以其它方式共享一个基本上共同的形貌)。在一些实施例中,例如,如果电连接器200a、200a′、200b、200b′和管芯连接器330a、330a′、330b、330b′已经暴露,可省略研磨或平坦化。
图5至图8代表性示出了形成的前侧再分布结构。如图8中代表性示出的,前侧再分布结构包括绝缘层500、600、700、第一金属化图案510、第二金属化图案610、第三金属化图案710,以及绝缘层810。
如图5中代表性实施例示出的,在密封剂400、电连接器200a、200a′、200b、200b′以及管芯连接器330a、330a′、330b、330b′上沉积绝缘层500。在一些实施例中,绝缘层500由聚合物形成并且绝缘层500包括聚合物,聚合物可以是使用光刻研磨而进行图案化的诸如PBO、聚酰亚胺、BCB等的光敏材料。在其它实施例中,绝缘层500可以由氮化物(例如,氮化硅)、氧化物(例如,氧化硅)、玻璃(例如,PSG,PSG,PSG)、介电材料等,或它们的组合形成。绝缘层500可以通过旋涂、层压、CVD等,或它们的组合形成。
图案化绝缘层500以形成开口,以暴露部分的电连接器200a、200a′、200b、200b′以及管芯连接器330a、330a′、330b、330b′。可以通过任何合适的工艺完成图案化,任何合适的工艺诸如通过采用感光材料的光刻曝光,接着通过显影和蚀刻(例如,同向异性蚀刻)。如果绝缘层500是感光材料,根据所需的图案可以通过曝光、显影,以及固化光刻胶材料图案化绝缘层500。
可以在绝缘层500上形成具有通孔的第一金属化图案510。例如,可以在绝缘层500上方和在通过绝缘层500的开口中形成晶种层(未示出)。在一些实施例中,晶种层可包括金属层,晶种层可以是单层或包括由不同的材料形成的多个子层的复合层。在一些实施例中,晶种层包括钛层和位于钛层上方的铜层。例如,可以使用PVD等形成晶种层。可以然后在晶种层上形成并且图案化光刻胶。可通过旋转涂布等形成光刻胶并且可将光刻胶暴露于光用于图案化。光刻胶的图案对应于随后形成的第一金属化图案510。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中形成导电材料并且在晶种层的暴露部分上形成导电材料。可通过诸如电镀或化学镀等的镀形成导电材料。导电材料可包括金属,例如,金属是铜、钛、钨、铝等。然后,去除光刻胶和晶种层的其上未形成导电材料的部分。例如,可以通过使用氧等离子体等的可接受的灰化或剥离工艺去除光刻胶。一旦去除光刻胶,可以诸如通过使用可接受的蚀刻工艺(例如,通过湿法蚀刻或干法蚀刻)去除晶种层的暴露部分。晶种层的剩余部分和导电材料形成具有通孔的第一金属化图案510。在通过绝缘层500至电连接器200a、200a′、200b、200b′以及管芯连接器330a、330a′、330b、330b′的开口中形成第一金属化图案510的通孔。在其它实施例中,可以通过沉积导电层并且图案化导电层形成金属化图案。
如图6中代表性示出的,在第一金属化图案510和绝缘层500上方和上部沉积绝缘层600。在一些实施例中,绝缘层600由聚合物形成,聚合物可以是使用光刻研磨而进行图案化诸如PBO、聚酰亚胺、BCB等的光敏材料。在其它实施例中,绝缘层600可以由氮化物(例如,氮化硅)、氧化物(例如,氧化硅)、玻璃(例如,PSG,PSG,PSG)、介电材料等,或它们的组合形成。绝缘层600可以通过旋涂、层压、CVD等,或它们的组合形成。
然后,介电层600被图案化以形成开口来暴露金属化图案510的一部分。可以通过任何合适的工艺完成图案化,任何合适的工艺诸如通过采用感光材料的光刻曝光,接着通过显影和蚀刻(例如,同向异性蚀刻)。如果绝缘层600是感光材料,根据所需的图案可以通过曝光、显影,以及固化光刻胶材料图案化绝缘层600。
参考如上所述的位于绝缘层500上的具有通孔的第一金属化图案510,可以以基本上类似的方式在绝缘层600上形成具有通孔的第二金属化图案610。
如图7中代表性示出的,在第二金属化图案610和绝缘层600上方和上部沉积绝缘层700。在一些实施例中,绝缘层700由聚合物形成,聚合物可以是使用光刻研磨而进行图案化诸如PBO、聚酰亚胺、BCB等的光敏材料。在其它实施例中,绝缘层700可以由氮化物(例如,氮化硅)、氧化物(例如,氧化硅)、玻璃(例如,PSG,PSG,PSG)、介电材料等,或它们的组合形成。绝缘层700可以通过旋涂、层压、CVD等,或它们的组合形成。
然后,介电层700被图案化以形成开口来暴露第二金属化图案610的一部分。可以通过任何合适的工艺完成图案化,任何合适的工艺诸如通过采用感光材料的光刻曝光,接着通过显影和蚀刻。如果绝缘层700是感光材料,根据所需的图案可以通过曝光、显影,以及固化光刻胶材料图案化绝缘层700。
参考如上所述的位于绝缘层500上的具有通孔的第一金属化图案510,可以以基本上类似的方式在绝缘层700上形成具有通孔的第三金属化图案710。
在代表性实施例中,绝缘层500和第一金属化图案510包括第一RDL,绝缘层600以及第二金属化图案610包括第二RDL,同时第三金属化图案710包括UBM层。因此,代表性前侧再分布结构可包括第一RDL(例如,第一绝缘层500、第一金属化图案510)、第二RDL(例如,第二绝缘层600、第二金属化图案610),以及UBM层(例如,第三绝缘层700、第三金属化图案710)。在各种其它实施例中,更多或更少的绝缘层和金属化图案可以形成在正前侧再分布结构中。如果将要形成更少的绝缘层和金属化图案,那么可以省略以上所讨论的代表性步骤和工艺。如果将要形成更多的绝缘层和金属化图案,那么可以重复以上所讨论的代表性步骤和工艺。本领域普通技术人员将容易理解可以省略或重复哪些步骤和工艺。
因此,各个代表性实施例提供了一种电路布线的路径(随后参考图16a、图16b以及图16c进行讨论),从部分的UBM层,向下至RDL线,向上至UBM层的UBM焊盘,然后从而外部连接器电连接至UBM焊盘。
如图8中代表性示出的,在第三金属化图案710和绝缘层700上方和上部沉积绝缘层810。在一些实施例中,绝缘层810可包括聚合物,聚合物可以是使用光刻研磨而进行图案化诸如PBO、聚酰亚胺、BCB等的光敏材料。在其它实施例中,绝缘层810可以由氮化物(例如,氮化硅)、氧化物(例如,氧化硅)、玻璃(例如,PSG,PSG,PSG)、介电材料等,或它们的组合形成。绝缘层810可以通过旋涂、层压、CVD等,或它们的组合形成。
如图9中代表性示出的,图案化绝缘层810以形成开口900a、900a′、900b、900b′,从而暴露部分的(例如,UBM焊盘部分910a、910a′、910b、910b′)第三金属化图案710。在前侧再分布结构的外侧上形成开口900a、900a′、900b、900b′。可以通过任何合适的工艺完成图案化,任何合适的工艺诸如通过采用感光材料的光刻曝光,接着通过显影和蚀刻。随后形成开口900a、900a′、900b、900b′、仍然通过绝缘层810的材料覆盖第三金属化图案710的迹线部分(随后参考图16C描述的1690),第三金属化图案710为UBM金属化图案。
如图10代表性示出的,导电连接器1000a、1000a′、1000b、1000b′形成在第三金属化图案710的UBM焊盘部分910a、910a′、910b、910b′上并且,导电连接器1000a、1000a′、1000b、1000b′连接至第三金属化图案710的UBM焊盘部分910a、910a′、910b、910b′。导电连接器1000a、1000a′、1000b、1000b′可包括球栅阵列(BGA)连接器,焊球、金属柱、可控坍塌芯片连接(C4)凸块、微凸块、化学镀镍-化学镀钯浸金技术(ENEPIG)形成的凸块等。导电连接器1000a、1000a′、1000b、1000b′可包括诸如焊料、铜、铝、金、镍、银、钯、锡等,或它们的组合的导电材料。在一些实施例中,可使用常用方法(例如,蒸发、电镀、印刷、焊料转移、植球等)通过首先沉积焊料层来形成导电连接器1000a、1000a′、1000b、1000b′。一旦在结构上形成焊料层,就可以执行回流,以将材料成形为期望的凸块形状。在其它实施例中,导电连接器1000a、1000a′、1000b、1000b′可包括通过溅射、印刷、电镀、化学镀、CVD等形成的金属柱(例如,铜柱)。金属柱可以基本上没有焊料并且金属柱具有基本上垂直的侧壁。在一些实施例中,可以在金属柱连接器的顶部上形成金属覆盖层。金属覆盖层可包括通过电镀工艺形成的镍、锡、锡-铅、金、银、钯、铟、镍钯金、镍金等或它们组合。根据代表性实施例,例如,导电连接器1000a、1000a′、1000b、1000b′可包括具有在从约150μm至约300μm范围内的直径的焊球。
如图10中代表性示出的(在此进一步参考图16a、图16b以及图16c的益处和优点),例如,对比于通过单独的UBM层直接布线,提供了一种用于通过位于RDL部分下方的布线UBM电信号的代表性UBM/RDL结构。
可以在形成导电连接器1000a、1000a′、1000b、1000b′后实施检测(例如,识别有缺陷的封装件结构)。然后,如图11中代表性示出的,可以实施载体衬底剥离步骤以从绝缘层120(或根据其它代表性实施例,后侧再分布结构)分离(剥离)载体衬底100。根据一些实施例,剥离包括在释放层110上发射电磁能量(例如,激光,紫外线等),使剥离层110分解,或以其它方式分离,以允许移除载体衬底100。然后翻转该结构并且将该结构放置在带1100上用于进一步的工艺。
根据可选的实施例,在形成电连接器200a、200a′、200b、200b′之前或在载体衬底移除之后,可以在绝缘层120上方形成复数的绝缘层和金属化层,以生产包括一个或多个绝缘层和一个或多个金属化层的后侧再分布结构。所以形成的后侧再分布结构518可包括任意数量的绝缘层、金属化图案以及通孔。例如,可以在通过在下面的绝缘层的开口中形成晶种层和金属化图案的导电材料的金属化图案的形成期间形成通孔。因此,通孔可以互连,并在所得的后侧再分布结构电连接的各种金属化层。参考上面讨论的形成的前侧RDL,可以用相似地方式形成后侧再分布结构。
如图12中代表性示出的,图案化绝缘层120以形成开口1200a、1200a′、1200b、1200b′,从而暴露电连接器200a、200a′、200b、200b′的后侧部分。可以通过任何可接受的工艺完成图案化,任何可接受的工艺诸如通过采用感光材料的光刻曝光,接着通过显影和蚀刻。如果绝缘层120是感光材料,在曝光后可以显影绝缘层120。可选的,可以通过激光钻孔等形成开口1200a、1200a′、1200b、1200b′。
如图13和图14中代表性示出的,切割封装件800a、800b以生产分立封装件。可通过沿划线1400(例如,在相邻的封装区800a和800b之间)锯切实施切割。第一封装区800a从第二封装区800b锯切分离。在一个实施例中,如图15中代表性示出的,在从带1100移除后,分离生产分立封装件800a。根据各种代表性实施例,分立封装件800a可包括集成多输出(InFO)封装件。
根据实施例,如图16a中示出的,分立封装件800a可配置为提供了从第三金属化图案710的UBM焊盘910a(和另外连接的导电连接器1000a)至下面的第二金属化图案610的导电线1615或从下面的第二金属化图案610的导电线1615至第三金属化图案710的UBM焊盘910a的第一电连接器1600、在第二金属化图案610中沿着导电线1615第二电连接器1610,以及从导电线1615至下面的第三金属化图案710的UBM层部分1625或从下面的第三金属化图案710的UBM层部分1625至导电线1615的第三电连接器1620。第二电连接器1610在第一电连接器1600和第三电连接器1620之间提供了的电连接,使得第三金属化图案710的UBM层部分1625是在与UBM焊盘910a电连接(但在其它方面没有机械或物理接触)。所以,在上方的第三金属化图案710的横向设置部分布线之前,电信号可以通过下面的再分布层布线(带来的好处,例如,通过上方的材料层给予的附加保护)。因此,第三金属化图案710除了提供一个或多个至/来自分立封装件800a的外部连接,也在分立封装件800a内提供了电气布线。
如图16b中代表性示出的,封装件800a包括至少横向封装IC管芯300a并且相邻于电连接器200a、200a′的模制化合物400。绝缘层500、600、700设置在IC管芯300a的顶面1630、模制化合物400,以及电连接器200a、200a′的上方。绝缘层500和第一金属化图案510包括第一RDL。绝缘层600和第二金属化图案610包括第二RDL。第三金属化图案710包括UBM层。IC管芯300a的底面1630b(作为用于附接到绝缘层120提供的)包括与后侧绝缘层120接触的粘合层310a。在第三金属化图案710中至少部分的导电连接器1000a设置在UBM焊盘910a的第一部分1640上方和上部。第三金属化图案710的第二部分1650通过绝缘层810的绝缘材料部分1660(第一绝缘区)从UBM焊盘910a的第一部分1640分离。第二金属化图案610的第三部分1670将第一部分1640电连接至第二部分1650。UBM焊盘910a的第一部分1640、第二部分1650,以及第二金属化图案610的第三部分1670电连接至导电连接器1000a,第二金属化图案610为RDL金属化图案。绝缘层700的绝缘材料部分1675(第二绝缘区)设置在第二金属化图案610的第三部分1670和绝缘层810的绝缘材料部分1660之间,并且绝缘材料部分1675插入到第二金属化图案610的第三部分1670和绝缘材料部分1660。
根据代表性实施例,绝缘材料部分1660包括不同于绝缘层700的绝缘材料部分1675的材料层。根据其它代表性实施例,绝缘材料部分1660包括不同于绝缘层700的绝缘材料部分1675的材料。根据其它代表性实施例,UBM焊盘910a的第一部分1640和第二部分1650可包括在相同工艺步骤中形成的相同的材料层。根据代表性方面,第三金属化图案710的UBM焊盘910a的第一部分1640和第二部分1650可包括相同材料。在其它代表性实施例中,UBM焊盘910a的第一部分1640和第二部分1650可包括不同于第二金属化图案610的第三部分1670的材料。在一个实施例中,第二RDL的第二金属化图案610和UBM层的第三金属化图案710电连接IC管芯300a至导电连接器1000a。
如图16c中通常示出的,根据用于提供UBM/RDL布线结构(例如,sans管芯)的代表性实施例提供了一种互连设计。绝缘层600和第二金属化图案610包括RDL。第三金属化图案710包括UBM层。UBM层位于RDL上方。至少部分的第一导电连接器1000a设置在第一UBM焊盘910a上方和上部。导电连接器1000a电连接至第一UBM焊盘910a。第二金属化图案610的第一部分1680通过RDL绝缘层700的绝缘材料1698从第二金属化图案610的第二部分1685分离。UBM迹线1690设置在RDL上方并且UBM迹线在第三金属化图案710中。UBM迹线1690将RDL的第一部分1680电连接至RDL的第二部分1685。第三金属化图案710包括第一UBM焊盘910a。第二金属化图案610的第二部分1685电连接至第一UBM焊盘910a。因此,第二金属化图案610的第一部分1680电连接(通过UBM层的UBM迹线1690、第二的金属化图案610的第二部分1685,以及UBM层的第一UBM焊盘910a)至导电连接器1000a。第三金属化图案710的UBM迹线1690电连接(通过RDL的第二金属化图案610的第二部分1685)至第一UBM焊盘910a。尽管有以上各项,对比于在UBM层的第三金属化图案710内金属部件,UBM迹线1690没有其它方式的物理或机械连接到第一UBM焊盘910a。也就是说,在UBM层内没有可以将UBM迹线1690直接或间接的连接至第一UBM焊盘910a的金属部件的配置和分布。
在代表性实施例中,UBM层的第三金属化图案710包括第二UBM焊盘910a′。至少部分的第二导电连接器1000a′设置在第二UBM焊盘910a′上方和上部。第二导电连接器1000a′电连接至第二UBM焊盘910a′。根据代表性实施例,从第一UBM焊盘910a和第一导电连接器1000a电隔离第二导电连接器1000a′和第二UBM焊盘910a′。在其它代表性实施例中,从在下面的RDL中的第一部分1680电隔离第二UBM焊盘910a′和第二导电连接器1000a′。在进一步代表性实施例中,从第二导电连接器1000a′和第二UBM焊盘910a′电隔离UBM迹线1690。
根据代表性实施例,绝缘层700的绝缘材料1698包括不同于绝缘层810的绝缘材料的材料层。根据代表性实施例,绝缘层700的绝缘材料1698包括不同于绝缘层810的绝缘材料的材料。根据代表性实施例,第二金属化图案610的第一部分1680和第二部分1685可包括在相同的工艺步骤中形成的相同材料层。根据代表性方面,第二金属化图案610的第一部分1680和第二部分1685可包括相同材料。在其它代表性实施例中,第一部分1680和第二部分1685可包括不同于形成UBM迹线1690的材料的材料。
因此,各个代表性实施例提供了一种电路布线的路径,从部分的UBM层,至下面的RDL线,至上面的UBM层的UBM焊盘,然后从而外部连接器电连接至UBM焊盘。
图17代表性示出了一种堆叠封装(PoP)结构1700,堆叠封装(PoP)结构1700包括封装件800(或称为第一封装件)、第二封装件1710,以及衬底1770。第二封装件1710包括衬底1720和一个或多个连接至衬底1720的堆叠管芯1730(1730a和1730b)。在一个实施例中,衬底1720基于诸如玻璃纤维增强树脂芯的绝缘芯。代表性芯材料包括诸如FR4的玻璃纤维树脂。可选地用于芯材料的包括双马来酰亚胺三嗪(BT)树脂或可替代地、其它的印刷电路板(PCB)材料或薄膜。建立的诸如味之素(Ajinomoto)积聚膜(ABF)或其它层压件的薄膜可用于衬底1720。
衬底1720可包括有源和无源器件(未在图17中示出)。作为本领域的普通技术人员将会明白,可以使用各种器件(诸如晶体管、电容器、电阻器、电感器等)来提供用于PoP结构1700的设计的结构和功能要求。可以使用任何合适的方法来形成这样的器件。
衬底1720也可包括金属化层(未示出)和通孔1752。金属化层可以形成在有源和无源器件上方,并且金属化层设计为连接各个器件组件以形成功能电路。金属化层可以由绝缘材料(例如,低k介电)和导电材料(例如,铜)的交替层形成,具有通孔的金属化层互连导电材料的层,并且可使用任何合适的工艺(诸如沉积、镶嵌、双镶嵌等)形成金属化层。在一些实施例中,衬底1720是基本上不含有源和无源器件。
衬底1720在衬底1720的第一侧上可具有接合焊盘1740以将接合焊盘1740连接至堆叠管芯1730,同时在衬底1720的第二侧上可具有接合焊盘1755以将接合焊盘1755连接至导电连接器1760,衬底1720的第二侧与第一侧是相对的。通过导线接合件1745,不过也可使用诸如导电凸块的其它的连接方式将堆叠管芯1730连接至衬底1720。在一个实施例中,例如,堆叠管芯1730可包括堆叠式存储管芯。例如,堆叠式存储管芯1730可包括低功耗(LP)双倍数据速率(DDR)存储模块,低功耗(LP)双倍数据速率(DDR)存储模块诸如LPDDR1、LPDDR2、LPDDR3等存储模块,或它们的组合物。在一些实施例中,堆叠管芯1730和导线接合件1745可由模制材料1750包封。
在形成第二封装件1710后,通过导电连接器1760、接合焊盘1755,以及电连接器200的方式将第二封装件1710接合至第一封装件800。在一些实施例中,可通过导线接合件1745、接合焊盘1740和1755、通孔1752、导电连接器1760,以及电连接器200将堆叠式存储管芯1730接合至IC管芯300。虽然导电连接器1760和1000不需要是相同的,上面描述的导电连接器1760可相似于导电连接器1000,并且这里不重复的说明。
半导体封装件1700包括安装至衬底1770的封装件800和1710。衬底1770可以被称为封装件衬底1770。通过第一封装件800使用导电连接器1000将第二封装件1710安装至封装件衬底1770。封装件衬底1770可包括有源和无源器件(未在图17中示出)。作为本领域的普通技术人员将会明白,可以使用各种器件(诸如晶体管、电容器、电阻器、电感器等)来提供用于PoP结构1700的设计的结构和功能要求,并且可以使用任何合适的方法形成PoP结构1700。在一些实施例中,封装件衬底1770是基本上不含有源和无源器件。
如图18a中一般性示出的,一种用于形成PoP结构1700的代表性方法1800,对于形成第一封装件开始于第一工艺1805。在步骤1810中,相邻于管芯形成一个或多个电连接器。在步骤1812中,使用封装材料(例如,模制化合物)封装管芯和电连接器。在步骤1814中,在管芯和电连接器上方形成第一绝缘层。在步骤1816中,在第一绝缘层中形成RDL。在步骤1818中,在RDL上方形成UBM层。在步骤1820中,在UBM上方形成第二绝缘层。在步骤1822中,在至少部分的UBM层上方形成一个或多个导电连接器。在代表性实施例中,第一工艺1805包括步骤1810、1812、1814、1816、1818、1820以及1822。可以继续进行步骤1830工艺,其中,第一封装件连接至第二封装件。在步骤1840中,结合PoP结构的第一封装件连接至衬底。
如图18b中一般性示出的,一种用于形成UBM/RDL布线结构的代表性方法1850,对于形成第一器件结构开始于第一工艺1855。在步骤1858中,提供了一种管芯。在步骤1860中,相邻于管芯可选择地(如在图18b中虚线表示的)形成一个或多个电连接器。在步骤1862中,使用封装材料(例如,模制化合物)可选择地封装管芯和电连接器。在步骤1864中,在管芯上方形成第一绝缘层。在步骤1866中,在第一绝缘层中形成RDL。在步骤1868中,在RDL上方形成UBM层。在步骤1870中,在UBM上方形成第二绝缘层。在步骤1872中,在至少部分的UBM层上方形成一个或多个导电连接器。在代表性实施例中,第一工艺1855包括步骤1858、1864、1866、1868、1870以及1872。在其它代表性实施例中,第一工艺1855包括步骤1858、1864、1866、1868、1870、1872,以及可选择地步骤1860和1862的一个或两个,其中,可以继续进行步骤1880工艺,第一器件结构可以可选择地连接至第二器件结构。在步骤1890中,复合器件包括连接的第二器件结构和第一器件结构可以可选择性地连接至衬底。
代表性器件和方法的实施例可以具有多种好处。例如,根据代表性实施例,利用布线设计(通常设计上直接采用UBM布线)使球疲劳减少了约67%。例如,根据代表性实施例,利用布线设计(通常设计上直接采用UBM布线)使预测封装件寿命增加了约82%。此外,根据代表性实施例,对于在110℃的操作温度下进行10年处模拟故障,电布线设计(通常设计上直接采用UBM布线)的电流容量提高了约300%。关于具体实施例已经描述了益处、其它优点以及对于问题的解决方案;然而,益处、优点、问题的解决方案,以及可能导致任何益处,优点,或解决方案发生或变得更显着的任何元件不应被解释为关键的、必需的,或必要的部件或组件。
根据代表性实施例,一种方法,包括如下步骤:在第一管芯的第一侧上方形成再分布层(RDL),第一管芯具有相对于第一侧的第二侧,RDL包括第一部分和第二部分,第一部分通过RDL的绝缘材料从第二部分分离,在RDL中第一部分和第二部分处于相同的水平面;在RDL上方形成凸块下冶金(UBM),UBM层包括UBM迹线和UBM焊盘,UBM迹线电连接第一部分至第二部分,UBM焊盘电连接至第二部分;以及在UBM焊盘上方形成第一导电连接器并且第一导电连接器电连接至UBM焊盘。相邻于第一管芯形成第一电连接器。RDL和UBM焊盘电连接第一管芯至第一导电连接器。使用模制化合物至少横向封装的第一管芯和第一电连接器以形成第一封装件。使用第二组导电连接器连接第二封装件至第一封装件,第二封装件邻近于第一管芯的第二侧,第二封装件包括第二管芯。第一部分和第二部分可包括相同的材料。可在相同的步骤中形成第一部分和第二部分。可以在UBM层上方形成绝缘层。
根据其它代表性实施例,一种方法,包括:形成第一封装件,包括:使用模制化合物至少横向封装第一管芯和第一电连接器,第一电连接器相邻第一管芯,第一管芯具有第一侧和第二侧,第二侧相对于第一侧;在第一管芯和模制化合物上方形成第一绝缘层;在第一绝缘层中形成金属化图案;在金属化图案上方形成凸块下冶金(UBM)层;在UBM层上方形成绝缘层;以及在UBM层的第一部分上方形成第一导电连接器,UBM层包括第二部分通过第二绝缘层的第一绝缘区从第一部分分离,金属化图案包括第三部分,第三部分电连接UBM层的第一部分和第二部分,第一部分、第二部分,以及第三部分电连接至第一导电连接器,并且UBM层的绝缘材料插入在第三部分和绝缘材料之间,其中,第一绝缘区相比第二绝缘区是不同的材料层。金属化图案和UBM层电连接第一管芯至第一导电连接器。UBM层可以是共形沉积。第一部分和第二部分可包括相同的材料。第一部分和第二部分可包括不同于第三部分的材料。可在相同的步骤中形成第一部分和第二部分。第一部分可包括UBM焊盘。使用第二组导电连接器将第二封装件连接至第一封装件,第二封装件邻近于第一管芯的第二侧。可以使用第一导电连接器将衬底连接至第一封装件,并且,第二封装件包括第二管芯。
根据其它代表性实施例,一种具有第一封装件的封装件结构,第一封装件包括:模制化合物,模制化合物横向封装管芯和电连接器,电连接器相邻于管芯,管芯具有第一侧和第一侧相对侧的第二侧;再分布层(RDL),再分布层(RDL)位于管芯的第一侧和模制化合物上方;凸块下冶金(UBM)层,凸块下冶金(UBM)层位于RDL上方;绝缘层,绝缘层位于UBM层上方;以及第一导电连接器,第一导电连接器位于UBM层的第一部分上方;其中:UBM层包括第二部分,第二部分通过绝缘层的第一绝缘材料与第一部分分离;RDL包括第三部分,第三部分设置在UBM层的第一部分和第二部分下方并且第三部分电连接至UBM层的第一部分和第二部分;第一部分、第二部分,以及第三部分电连接至第一导电连接器;以及UBM层的绝缘材料,该绝缘材料插入至第三部分和绝缘材料之间,该绝缘材料相比于绝缘材料在不同的材料层中。RDL和UBM焊盘电连接管芯至第一导电连接器。使用第二组导电连接器将第二封装件连接至第一封装件,第二封装件邻近于第一管芯的第二侧。
根据本发明的一个方面,提供一种方法,包括:在第一管芯的第一侧上方形成再分布层(RDL),第一管芯具有与第一侧相对的第二侧,RDL包括第一部分和第二部分,第一部分通过RDL的绝缘材料与第二部分分离开,在RDL中第一部分和第二部分处于相同水平;在RDL上方形成凸块下冶金(UBM),UBM层包括UBM迹线和UBM焊盘,UBM迹线将第一部分电连接至第二部分,UBM焊盘电连接至第二部分;以及在UBM焊盘上方形成第一导电连接器并且第一导电连接器电连接至UBM焊盘。
根据本发明的一个实施例,方法还包括相邻于第一管芯形成第一电连接器。
根据本发明的一个实施例,RDL和UBM焊盘将第一管芯电连接至第一导电连接器。
根据本发明的一个实施例,方法还包括使用模制化合物至少横向地封装第一管芯和第一电连接器以形成第一封装件。
根据本发明的一个实施例,方法还包括使用第二组导电连接器将第二封装件连接至第一封装件,第二封装件接近第一管芯的第二侧,第二封装件包括第二管芯。
根据本发明的一个实施例,第一部分和第二部分包括相同的材料。
根据本发明的一个实施例,在相同的步骤中形成第一部分和第二部分。
根据本发明的一个实施例,方法还包括在UBM迹线上方形成绝缘层。
根据本发明的另一方面,提供一种方法,包括:通过以下方法形成第一封装件:使用模制化合物横向地封装第一管芯和第一电连接器,第一电连接器相邻于第一管芯,第一管芯具有第一侧和第二侧,第二侧与第一侧相对;在第一管芯的第一侧和模制化合物上方形成第一绝缘层;在第一绝缘层中形成金属化图案;在金属化图案上方形成凸块下冶金(UBM)层;在UBM层上方形成第二绝缘层;以及在UBM层的第一部分上方形成第一导电连接器,UBM层包括通过第二绝缘层的第一绝缘区与第一部分分离开的第二部分,金属化图案包括第三部分,第三部分电连接UBM层的第一部分和第二部分,第一部分、第二部分以及第三部分电连接至第一导电连接器,并且第二绝缘区插入金属化图案的第三部分和第一绝缘区之间,其中,第一绝缘区相比第二绝缘区是不同的材料层。
根据本发明的一个实施例,金属化图案和UBM层将第一管芯电连接至第一导电连接器。
根据本发明的一个实施例,UBM层被共形地沉积。
根据本发明的一个实施例,UBM层的第一部分和第二部分包括相同的材料。
根据本发明的一个实施例,UBM层的第一部分和第二部分包括不同于金属化图案的第三部分的材料。
根据本发明的一个实施例,在相同的步骤中形成UBM层的第一部分和第二部分。
根据本发明的一个实施例,方法还包括使用第二组导电连接器将第二封装件连接至第一封装件,第二封装件接近第一管芯的第二侧。
根据本发明的一个实施例,方法还包括使用第一导电连接器将衬底连接至第一封装件,并且其中,第二封装件包括第二管芯。
根据本发明的另一方面,提供一种封装件结构,包括:第一封装件,包括:模制化合物,模制化合物横向地封装管芯和电连接器,电连接器相邻于管芯,管芯具有第一侧和与第一侧相对的第二侧;位于管芯的第一侧和模制化合物上方的再分布层(RDL);位于RDL上方的凸块下冶金(UBM);位于UBM层上方的绝缘层;以及位于UBM层的第一部分上方的第一导电连接器;其中:UBM层包括第二部分,第二部分通过绝缘层的第一绝缘材料与第一部分分离开;RDL包括第三部分,第三部分设置在UBM层的第一部分和第二部分下方并且电连接至第一部分和第二部分;第一部分、第二部分以及第三部分电连接至第一导电连接器;以及插入RDL的第三部分和第一绝缘材料之间的第二绝缘材料,第一绝缘材料与第二绝缘材料在不同的材料层中。
根据本发明的一个实施例,RDL和UBM层将管芯电连接至第一导电连接器。
根据本发明的一个实施例,封装件结构还包括使用第二组导电连接器连接至第一封装件的第二封装件,第二封装件接近第一管芯的第二侧。
根据本发明的一个实施例,封装件结构还包括使用第一导电连接器连接至第一封装件的衬底,并且其中,第二封装件包括第二管芯。
上述内容概括了几个实施例的特征使得本领域技术人员可更好地理解本发明的各个方面。本领域技术人员应该理解,可以很容易地使用本发明作为基础来设计或更改其它的处理和结构以用于达到与本发明所介绍实施例相同的目的和/或实现相同优点。本领域技术人员也应该意识到,这些等效结构并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,可以进行多种变化、替换以及改变。

Claims (24)

1.一种形成封装件结构的方法,包括:
设置相邻于位于聚合物层上的第一管芯的第一电连接器,所述聚合物层覆盖载体衬底;
在设置相邻于所述第一管芯的所述第一电连接器之后,使用模制化合物封装所述第一电连接器和所述第一管芯;
在封装所述第一电连接器和所述第一管芯之后,在所述第一管芯的第一侧上方形成再分布层,所述第一管芯具有与所述第一侧相对的第二侧,所述再分布层包括第一部分和第二部分,所述再分布层的所述第一部分通过所述再分布层的绝缘材料的第一部分与所述再分布层的所述第二部分分离开,所述绝缘材料的所述第一部分从所述再分布层的所述第一部分延伸至所述再分布层的所述第二部分,所述再分布层的所述第一部分和所述再分布层的所述第二部分处于相同水平;
在形成所述再分布层之后,在所述再分布层上方形成凸块下冶金层,所述凸块下冶金层包括凸块下冶金迹线和凸块下冶金焊盘,所述凸块下冶金迹线的下部通过所述再分布层的绝缘材料的第二部分与所述凸块下冶金焊盘的下部分离开,所述再分布层的绝缘材料的所述第二部分与所述再分布层的所述第二部分的最上表面接触,绝缘材料的所述第一部分的最上表面全部被所述凸块下冶金迹线覆盖,并且绝缘材料的所述第一部分填充由所述凸块下冶金迹线下方至在所述再分布层的所述第一部分的最底表面和所述再分布层的所述第二部分的最底表面之间连续延伸的直线所限定的所述再分布层的全部区域,所述凸块下冶金层的所述凸块下冶金迹线将所述再分布层的所述第一部分电连接至所述再分布层的所述第二部分并且所述再分布层的所述第二部分将所述凸块下冶金迹线电连接至所述凸块下冶金焊盘,其中,所述再分布层的所述第一部分和所述再分布层的所述第二部分的最上表面处于第一水平,并且其中,所述凸块下冶金迹线和所述凸块下冶金焊盘的最上表面处于第二水平,所述第二水平高于所述第一水平;以及
在形成所述凸块下冶金层之后,在所述凸块下冶金层上方沉积钝化层,其中,所述钝化层的部分将所述凸块下冶金迹线的上部与所述凸块下冶金焊盘的上部分离开,并且所述再分布层的绝缘材料的第二部分将钝化层部分与所述再分布层的所述第二部分分离开;
在沉积所述钝化层之后,在所述凸块下冶金焊盘上方形成第一导电连接器并且所述第一导电连接器电连接至所述凸块下冶金焊盘,所述再分布层的所述第一部分、所述凸块下冶金迹线、所述再分布层的所述第二部分和所述凸块下冶金焊盘电连接至所述第一导电连接器,其中,所述第一电连接器在垂直方向上直接位于所述再分布层的所述第一部分下面;
去除所述载体衬底并且通过所述聚合物层暴露所述第一电连接器。
2.根据权利要求1所述的形成封装件结构的方法,其中,所述再分布层和所述凸块下冶金焊盘将所述第一管芯电连接至所述第一导电连接器。
3.根据权利要求2所述的形成封装件结构的方法,还包括使用模制化合物至少横向地封装所述第一管芯和所述第一电连接器以形成第一封装件。
4.根据权利要求3所述的形成封装件结构的方法,还包括使用第二组导电连接器将第二封装件连接至所述第一封装件,所述第二封装件接近所述第一管芯的所述第二侧,所述第二封装件包括第二管芯。
5.根据权利要求1所述的形成封装件结构的方法,其中,所述再分布层的第一部分和所述再分布层的第二部分包括相同的材料。
6.根据权利要求5所述的形成封装件结构的方法,其中,在相同的步骤中形成所述再分布层的第一部分和所述再分布层的第二部分。
7.根据权利要求1所述的形成封装件结构的方法,还包括在所述凸块下冶金迹线上方形成绝缘层。
8.一种形成封装件结构的方法,包括:
通过以下方法形成第一封装件:
使用模制化合物横向地封装第一管芯和第一电连接器,所述第一电连接器相邻于所述第一管芯,所述第一管芯具有第一侧和第二侧,所述第二侧与所述第一侧相对,其中,当所述第一管芯和所述第一电连接器位于载体衬底上方的聚合物层的上方时,发生所述横向地封装;
在使用模制化合物横向地封装所述第一管芯和所述第一电连接器之后,在所述第一管芯的所述第一侧和所述模制化合物上方形成第一绝缘层;
在形成所述第一绝缘层之后,在所述第一绝缘层中形成金属化图案,其中,所述金属化图案包括第一部分和通过所述第一绝缘层的第一绝缘区域与所述第一部分分离开的第二部分;
在形成所述金属化图案之后,在所述金属化图案上方形成凸块下冶金层,其中:
所述凸块下冶金层包括凸块下冶金焊盘;
所述第一部分与第二部分处于所述金属化图案的相同的第一水平;
所述金属化图案和所述凸块下冶金焊盘的最上表面处于相同的第二水平;以及
所述凸块下冶金层包括电连接至所述第一部分和所述第二部分的第三部分,其中,所述第三部分形成在覆盖所述第一绝缘区域的第二水平处,并且形成为具有在所述第一水平处与所述第一部分接触的一端以及形成为具有与所述一端相对的在所述第一水平处与所述第二部分接触的另一端,所述第三部分与所述凸块下冶金焊盘是与所述第一部分和第二部分的导电材料不同的导电材料,并且其中,所述第一绝缘区域的最上表面全部被所述凸块下冶金层的所述第三部分覆盖,并且所述第一绝缘区域填充由所述凸块下冶金层的所述第三部分下方至在所述金属化图案的所述第一部分的最底表面和所述金属化图案的所述第二部分的最底表面之间连续延伸的直线所限定的所述金属化图案的全部区域;
在形成所述凸块下冶金层之后,在所述凸块下冶金层上方形成第二绝缘层;以及
在形成所述第二绝缘层之后,在所述凸块下冶金层上方形成第一导电连接器,其中,所述第一部分、所述第二部分、所述第三部分以及所述凸块下冶金焊盘电连接至所述第一导电连接器,并且其中,所述凸块下冶金层的所述第三部分直接位于所述第一电连接器上面;
在形成所述第二绝缘层之后,去除所述载体衬底;
在去除所述载体衬底之后,形成穿过所述聚合物层的开口以暴露所述第一电连接器;
在形成所述第一导电连接器之后,识别有缺陷的封装件结构。
9.根据权利要求8所述的形成封装件结构的方法,其中,所述金属化图案和所述凸块下冶金层将所述第一管芯电连接至所述第一导电连接器。
10.根据权利要求8所述的形成封装件结构的方法,其中,所述凸块下冶金层被共形地沉积。
11.根据权利要求8所述的形成封装件结构的方法,其中,所述第一部分和所述第二部分包括相同的材料。
12.根据权利要求11所述的形成封装件结构的方法,其中,所述第一部分和所述第二部分包括不同于所述第三部分的材料。
13.根据权利要求8所述的形成封装件结构的方法,其中,在相同的步骤中形成所述第一部分和所述第二部分。
14.根据权利要求8所述的形成封装件结构的方法,还包括使用第二组导电连接器将第二封装件连接至所述第一封装件,所述第二封装件接近所述第一管芯的所述第二侧。
15.根据权利要求14所述的形成封装件结构的方法,还包括使用所述第一导电连接器将衬底连接至所述第一封装件,并且其中,所述第二封装件包括第二管芯。
16.一种封装件结构,包括:
第一封装件,包括:
模制化合物,所述模制化合物横向地封装管芯和电连接器,所述电连接器相邻于所述管芯,所述管芯具有第一侧和与所述第一侧相对的第二侧;
位于所述管芯的所述第一侧和所述模制化合物上方的再分布层;
位于所述再分布层上方的凸块下冶金层;
位于所述凸块下冶金层上方的绝缘层;以及
位于所述凸块下冶金层的第一部分上方的第一导电连接器;
其中:
所述凸块下冶金层包括第二部分,所述第二部分通过所述绝缘层的第一绝缘材料与所述第一部分分离开;
所述再分布层包括第三部分,所述第三部分设置在所述凸块下冶金层的所述第一部分和所述第二部分下方并且电连接至所述第一部分和所述第二部分,所述第一绝缘材料填充由所述再分布层的所述第三部分下方至在所述凸块下冶金层的所述第一部分的最底表面和所述凸块下冶金层的所述第二部分的最底表面之间连续延伸的直线所限定的全部区域;
所述第一部分、所述第二部分以及所述第三部分电连接至所述第一导电连接器;以及
插入所述再分布层的所述第三部分和所述第一绝缘材料之间的第二绝缘材料,所述第一绝缘材料与所述第二绝缘材料在不同的材料层中。
17.根据权利要求16所述的封装件结构,其中,所述再分布层和所述凸块下冶金层将所述管芯电连接至所述第一导电连接器。
18.根据权利要求16所述的封装件结构,还包括使用第二组导电连接器连接至所述第一封装件的第二封装件,所述第二封装件接近所述管芯的所述第二侧。
19.根据权利要求18所述的封装件结构,还包括使用所述第一导电连接器连接至所述第一封装件的衬底,并且其中,所述第二封装件包括第二管芯。
20.一种形成封装件结构的方法,包括:
通过以下方法形成第一封装件:
设置相邻于位于聚合物层上方的管芯的第一电连接器,所述管芯具有第一侧和与所述第一侧相对的第二侧,其中,在设置所述第一电连接器期间,所述聚合物层位于载体衬底上方;
在设置相邻于所述管芯的所述第一电连接器之后,使用模制化合物横向地封装所述管芯和所述第一电连接器;
在横向地封装所述管芯和所述第一电连接器之后,在所述管芯的所述第一侧和所述模制化合物上方形成再分布层;
在形成所述再分布层之后,在所述再分布层上方设置凸块下冶金层;
在所述再分布层上方设置所述凸块下冶金层之后,在所述凸块下冶金层上方形成绝缘层;以及
在形成所述绝缘层之后,在所述凸块下冶金层的第一部分上方设置第一导电连接器,其中:
所述凸块下冶金层包括通过所述绝缘层的第一绝缘材料与所述第一部分分离开的第二部分,其中,所述第二部分具有背离所述管芯的顶面,所述顶面包括第一凹进和第二凹进,其中,所述第一绝缘材料延伸至并填充所述第一凹进和所述第二凹进并且延伸以与所述第一导电连接器和所述凸块下冶金层的所述第一部分的表面物理接触,所述表面还与所述第一导电连接器物理接触;
所述第一部分包括所述凸块下冶金层的凸块下冶金焊盘,并且,所述第二部分包括所述凸块下冶金层的凸块下冶金迹线并且不包括所述凸块下冶金焊盘或另一凸块下冶金焊盘;
所述再分布层包括设置在所述凸块下冶金层下方并且电连接至所述凸块下冶金层的所述第一部分和所述第二部分的第三部分,并且所述再分布层包括设置在所述凸块下冶金层下方的第四部分,所述凸块下冶金迹线电连接至所述再分布层的所述第三部分和所述第四部分,所述第一凹进覆盖与所述凸块下冶金迹线物理接触的所述再分布层的所述第四部分的区域,并且所述第二凹进覆盖与凸块下冶金层的所述第二部分物理接触的所述再分布层的所述第三部分的区域;
所述第一部分、所述第二部分、所述第三部分以及所述第四部分电连接至所述第一导电连接器,其中,第一点在第一方向上覆盖第二点,所述第一方向与所述管芯的侧壁平行,所述第一点位于所述第一部分、所述第二部分、所述第三部分和所述第四部分中的一个内,并且所述第二点位于所述第一电连接器的第一表面上;
所述第一部分和所述第二部分的最上表面与所述凸块下冶金层的最上表面处于相同的水平;
第二绝缘材料插入所述再分布层的所述第三部分和所述第一绝缘材料之间;
所述第二绝缘材料的第一绝缘区域的最上表面全部被所述凸块下冶金层的所述第二部分覆盖,并且所述第二绝缘材料的第一绝缘区域填充由所述凸块下冶金层的所述第二部分下方至在所述再分布层的所述第三部分的最底表面和所述再分布层的所述第四部分的最底表面之间连续延伸的直线所限定的再分布层图案的全部区域;
再分布层所述第一绝缘材料与所述第二绝缘材料位于不同的材料层中;以及
去除所述载体衬底并通过所述聚合物层暴露所述第一电连接器。
21.根据权利要求20所述的形成封装件结构的方法,还包括通过所述再分布层和所述凸块下冶金层将所述管芯电连接至所述第一导电连接器。
22.根据权利要求20所述的形成封装件结构的方法,还包括使用第二组导电连接器将第二封装件连接至所述第一封装件,所述第二封装件接近所述管芯的所述第二侧。
23.根据权利要求22所述的形成封装件结构的方法,还包括使用所述第一导电连接器将衬底连接至所述第一封装件,其中,所述第二封装件包括第二管芯。
24.根据权利要求23所述的形成封装件结构的方法,其中,所述第一绝缘材料包括与所述第二绝缘材料不同的材料。
CN201710344109.0A 2016-05-17 2017-05-16 封装件结构及其形成方法 Active CN107452634B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/157,312 US20170338204A1 (en) 2016-05-17 2016-05-17 Device and Method for UBM/RDL Routing
US15/157,312 2016-05-17

Publications (2)

Publication Number Publication Date
CN107452634A CN107452634A (zh) 2017-12-08
CN107452634B true CN107452634B (zh) 2021-03-09

Family

ID=60330440

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710344109.0A Active CN107452634B (zh) 2016-05-17 2017-05-16 封装件结构及其形成方法

Country Status (2)

Country Link
US (3) US20170338204A1 (zh)
CN (1) CN107452634B (zh)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016192447A (ja) * 2015-03-30 2016-11-10 株式会社東芝 半導体装置
KR102019352B1 (ko) * 2016-06-20 2019-09-09 삼성전자주식회사 팬-아웃 반도체 패키지
US10224298B2 (en) * 2016-09-02 2019-03-05 Advanced Semiconductor Engineering, Inc. Semiconductor package device having glass transition temperature greater than binding layer temperature
DE102018123492A1 (de) * 2018-03-26 2019-09-26 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleiterbauelement und herstellungsverfahren
US11488881B2 (en) * 2018-03-26 2022-11-01 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US11380616B2 (en) * 2018-05-16 2022-07-05 Intel IP Corporation Fan out package-on-package with adhesive die attach
KR102073295B1 (ko) 2018-06-22 2020-02-04 삼성전자주식회사 반도체 패키지
US10515848B1 (en) 2018-08-01 2019-12-24 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method
CN108766489B (zh) * 2018-08-01 2023-08-08 灿芯半导体(上海)股份有限公司 一种用于倒装封装的ddr接口
DE102019113476A1 (de) * 2018-08-30 2020-03-05 Taiwan Semiconductor Manufacturing Company, Ltd. Halbleiter-bauelement und verfahren zu dessen herstellung
US11171090B2 (en) 2018-08-30 2021-11-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US11374149B2 (en) * 2019-05-09 2022-06-28 Samsung Electronics Co., Ltd. Method of manufacturing display device and source substrate structure
WO2020245416A1 (en) 2019-06-07 2020-12-10 Rockley Photonics Limited Silicon photonic interposer with two metal redistribution layers
TWI768294B (zh) 2019-12-31 2022-06-21 力成科技股份有限公司 封裝結構及其製造方法
JP7512109B2 (ja) * 2020-07-20 2024-07-08 キオクシア株式会社 半導体装置の製造方法
TWI807827B (zh) * 2022-05-13 2023-07-01 矽品精密工業股份有限公司 電子封裝件及其製法
US20240243056A1 (en) * 2023-01-17 2024-07-18 Qualcomm Incorporated Integrated circuit (ic) package employing a re-distribution layer (rdl) substrate(s) with photosensitive dielectric layer(s) for increased package rigidity, and related fabrication methods

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7977783B1 (en) * 2009-08-27 2011-07-12 Amkor Technology, Inc. Wafer level chip size package having redistribution layers
CN104795371A (zh) * 2014-01-17 2015-07-22 台湾积体电路制造股份有限公司 扇出型封装件及其形成方法
CN105321912A (zh) * 2014-05-30 2016-02-10 台湾积体电路制造股份有限公司 用于激光标刻的金属焊盘

Family Cites Families (120)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6977025B2 (en) * 1996-08-01 2005-12-20 Loctite (R&D) Limited Method of forming a monolayer of particles having at least two different sizes, and products formed thereby
US6402876B1 (en) * 1997-08-01 2002-06-11 Loctite (R&D) Ireland Method of forming a monolayer of particles, and products formed thereby
CN100378551C (zh) * 2001-10-22 2008-04-02 三星电子株式会社 液晶显示器及其制造方法
US6638796B2 (en) * 2002-02-13 2003-10-28 Taiwan Semiconductor Manufacturing Company Method of forming a novel top-metal fuse structure
JP3633566B2 (ja) * 2002-02-28 2005-03-30 セイコーエプソン株式会社 電子デバイス及びその製造方法並びに電子機器
US6987031B2 (en) * 2002-08-27 2006-01-17 Micron Technology, Inc. Multiple chip semiconductor package and method of fabricating same
US20040040855A1 (en) * 2002-08-28 2004-03-04 Victor Batinovich Method for low-cost redistribution and under-bump metallization for flip-chip and wafer-level BGA silicon device packages
US7043830B2 (en) * 2003-02-20 2006-05-16 Micron Technology, Inc. Method of forming conductive bumps
US20050045697A1 (en) * 2003-08-26 2005-03-03 Lacap Efren M. Wafer-level chip scale package
US7148089B2 (en) * 2004-03-01 2006-12-12 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming copper fuse links
TWI268564B (en) * 2005-04-11 2006-12-11 Siliconware Precision Industries Co Ltd Semiconductor device and fabrication method thereof
TWI288447B (en) * 2005-04-12 2007-10-11 Siliconware Precision Industries Co Ltd Conductive bump structure for semiconductor device and fabrication method thereof
TW200638497A (en) * 2005-04-19 2006-11-01 Elan Microelectronics Corp Bumping process and bump structure
US7402908B2 (en) * 2005-05-05 2008-07-22 Micron Technology, Inc. Intermediate semiconductor device structures
US7674701B2 (en) * 2006-02-08 2010-03-09 Amkor Technology, Inc. Methods of forming metal layers using multi-layer lift-off patterns
US7932615B2 (en) * 2006-02-08 2011-04-26 Amkor Technology, Inc. Electronic devices including solder bumps on compliant dielectric layers
JP4337830B2 (ja) * 2006-02-23 2009-09-30 エプソンイメージングデバイス株式会社 電気光学装置及び電子機器
US7993972B2 (en) * 2008-03-04 2011-08-09 Stats Chippac, Ltd. Wafer level die integration and method therefor
JP4254883B2 (ja) * 2006-05-29 2009-04-15 エプソンイメージングデバイス株式会社 配線基板、実装構造体及びその製造方法
US7901956B2 (en) * 2006-08-15 2011-03-08 Stats Chippac, Ltd. Structure for bumped wafer test
US20080054461A1 (en) * 2006-08-30 2008-03-06 Dennis Lang Reliable wafer-level chip-scale package solder bump structure in a packaged semiconductor device
KR20080031091A (ko) * 2006-10-03 2008-04-08 삼성전자주식회사 표시장치 및 이의 제조 방법
US7834449B2 (en) * 2007-04-30 2010-11-16 Broadcom Corporation Highly reliable low cost structure for wafer-level ball grid array packaging
US7615865B2 (en) * 2007-05-21 2009-11-10 Stats Chippac, Ltd. Standoff height improvement for bumping technology using solder resist
US8241954B2 (en) * 2007-12-03 2012-08-14 Stats Chippac, Ltd. Wafer level die integration and method
US10074553B2 (en) * 2007-12-03 2018-09-11 STATS ChipPAC Pte. Ltd. Wafer level package integration and method
US7767496B2 (en) * 2007-12-14 2010-08-03 Stats Chippac, Ltd. Semiconductor device and method of forming interconnect structure for encapsulated die having pre-applied protective layer
JP2009283431A (ja) * 2007-12-27 2009-12-03 Fujifilm Corp 微細構造体およびその製造方法
US20090212428A1 (en) * 2008-02-22 2009-08-27 Advanced Chip Engineering Technology Inc. Re-distribution conductive line structure and the method of forming the same
US8084302B2 (en) * 2008-03-07 2011-12-27 Stats Chippac, Ltd. Semiconductor package having semiconductor die with internal vertical interconnect structure and method therefor
US7648911B2 (en) * 2008-05-27 2010-01-19 Stats Chippac, Ltd. Semiconductor device and method of forming embedded passive circuit elements interconnected to through hole vias
US8039303B2 (en) * 2008-06-11 2011-10-18 Stats Chippac, Ltd. Method of forming stress relief layer between die and interconnect structure
US7838337B2 (en) * 2008-12-01 2010-11-23 Stats Chippac, Ltd. Semiconductor device and method of forming an interposer package with through silicon vias
TWI499024B (zh) * 2009-01-07 2015-09-01 Advanced Semiconductor Eng 堆疊式多封裝構造裝置、半導體封裝構造及其製造方法
JP5296590B2 (ja) * 2009-03-30 2013-09-25 新光電気工業株式会社 半導体パッケージの製造方法
US9875911B2 (en) * 2009-09-23 2018-01-23 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming interposer with opening to contain semiconductor die
US9941195B2 (en) * 2009-11-10 2018-04-10 Taiwan Semiconductor Manufacturing Co., Ltd. Vertical metal insulator metal capacitor
US8937381B1 (en) * 2009-12-03 2015-01-20 Amkor Technology, Inc. Thin stackable package and method
US8822281B2 (en) * 2010-02-23 2014-09-02 Stats Chippac, Ltd. Semiconductor device and method of forming TMV and TSV in WLCSP using same carrier
US8951839B2 (en) * 2010-03-15 2015-02-10 Stats Chippac, Ltd. Semiconductor device and method of forming conductive vias through interconnect structures and encapsulant of WLCSP
JP2011237771A (ja) * 2010-04-12 2011-11-24 Seiko Epson Corp 電気泳動表示装置および電子機器
US8581418B2 (en) * 2010-07-21 2013-11-12 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-die stacking using bumps with different sizes
US8343810B2 (en) * 2010-08-16 2013-01-01 Stats Chippac, Ltd. Semiconductor device and method of forming Fo-WLCSP having conductive layers and conductive vias separated by polymer layers
US8097490B1 (en) * 2010-08-27 2012-01-17 Stats Chippac, Ltd. Semiconductor device and method of forming stepped interconnect layer for stacked semiconductor die
US8492203B2 (en) * 2011-01-21 2013-07-23 Stats Chippac, Ltd. Semiconductor device and method for forming semiconductor package having build-up interconnect structure over semiconductor die with different CTE insulating layers
US8883561B2 (en) * 2011-04-30 2014-11-11 Stats Chippac, Ltd. Semiconductor device and method of embedding TSV semiconductor die within encapsulant with TMV for vertical interconnect in POP
US8786081B2 (en) * 2011-07-27 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Method and device for circuit routing by way of under-bump metallization
US9102851B2 (en) * 2011-09-15 2015-08-11 Trillion Science, Inc. Microcavity carrier belt and method of manufacture
US9679863B2 (en) * 2011-09-23 2017-06-13 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming interconnect substrate for FO-WLCSP
US9123763B2 (en) * 2011-10-12 2015-09-01 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package (PoP) structure having at least one package comprising one die being disposed in a core material between first and second surfaces of the core material
US8975741B2 (en) * 2011-10-17 2015-03-10 Taiwan Semiconductor Manufacturing Company, Ltd. Process for forming package-on-package structures
US9613914B2 (en) * 2011-12-07 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Post-passivation interconnect structure
US8823180B2 (en) * 2011-12-28 2014-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package devices and methods of packaging semiconductor dies
US9082780B2 (en) * 2012-03-23 2015-07-14 Stats Chippac, Ltd. Semiconductor device and method of forming a robust fan-out package including vertical interconnects and mechanical support layer
US9991190B2 (en) * 2012-05-18 2018-06-05 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging with interposer frame
US9355978B2 (en) * 2013-03-11 2016-05-31 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging devices and methods of manufacture thereof
KR101985921B1 (ko) * 2012-06-13 2019-06-05 삼성디스플레이 주식회사 유기 발광 표시 장치
JP6169914B2 (ja) * 2012-08-01 2017-07-26 デクセリアルズ株式会社 異方性導電フィルムの製造方法、異方性導電フィルム、及び接続構造体
US10269676B2 (en) * 2012-10-04 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Thermally enhanced package-on-package (PoP)
US9406552B2 (en) * 2012-12-20 2016-08-02 Advanced Semiconductor Engineering, Inc. Semiconductor device having conductive via and manufacturing process
US9368438B2 (en) * 2012-12-28 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package (PoP) bonding structures
US9953907B2 (en) * 2013-01-29 2018-04-24 Taiwan Semiconductor Manufacturing Company, Ltd. PoP device
US9263511B2 (en) * 2013-02-11 2016-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Package with metal-insulator-metal capacitor and method of manufacturing the same
US9087832B2 (en) * 2013-03-08 2015-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Warpage reduction and adhesion improvement of semiconductor die package
KR101568659B1 (ko) * 2013-03-29 2015-11-12 제일모직주식회사 도전성 접착층을 포함하는 이방 도전성 필름 및 상기 필름에 의해 접속된 반도체 장치
US9974175B2 (en) * 2013-04-29 2018-05-15 Samsung Display Co., Ltd. Electronic component, electric device including the same, and bonding method thereof
KR102047068B1 (ko) * 2013-04-29 2019-11-21 삼성디스플레이 주식회사 표시패널, 전자기기 및 전자기기의 본딩 방법
US11457531B2 (en) * 2013-04-29 2022-09-27 Samsung Display Co., Ltd. Electronic component, electric device including the same, and bonding method thereof
JP6151597B2 (ja) * 2013-07-29 2017-06-21 デクセリアルズ株式会社 導電性接着フィルムの製造方法、導電性接着フィルム、接続体の製造方法
US9252076B2 (en) * 2013-08-07 2016-02-02 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
KR20150037198A (ko) * 2013-09-30 2015-04-08 삼성디스플레이 주식회사 표시패널 및 이를 갖는 표시장치
JP6119718B2 (ja) * 2013-11-19 2017-04-26 デクセリアルズ株式会社 異方導電性フィルム及び接続構造体
US9006030B1 (en) * 2013-12-09 2015-04-14 Xilinx, Inc. Warpage management for fan-out mold packaged integrated circuit
CN105765711A (zh) * 2013-12-23 2016-07-13 英特尔公司 封装体叠层架构以及制造方法
KR102194822B1 (ko) * 2014-01-16 2020-12-24 삼성디스플레이 주식회사 디스플레이 장치
US10804153B2 (en) * 2014-06-16 2020-10-13 STATS ChipPAC Pte. Ltd. Semiconductor device and method to minimize stress on stack via
US9263373B2 (en) * 2014-06-18 2016-02-16 Dyi-chung Hu Thin film RDL for nanochip package
JP6331776B2 (ja) * 2014-06-30 2018-05-30 デクセリアルズ株式会社 異方導電性フィルム及び接続構造体
US9373604B2 (en) * 2014-08-20 2016-06-21 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures for wafer level package and methods of forming same
US9842825B2 (en) * 2014-09-05 2017-12-12 Taiwan Semiconductor Manufacturing Company, Ltd. Substrateless integrated circuit packages and methods of forming same
US9520371B2 (en) * 2014-10-27 2016-12-13 Globalfoundries Singapore Pte. Ltd. Planar passivation for pads
JP6661969B2 (ja) * 2014-10-28 2020-03-11 デクセリアルズ株式会社 異方性導電フィルム及び接続構造体
WO2016068127A1 (ja) * 2014-10-28 2016-05-06 デクセリアルズ株式会社 異方導電性フィルム及び接続構造体
US20160133614A1 (en) * 2014-11-07 2016-05-12 Qualcomm Incorporated Semiconductor package with incorporated inductance element
KR102335815B1 (ko) * 2014-12-08 2021-12-07 삼성디스플레이 주식회사 표시 장치
BR112015029099A2 (pt) * 2014-12-19 2017-07-25 Intel Ip Corp embalagem de dispositivo semicondutor em pilha, método de produção da mesma e dispositivo de computação
KR102355256B1 (ko) * 2015-01-22 2022-01-25 삼성디스플레이 주식회사 표시 장치
US9633974B2 (en) * 2015-03-04 2017-04-25 Apple Inc. System in package fan out stacking architecture and process flow
US9786623B2 (en) * 2015-03-17 2017-10-10 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming PoP semiconductor device with RDL over top package
KR102367317B1 (ko) * 2015-03-23 2022-02-25 삼성디스플레이 주식회사 인쇄회로기판 어셈블리
US9659907B2 (en) * 2015-04-07 2017-05-23 Apple Inc. Double side mounting memory integration in thin low warpage fanout package
US9806063B2 (en) * 2015-04-29 2017-10-31 Qualcomm Incorporated Reinforced wafer level package comprising a core layer for reducing stress in a solder joint and improving solder joint reliability
TWI691977B (zh) * 2015-05-27 2020-04-21 日商迪睿合股份有限公司 異向導電性膜及連接構造體
KR102449287B1 (ko) * 2015-05-27 2022-09-29 데쿠세리아루즈 가부시키가이샤 이방 도전성 필름 및 접속 구조체
US9679801B2 (en) * 2015-06-03 2017-06-13 Apple Inc. Dual molded stack TSV package
US9728498B2 (en) * 2015-06-30 2017-08-08 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure
US9786632B2 (en) * 2015-07-30 2017-10-10 Mediatek Inc. Semiconductor package structure and method for forming the same
US9786599B2 (en) * 2015-08-21 2017-10-10 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and method of forming the same
US9559081B1 (en) * 2015-08-21 2017-01-31 Apple Inc. Independent 3D stacking
US9640496B2 (en) * 2015-09-17 2017-05-02 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device
US9449953B1 (en) * 2015-10-08 2016-09-20 Inotera Memories, Inc. Package-on-package assembly and method for manufacturing the same
US10049986B2 (en) * 2015-10-30 2018-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods of making the same
KR102019350B1 (ko) * 2015-11-06 2019-09-09 삼성전자주식회사 전자부품 패키지 및 그 제조방법
WO2017098559A1 (ja) * 2015-12-07 2017-06-15 堺ディスプレイプロダクト株式会社 端子接続構造及び表示装置
CN105529339B (zh) * 2016-02-17 2018-12-28 京东方科技集团股份有限公司 阵列基板、覆晶薄膜及显示装置
KR102535557B1 (ko) * 2016-03-07 2023-05-24 삼성디스플레이 주식회사 표시 장치 및 전자 디바이스
KR102513996B1 (ko) * 2016-03-15 2023-03-24 삼성디스플레이 주식회사 표시 장치
JP7274811B2 (ja) * 2016-05-05 2023-05-17 デクセリアルズ株式会社 異方性導電フィルム
KR20170130003A (ko) * 2016-05-17 2017-11-28 삼성디스플레이 주식회사 이방성 도전 필름을 포함하는 표시 장치 및 이방성 도전 필름의 제조 방법
KR102595086B1 (ko) * 2016-07-08 2023-10-27 삼성디스플레이 주식회사 표시 장치 및 이의 제조 방법
WO2018077257A1 (zh) * 2016-10-31 2018-05-03 昆山工研院新型平板显示技术中心有限公司 驱动电路载体、显示面板、平板显示器及制造方法
KR102251441B1 (ko) * 2016-12-01 2021-05-12 데쿠세리아루즈 가부시키가이샤 접속 구조체
KR20180070774A (ko) * 2016-12-16 2018-06-27 삼성디스플레이 주식회사 기판, 전자 장치 및 이를 구비하는 표시 장치
US10468345B2 (en) * 2017-05-19 2019-11-05 Taiwan Semiconductor Manufacturing Company Ltd. 3D IC decoupling capacitor structure and method for manufacturing the same
KR102451017B1 (ko) * 2017-08-16 2022-10-04 엘지디스플레이 주식회사 플렉서블 표시 장치
JP6369616B1 (ja) * 2017-11-07 2018-08-08 Smk株式会社 タッチパネル及びウェアラブル機器
JP7046351B2 (ja) * 2018-01-31 2022-04-04 三国電子有限会社 接続構造体の作製方法
KR102519126B1 (ko) * 2018-03-30 2023-04-06 삼성디스플레이 주식회사 표시 장치
KR102640726B1 (ko) * 2018-04-18 2024-02-27 삼성디스플레이 주식회사 유기 발광 표시 장치
US20200098692A1 (en) * 2018-09-26 2020-03-26 Intel Corporation Microelectronic assemblies having non-rectilinear arrangements

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7977783B1 (en) * 2009-08-27 2011-07-12 Amkor Technology, Inc. Wafer level chip size package having redistribution layers
CN104795371A (zh) * 2014-01-17 2015-07-22 台湾积体电路制造股份有限公司 扇出型封装件及其形成方法
CN105321912A (zh) * 2014-05-30 2016-02-10 台湾积体电路制造股份有限公司 用于激光标刻的金属焊盘

Also Published As

Publication number Publication date
US20190393195A1 (en) 2019-12-26
US20170338204A1 (en) 2017-11-23
US20210143131A1 (en) 2021-05-13
CN107452634A (zh) 2017-12-08

Similar Documents

Publication Publication Date Title
CN107452634B (zh) 封装件结构及其形成方法
US10867976B2 (en) Semiconductor packages having dummy connectors and methods of forming same
US11018088B2 (en) Dummy features in redistribution layers (RDLS) and methods of forming same
US11189603B2 (en) Semiconductor packages and methods of forming same
CN109786266B (zh) 半导体封装件及其形成方法
CN107808870B (zh) 半导体封装件中的再分布层及其形成方法
CN108987380B (zh) 半导体封装件中的导电通孔及其形成方法
US20180366412A1 (en) Semiconductor Package and Method of Forming the Same
CN108122880B (zh) 半导体装置的制造方法
KR20190055692A (ko) 반도체 패키지들 내의 금속화 패턴들 및 그 형성 방법들
US12002767B2 (en) Integrated circuit package and method
US20230075602A1 (en) Semiconductor Packages
US20220359465A1 (en) Package structures and method for forming the same
CN115497916A (zh) 半导体结构及形成半导体器件的方法
US11830859B2 (en) Package structures and method for forming the same
US20230335536A1 (en) Semiconductor Packages and Methods of Forming the Same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant