JP2016192447A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2016192447A JP2016192447A JP2015070401A JP2015070401A JP2016192447A JP 2016192447 A JP2016192447 A JP 2016192447A JP 2015070401 A JP2015070401 A JP 2015070401A JP 2015070401 A JP2015070401 A JP 2015070401A JP 2016192447 A JP2016192447 A JP 2016192447A
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- Prior art keywords
- conductive layer
- electrode
- semiconductor chip
- semiconductor device
- opening
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 201
- 229910052751 metal Inorganic materials 0.000 claims abstract description 22
- 239000002184 metal Substances 0.000 claims abstract description 22
- 229910000679 solder Inorganic materials 0.000 claims description 35
- 229920005989 resin Polymers 0.000 claims description 27
- 239000011347 resin Substances 0.000 claims description 27
- 239000010410 layer Substances 0.000 description 160
- 238000000034 method Methods 0.000 description 24
- 239000012790 adhesive layer Substances 0.000 description 19
- 238000004519 manufacturing process Methods 0.000 description 16
- 239000000758 substrate Substances 0.000 description 16
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 12
- 238000005530 etching Methods 0.000 description 10
- 238000012986 modification Methods 0.000 description 10
- 230000004048 modification Effects 0.000 description 10
- 239000010949 copper Substances 0.000 description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 229910052802 copper Inorganic materials 0.000 description 7
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 6
- 229910052759 nickel Inorganic materials 0.000 description 6
- 229910052719 titanium Inorganic materials 0.000 description 6
- 239000010936 titanium Substances 0.000 description 6
- 239000004020 conductor Substances 0.000 description 5
- 238000001459 lithography Methods 0.000 description 5
- 239000004642 Polyimide Substances 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- -1 for example Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 229920005992 thermoplastic resin Polymers 0.000 description 1
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- H—ELECTRICITY
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Abstract
Description
図1を用いて、第一実施形態の半導体装置5を説明する。
図2〜図15を用いて、第一実施形態の半導体装置5の製造方法を説明する。なお、図2〜図4は、図1と反転して図示する。
本実施形態によれば、第二半導体チップ70、第三半導体チップ100は、第一半導体チップ20に設けられた第一導電コンタクト50及び第一電極40を介して半田バンプ200に電気的に接続する。つまり、本実施形態によれば、第二半導体チップ70及び第三半導体チップ100は、第一導電コンタクト50と電気的に接続し、第一導電コンタクト50を介して半田バンプ200と電気的に接続する。具体的には、図1で示すように、第二半導体チップ70、第三半導体チップ100は、半田バンプ200cと電気的に接続する。なお、この第一導電コンタクト50は、第一半導体チップ20と電気的に接続しても良く、第二半導体チップ70及び第三半導体チップ100は、第一半導体チップ20と電気的に接続しても構わない。
図5に示した支持基板10の剥離は、次のように行っても良い。
図1において、第一半導体チップ20、第二半導体チップ70、第三半導体チップ100が存在する場合を説明したが、半導体チップの枚数は3枚に限られず、任意の枚数で構わない。
図16に示すように、第一半導体チップ20は、第一電極40及び第一電極パッド60を含まなくてもよい。この場合は、第一導電コンタクト50は、第一面20a及び第二面20bにおいて電極となり、金属ワイヤ130及び第一導電層160と電気的に接続する。
図1において、第一半導体チップ20が、第一導電層160、第二導電層180、第三導電層190を介して、半田バンプ200に接続される例を示したが、これに限られない。例えば、半導体装置5は第三導電層190を備えずに、第二導電層180上に半田バンプ200を備えてもよい。また、半導体装置5は第二導電層180、第三導電層190を備えずに、第一導電層160上に半田バンプ200を備えてもよい。また、逆に、半導体装置5は、第三導電層190上に新たな導電層を備え、半田バンプ200をその新たな導電層上に備えてもよい。
図1において、第一半導体チップ20が、第一電極40a,40b,40c、第一導電コンタクト50b、50cを含む場合を示したがこれに限られない。第一半導体チップ20は、この一部のみを含んでも良いし、さらに多くの第一電極40、第一導電コンタクト50を含んでも良い。
図17に示すように、第二半導体チップ70、第三半導体チップ100は、第二電極パッド90、第三電極パッド120を含まなくてもよい。この場合、第二半導体チップ70、第三半導体チップ100は、第一半導体チップ20と同様に第二導電コンタクト52、第三導電コンタクト54を含む。そして、第二半導体チップ70、第三半導体チップ100は、第二導電コンタクト52、第三導電コンタクト54を介して第一半導体チップ20に接続される。第一半導体チップ20、第二半導体チップ70、第三半導体チップ100を階段状にずらして積層する必要がないため、半導体装置5のさらなる小型化が可能である。
10…支持基板
20…第一半導体チップ
30…第一接着材層
40…第一電極
50…第一導電コンタクト
52…第二導電コンタクト
54…第三導電コンタクト
60…第一電極パッド
70…第二半導体チップ
80…第二接着材層
90…第二電極パッド
100…第三半導体チップ
110…第三接着材層
120…第三電極パッド
130…金属ワイヤ
140…樹脂層
150…第一絶縁層
155…第一開口部
160…第一導電層
170…第一マスクパターン
175…第二絶縁層
177…第二開口部
180…第二導電層
190…第三導電層
200…半田バンプ
Claims (17)
- 第一面と、前記第一面とは反対側の第二面と、前記第一面に設けられた第一電極と、前記第二面に設けられた第二電極と、前記第一電極と前記第二電極とを電気的に接続する第一コンタクトと、を有する第一半導体チップと、
前記第一面に対向して配置された第三面と、前記第三面の反対側の面である第四面と、前記第四面に設けられた第三電極と、を有した、第二半導体チップと、
前記第三電極と前記第一電極とを電気的に接続する金属ワイヤと、
前記第一半導体チップの前記第二面に配置され、第一開口部を有する第一絶縁層と、
前記第一開口部及び前記第一絶縁層の上の一部に配置され、前記第一開口部において前記第二電極と電気的に接続された第一導電層と、
前記第一導電層に電気的に接続された第一外部端子と、
を有する半導体装置。 - 前記第一導電層の直上に配置された第二導電層と、
前記第一絶縁層と前記第二導電層の上に配置され、第二開口部を有する第二絶縁層と、
前記第二開口部内に配置され、前記第二開口部において前記第二導電層と電気的に接続された第三導電層と、をさらに有し、
前記第一外部端子は、前記第三導電層の直上に配置された請求項1記載の半導体装置。 - 前記第一面は、第一回路素子を備え、
前記第四面は、第二回路素子を備え、
前記第二回路素子は、前記第三電極と電気的に接続する
請求項1記載の半導体装置。 - 前記第二面は、第四電極を備え、
前記第一半導体チップは、前記第一回路素子と前記第四電極とを電気的に接続する第二コンタクトを備え、
前記第一絶縁層は、第三開口部を備え、
前記第三開口部及び前記第四電極の上の一部に配置され、前記第三開口部において、前記第四電極と電気的に接続された第四導電層と、
前記第四導電層に電気的に接続された第二外部端子と、
をさらに備えた請求項3記載の半導体装置。 - 前記第一導電層の直上に配置された第二導電層と、
前記第四導電層の直上に配置された第五導電層と、
前記第一絶縁層と前記第二導電層と前記第五導電層の上に配置され、第二開口部と第四開口部を有する第二絶縁層と、
前記第二開口部内に配置され、前記第二開口部において前記第二導電層と電気的に接続された第三導電層と、
前記第四開口部内に配置され、前記第四開口部において前記第五導電層と電気的に接続された第六導電層と、をさらに備え、
前記第一外部端子は、前記第三導電層の直上に配置され、
前記第二外部端子は、前記第六導電層の直上に配置された、
請求項4記載の半導体装置。 - 前記第一半導体チップと前記第二半導体チップは、実質的に同一の構造を持つ
請求項1〜5何れか一項記載の半導体装置。 - 前記第一外部端子は、半田バンプである請求項1記載の半導体装置。
- 前記第一外部端子と前記第二外部端子との距離は、前記第二電極と前記第四電極との距離よりも長い請求項4記載の半導体装置。
- 前記第一半導体チップ及び前記第二半導体チップを覆う樹脂層と、をさらに備え、
前記樹脂層は、前記第一絶縁層の下面と側面とに接触している請求項1〜8何れか一項記載の半導体装置。 - 第一面と、前記第一面とは反対側の第二面と、前記第一面に設けられた第一電極と、前記第二面に設けられた第二電極と、前記第一電極と前記第二電極とを電気的に接続する第一コンタクトと、を有する第一半導体チップと、
前記第一面に対向して配置された第三面と、前記第三面の反対側の面である第四面と、前記第四面に設けられた第三電極と、を有した、第二半導体チップと、
前記第三電極と前記第一電極とを電気的に接続する金属ワイヤと、
前記第二面と交差する第一方向に延伸し、前記第二電極と接続する第一部分と、前記第一方向に交差する第二方向に延伸して配置される第二部分と、を有する第一導電層と、
前記第一導電層に電気的に接続された第一外部端子と、
を有する半導体装置。 - 前記第一導電層の直上に配置された第二導電層と、
前記第二導電層の少なくとも一部の領域の直上に配置された第三導電層と、をさらに有し、
前記第一外部端子は、前記第三導電層の直上に配置された請求項10記載の半導体装置。 - 前記第一面は、第一回路素子を備え、
前記第四面は、第二回路素子を備え、
前記第二回路素子は、前記第三電極と電気的に接続する
請求項10記載の半導体装置。 - 前記第二面は、第四電極を備え、
前記第一半導体チップは、前記第一回路素子と前記第四電極とを電気的に接続する第二コンタクトを備え、
前記第一方向に延伸し、前記第四電極と接続する第三部分と、前記第一方向に交差する第三方向に延伸して設けられる第四部分と、を有する第四導電層と、
前記第四導電層に電気的に接続された第二外部端子と、
をさらに備えた請求項12記載の半導体装置。 - 前記第一導電層の直上に配置された第二導電層と、
前記第四導電層の直上に配置された第五導電層と、
前記第二導電層の少なくとも一部の領域の直上に配置された第三導電層と、
前記第五導電層の少なくとも一部の領域の直上に配置された第六導電層と、
をさらに有し、
前記第一外部端子は、前記第三導電層の直上に配置され、
前記第二外部端子は、前記第六導電層の直上に配置された、
請求項13記載の半導体装置。 - 前記第一半導体チップと前記第二半導体チップは、実質的に同一の構造を持つ
請求項10〜14何れか一項記載の半導体装置。 - 前記第一外部端子は、半田バンプである請求項10記載の半導体装置。
- 前記第一外部端子と前記第二外部端子との距離は、前記第二電極と前記第四電極との距離よりも長い請求項13記載の半導体装置。
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CN106024755B (zh) | 2019-05-10 |
US20160293582A1 (en) | 2016-10-06 |
CN106024755A (zh) | 2016-10-12 |
US10115704B2 (en) | 2018-10-30 |
TW201705439A (zh) | 2017-02-01 |
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