CN101615587A - 半导体装置中的导线层叠式缝线接合 - Google Patents

半导体装置中的导线层叠式缝线接合 Download PDF

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Publication number
CN101615587A
CN101615587A CN200810127580A CN200810127580A CN101615587A CN 101615587 A CN101615587 A CN 101615587A CN 200810127580 A CN200810127580 A CN 200810127580A CN 200810127580 A CN200810127580 A CN 200810127580A CN 101615587 A CN101615587 A CN 101615587A
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China
Prior art keywords
suture
semiconductor die
lead
ball
semiconductor
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CN200810127580A
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English (en)
Inventor
梁行志
方海波
王丽
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SanDisk Corp
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SanDisk Corp
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Publication date
Application filed by SanDisk Corp filed Critical SanDisk Corp
Priority to CN200810127580A priority Critical patent/CN101615587A/zh
Priority to US12/165,375 priority patent/US20090321501A1/en
Priority to US12/165,391 priority patent/US20090321952A1/en
Priority to KR1020117002196A priority patent/KR20110039299A/ko
Priority to PCT/US2009/048712 priority patent/WO2009158533A2/en
Priority to EP09771065A priority patent/EP2291857A2/en
Publication of CN101615587A publication Critical patent/CN101615587A/zh
Pending legal-status Critical Current

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Abstract

本发明揭示一种低剖面半导体封装，其包括安装到衬底的至少第一和第二堆叠半导体电路小片。所述第一半导体电路小片可在前向球形接合工艺中使用多个缝线而电耦合到所述衬底。所述第二半导体电路小片又可使用接合在所述第一与第二半导体电路小片的电路小片接合垫之间的第二组缝线而电耦合到所述第一半导体电路小片。所述第二组缝线每一者可包括具有接合到所述第二半导体电路小片的所述接合垫的缝线球的前端。所述第二组缝线中的每一缝线的尾端可直接楔形接合到所述第一组缝线中的缝线的前端。

Description

半导体装置中的导线层叠式缝线接合
技术领域
本发明的实施例涉及一种低剖面半导体装置及其制造方法。
背景技术
对便携式消费者电子产品的需求的强劲增长推进了对高容量存储装置的需要。例如快闪存储器存储卡的非易失性半导体存储器装置变得广泛使用，以满足对数字信息存储和交换的不断增长的需求。其便携性、通用性和坚固设计以及其高可靠性和大容量以使此类存储器装置理想地用于多种电子装置中的，所述电子装置包括例如数码相机、数字音乐播放器、视频游戏控制台、PDA和蜂窝式电话。
虽然已知多种封装配置，但通常可将快闪存储器存储卡制造为系统级封装(system-in-a-package，SiP)或多芯片模块(MCM)，其中将功能系统组装到单个封装中。在现有技术图1和图2中展示了常规半导体封装20(没有模塑料)的侧视图。典型封装包括安装到衬底26的多个半导体电路小片22、24。尽管在图1和图2中未展示，但半导体电路小片使用电路小片上表面上的电路小片接合垫而形成。衬底26可由夹在上部导电层与下部导电层之间的电绝缘核心形成。上部和/或下部导电层可经蚀刻以形成包括电引线和接触垫的导电图案。在本文中称作缝线的接合线接合在半导体电路小片22、24的电路小片接合垫与衬底26的接触垫之间，以将半导体电路小片电耦合到衬底。衬底上的电引线又在电路小片与主机装置之间提供电路径。一旦在电路小片与衬底之间产生电连接，组合件接着就通常装入在模塑料中以提供保护性封装。
已知层半导体电路小片带偏移地彼此层叠(现有技术图1)或处于堆叠配置中(现有技术图2)。在图1的偏移配置中，电路小片带偏移地堆叠，使得下一下部电路小片的接合垫左边暴露。此类配置展示在例如Lin等人的题为“具有堆叠芯片配置的多芯片模块(Multichip Module Having A Stacked Chip Arrangement)”的第6,359,340号美国专利中。偏移配置提供了方便接近每一半导体电路小片上的接合垫的优势。然而，偏移在衬底上需要较大的占用面积，但在衬底上的空间是非常珍贵的。
在图2的堆叠配置中，两个或两个以上半导体电路小片直接彼此上下堆叠，因此与偏移配置相比较在衬底上占据较少的占用面积。然而，在堆叠配置中，必须在相邻半导体电路小片之间提供空间用于导线缝线30。除了缝线30本身的高度以外，必须在缝线上方留出额外空间，因为一个电路小片的缝线30与上方下一电路小片的接触可导致电短路。如图2中所示，因此已知提供介电间隔层34以提供足够的空间用于缝线30接合到下部电路小片24上的电路小片接合垫。替代于间隔层34，还已知将两个相邻半导体电路小片之间的导线缝线埋于各自电路小片之间的粘接层内。此类配置展示于例如Lee等人的题为“多芯片模块(Multi-Chip Module)”的第6,388,313号美国专利以及Jiang等人的题为“堆叠微电子装置及其制造方法(Stacked Microelectronic Devices and Methodsof Fabricating Same)”的第7,037,756号美国专利中。
经常存在增加存储器模块内的存储容量的需要。一种增加存储容量的方法是增加在封装内使用的存储器电路小片的数目。在便携式存储器封装中，可使用的电路小片数目由封装的厚度限制。因此在以下方面存在浓厚的兴趣：在增加存储器密度的同时减少封装的内含物的厚度。
现有技术图1和图2中所示的封装20需要在封装内提供额外空间以容纳导线缝线30的高度。参看现有技术图3到图5的透视图来解释关于形成缝线30的常规工艺的其它细节。在图3到图5中，电路小片22和24已安装到衬底26。图3展示由前向球形接合工艺(forward ball bonding process)形成缝线30。此工艺使用称作导线接合毛细管的导线接合装置。一定长度的导线(通常是金或铜)馈穿导线接合毛细管的中央腔。导线穿过毛细管的尖端伸出，其中从与毛细管尖端相关联的换能器将高压电荷施加到导线。电荷使尖端的导线熔化，且导线由于熔融金属的表面张力而形成为球形(图3中的38)。
随着球凝固，毛细管降低到半导体电路小片24上所形成的电路小片接合垫40的表面。可加热电路小片24的表面以有助于较好的接合。缝线球38在负荷作用下沉积在电路小片接合垫40上，而换能器施加超声能。结合的热、压力和超声能在缝线球38与电路小片接合垫40之间产生导线接合。
接着在将导线放松穿出毛细管时将导线接合毛细管上拉且离开半导体电路小片24的表面。毛细管接着移动到衬底26上的接纳缝线的第二末端的接触垫44。接着再次使用热、压力和超声能在接触垫44上形成称作楔形或尾部接合的第二导线接合，但并非形成球形，导线在压力下被压扁以产生第二导线接合。导线接合装置接着放松较短长度的导线，并将导线从第二导线接合的表面撕下。接着使用从毛细管的末端悬挂的导线的小尾部以形成用于下一随后缝线的缝线球38。可将上述周期每秒重复约20到30次，直至在半导体电路小片与衬底之间形成所有缝线30为止。应了解，可存在比图3和图4中所示的缝线多得多的缝线30。
由于导线缝线30必须从每一缝线30上的球38向上拉的事实，图3中所示的由前向球形接合工艺形成的缝线具有相对大的高度。如上文所指示，此高度增加了封装的整体厚度，但在封装中的空间是非常珍贵的。现有技术图4是由反向球形接合工艺形成的电路小片22、24、衬底26和缝线30的透视图。在反向球形接合工艺中，缝线球50最初形成在半导体电路小片24的电路小片接合垫40上。即，毛细管形成球形且将其接合到接合垫40，但在未放松导线的情况下拉开。重复此工艺以将球50沉积到电路小片24上的每一接合垫40上。其后，为了形成第一导线缝线，将第二球52导线接合在衬底26的接触垫44上，且毛细管在放松导线的同时上拉且离开球52。毛细管接着使用楔形接合将缝线30导线接合到电路小片接合垫40上的相应球50。由于毛细管使用扁平的楔形接合来将缝线30附着到球50，所以缝线具有比图3的前向球形接合工艺中的剖面低的剖面，图3的前向球形接合工艺中导线被提起且离开电路小片接合垫上的球38。重复此工艺以形成电路小片24与衬底26之间的各自缝线。
参看现有技术图5，接着已知重复所述工艺以导线接合电路小片22。即，首先将缝线球60贴附到电路小片22的接合垫40。接着在电路小片24上的楔形接合的顶部形成缝线球62。导线经放松且接合到球60以在电路小片22上形成缝线66。可再次重复此工艺用于电路小片堆叠上的任何额外电路小片。如图所示，不同电路小片22和24上的相应(对准的)电路小片接合垫40电短接到一起。通过启用堆叠中的仅一个电路小片(经由未图示的芯片启用信号连接)将信号发送到特定电路小片且从特定电路小片发送信号，使得可沿着特定缝线连接路径来发送信号，但仅有启用的电路小片将进行响应。
如上文关于图4和图5所描述的常规反向导线接合工艺产生比图3的前向导线接合工艺低的剖面。然而，电路小片堆叠中的电路小片(除了最上层电路小片之外)上的所有缝线将具有球-导线-球配置。即，如图5中针对电路小片24所示，接合垫40上的缝线包括接合在缝线30的末端上的球62，所述缝线30的末端又形成在球50上。
在电路小片堆叠中的所有中间电路小片的电路小片接合垫上具有球-导线-球配置具有缺点。首先，在反向导线接合工艺中必须增加额外缝线球增加了制造工艺的处理步骤和时间，尤其考虑到在任何给定半导体封装中所需要的大量接合。另外，球-导线-球配置具有相对笨重的结构，其具有高缝线故障率。在四存储器电路小片微SD封装的一个实例中，已发现良率损失为约2000PPM(百万分率)。
发明内容
本发明的实施例涉及一种低剖面半导体封装，其包括安装到衬底的至少第一和第二堆叠半导体电路小片。所述第一半导体电路小片可在前向球形接合工艺中使用多个缝线而电耦合到所述衬底。所述第二半导体电路小片又可使用接合在所述第一与第二半导体电路小片的所述电路小片接合垫之间的第二组缝线而电耦合到所述第一半导体电路小片。所述第二组缝线每一者可包括前端，其具有接合到所述第二半导体电路小片的所述接合垫的缝线球。所述第二组缝线中的每一缝线的尾端可直接楔形接合到所述第一组缝线中的缝线的前端。
将缝线的尾端直接贴附到下方电路小片上的导线接合提供了优于包括球-导线-球配置的常规系统的改进。举例来说，本系统需要较少的步骤和较少的制造时间。具体来说，常规反向接合技术需要缝线球形成在缝线的前端和尾端两者处。相反，本发明仅需要在缝线的前端处的缝线球。缝线的尾端可直接楔形接合到下方电路小片的前端导线接合。这导致与常规反向接合技术相比将缝线形成周期时间减少30％到50％。此外，替代于常规球-导线-球配置，本发明的导线层叠式配置体积不大，从而提供减少电噪音且较大稳定性的益处，较大稳定性导致较低的缝线破裂率。
附图说明
图1是包括以偏移关系堆叠的一对半导体电路小片的常规半导体装置的现有技术侧视图。
图2是包括以重叠关系堆叠且由间隔层分隔的一对半导体电路小片的常规半导体装置的现有技术侧视图。
图3是包括在前向球形接合工艺中安装且缝合到衬底的半导体电路小片的常规半导体装置的现有技术局部透视图。
图4是包括使用反向球形接合工艺安装且缝合到衬底的半导体电路小片的常规半导体装置的现有技术局部透视图。
图5是包括安装且缝合到图4中所示的半导体电路小片的半导体电路小片的常规半导体装置的现有技术局部透视图。
图6是展示根据本发明的半导体装置的制造的流程图。
图7是包括缝合到衬底的电路小片的制造期间的半导体装置的侧视图。
图8是包括缝合到衬底的电路小片的制造期间的半导体装置的透视图。
图9是包括缝合到衬底的第一电路小片和缝合到第一电路小片的第二电路小片的制造期间的半导体装置的侧视图。
图10是包括缝合到衬底的第一电路小片和缝合到第一电路小片的第二电路小片的制造期间的半导体装置的透视图。
图10A是缝合到第一电路小片的第二电路小片的导线接合的放大视图。
图11是包括缝合到衬底的第一电路小片、缝合到第一电路小片的第二电路小片和缝合到第二电路小片的第三电路小片的制造期间的半导体装置的透视图。
图12是根据本发明实施例完成的半导体装置的横截面侧视图。
具体实施方式
现将参看图6到图12来描述实施例，其涉及低剖面半导体封装。应了解，本发明可以许多不同形式实施，且不应解释为限于本文所陈述的实施例。事实上，提供这些实施例使得本揭示案将是彻底且完整的，且将把本发明充分传达给所属领域的技术人员。实际上，本发明希望涵盖包括在如由所附权利要求书界定的本发明的范围和精神内的这些实施例的替代、修改和等效物。此外，在本发明的以下详细描述中，陈述众多具体细节以便提供对本发明的透彻理解。然而，所属领域的一般技术人员将显而易见，可在没有此类具体细节的情况下实践本发明。
在本文中使用术语“顶部”与“底部”以及“上部”和“下部”仅用于方便和说明性目的，且并不意图限制本发明的描述，因为所参考项目可在位置上交换。
现将参看图6的流程图以及图7到图12的视图来解释形成根据本发明的半导体封装的工艺。首先参看图7的侧视图和图8的透视图，在步骤200中第一半导体电路小片102可安装在衬底106上。电路小片102可在已知的粘接或共晶电路小片接合工艺中经由电路小片附着粘接剂而安装到衬底106。尽管未图示，但衬底106可以是衬底的面板的一部分，使得根据本发明的半导体封装可被批量处理以实现大规模经济的效益。尽管在下文描述单个半导体封装的制造，但应了解以下描述可适用于衬底面板上所形成的所有封装。
尽管对于本发明并不关键，但衬底106可以是多种不同芯片载体媒介，包括PCB、引线框或带式自动接合(TAB)带。当衬底106是PCB时，衬底可由其上形成有顶部和/或底部导电层的核心形成。核心可以是各种介电材料，例如聚酰亚胺层板、包括FR4和FR5的环氧树脂、双马来酰亚胺三嗪(bismaleimide triazine，BT)等等。
导电层可由铜或铜合金、镀铜或镀铜合金、合金42(42FE/58NI)、镀铜钢或已知用于衬底上的其它金属或材料形成。导电层可被蚀刻为已知用于在半导体电路小片102与外部装置(未图示)之间传送信号的导电图案。衬底106可额外包括暴露金属部分，其在衬底106的上部表面上形成接触垫108(例如展示在图8中)。当半导体封装是焊盘栅格阵列(land grid array，LGA)封装时，也可在衬底106的下部表面上界定接触指(未图示)。接触垫108和/或接触指可例如在所属领域中已知的电镀工艺中镀有一个或一个以上金层。
在步骤200中将第一半导体电路小片102贴附到衬底106之后，一个或一个以上额外电路小片可以偏移配置安装在电路小片102上。举例来说，图7到图10展示安装在电路小片102上的一个额外电路小片104。图11和图12展示安装在电路小片102上的两个额外电路小片104和110。应了解，在其它实施例中电路小片堆叠可包括两个以上额外电路小片。
如图7和图8中所示，在步骤202中，第一组导线缝线120可在常规前向球形接合工艺中附着在电路小片102上的电路小片接合垫124与衬底106上的接触垫108之间。首先，导线接合122可形成在电路小片102上的缝线120与电路小片接合垫124之间。这可使用已知构造的导线接合毛细管装置(未图示)来完成，所述导线接合毛细管装置形成缝线球126且将其沉积在电路小片102的接合垫124上。在换能器施加超声能的同时，可在负荷下将球126施加到接合垫124。结合的热、压力和超声能在缝线球126与电路小片接合垫124之间产生导线接合122。在实施例中，可通过加热接纳缝线的前端或尾端的接合垫的表面而进一步促进上述缝线接合工艺以及在下文中描述的工艺。
接着在导线120与衬底106之间形成例如楔形接合的第二导线接合128。具体来说，在形成第一导线接合122之后，毛细管在放松导线的同时上拉且离开球126，且将导线接合到衬底106上的相应接触垫108以完成缝线120。缝线120可在负荷作用下施加到接触垫108，而换能器施加超声能。结合的热、压力和超声能在缝线120与接触垫108之间产生接合。导线接合毛细管接着放松较短长度的导线，并将导线从接触垫108的表面撕下。接着使用从毛细管的末端悬挂的导线的小尾部以形成用于下一随后缝线的缝线球126。可重复上述周期直至在电路小片102与衬底106之间形成所有缝线120为止。应了解，可存在比图8中所示的缝线多得多的缝线120。
现参看图9到图10A，根据本发明，第二组缝线130可接着经形成，使得第一导线接合132在电路小片104上且第二导线接合在电路小片102的导线接合124上的导线接合122顶部。在步骤204中，导线接合毛细管装置可形成缝线球136且将其沉积在电路小片104的接合垫134上。球136可在负荷作用下施加到接合垫134，而换能器施加超声能。
接着，毛细管在放松导线的同时上拉且离开球316，且通过将缝线130的尾端直接附着到导线接合122的顶部而完成缝线130。在换能器施加超声能的同时，可在负荷下将缝线130的导线接合在导线接合122的顶部。图10A是展示连接到导线接合122的缝线130的尾端130a的放大视图。图10A展示包括贴附到电路小片接合垫124的缝线球126的导线接合122以及从导线接合122延伸的缝线120。使用导线接合毛细管装置所施加的结合的热、压力和超声能将缝线130的末端130a推进且附着到导线接合122中。
在一个实施例中，毛细管可在14微秒的周期内施加60mAps的电流和35克的力，以便将缝线130的末端130a与导线接合122接合。此压力和超声能足以将缝线130的末端130a贴附到且电耦合到电路小片接合垫124上的导线接合122。应了解，尾端130a贴附到导线接合122所使用的上述电流、力和/时间仅仅是例示性的，且参数可在上文其它实施例中给出的值上下变化。应进一步了解，用于将缝线130的尾端130a贴附到导线接合122的工艺可包括尾部130a到缝线120的从缝线球126延伸的一部分的物理连接、尾部130a到缝线球126本身的物理连接或两者。
如在图10A中所见，毛细管在贴附缝线130的末端130a之后可立即将从导线接合122延伸的缝线120部分压平(例如，在部分120a处)。除了提供扁平接合表面用于连接尾端130a以外，将从导线接合122延伸的缝线120压平可进一步用以减少缝线120的高度。
在尾端130a贴附到导线接合122之后，导线接合毛细管接着放松一小段导线，并将导线从导线接合122的表面撕下。接着使用从毛细管的末端悬挂的导线的小尾部以形成用于下一随后缝线的缝线球136。可重复上述循环直至在电路小片104与电路小片102上的导线接合122之间形成所有缝线130为止。应了解，可存在比图10中所示的缝线多得多的缝线130。
根据本发明的缝合系统提供优于如发明背景部分中所论述的包括球-导线-球配置的常规系统的改进。首先，本发明系统需要较少的步骤和较少的制造时间。具体来说，常规反向接合技术需要缝线球形成在缝线的前端和尾端两者处。相反，本发明仅需要在缝线的前端处的缝线球。缝线的尾端可直接楔形接合到下方电路小片的前端导线接合。这导致与常规反向接合技术相比将缝线形成周期时间减少例如30％到50％。此外，替代于球-导线-球配置，在中间电路小片(即，在堆叠中的最上层电路小片下方)上的导线接合具有体积不大的导线层叠式配置，从而提供减少电噪音且较大稳定性的益处。较大的稳定性导致较低的缝线破裂率。举例来说，当现有技术的四电路小片微SD封装可具有2000PPM的良率损失时，根据本发明所接合的相同封装导线可具有400PPM以下的良率损失。
依据在堆叠中包括多少半导体电路小片，可重复步骤204(如由图6中的虚线箭头所指示)以在电路小片堆叠中的任何额外半导体电路小片上形成缝线。举例来说，在图7到图10中，仅存在两个半导体电路小片，所以在形成缝线130之后，可如下文所解释而包封且单一化导线连接的半导体封装。然而，在图11到图12中，电路小片堆叠包括第三半导体电路小片110。因此，重复步骤204使得如上所述形成缝线140。即，缝线140的前端附着到接合垫144，且缝线140的尾端直接贴附到电路小片104上的导线接合132的顶部。应了解，可在存在一个或一个以上额外电路小片安装在电路小片110的顶部上的情况下重复步骤204一次或一次以上。
在上述实施例中，首先将电路小片堆叠中的所有电路小片安装在衬底上，且接着将其导线接合到一起。在替代实施例中，可将电路小片贴附到堆叠，且接着在添加堆叠中的下一电路小片之前如上文所述来接合导线。
在上述实施例中，缝线可以是未涂覆的金，但其或者可以是铜、铝或其它金属。在本发明的其它实施例中，缝线可使用聚合绝缘层来预绝缘，所述聚合绝缘层使导线的表面是非导电的。适合用于本发明的预绝缘缝线的两个实例揭示于题为“树脂涂覆的接合导线、其制造方法和半导体装置(Resin Coated Bonding Wire，Method Of ManufacturingThe Same，And Semiconductor Device)”的第5,396,106号美国专利以及题为“高密度集成电路及其封装方法(High Density Integrated Circuits And The Method Of Packaging theSame)”的第2004/0124545号美国公开专利申请案中，所述专利和专利申请案两者全文以引用的方式并入本文中。
如图12中所示，在形成电路小片堆叠且将电路小片堆叠彼此且与衬底106电耦合之后，可在步骤210中将电路小片堆叠装入在模塑料150内。模塑料150可以是例如可从住友(Sumitomo)公司和日东电工(Nitto Denko)公司购得的已知环氧树脂，两个公司的总部均设在日本。如上文所指示，半导体封装在面板上一次形成许多个。因此，在包封之后，在步骤212中，各自封装可从面板单一化以形成完成的半导体封装160。在一些实施例中，在步骤220中，完成的封装160可视情况密封在盖子内。
如图中所示，堆叠中的不同半导体中的所有相应(对准)缝线电短接在一起。举例来说，在图11中，沿着电路小片102、104和110的最右边缘标记的三个缝线120、130和140短接在一起。通过仅启用堆叠中的一个电路小片(经由未图示的电路小片启用信号连接)来将信号发送到特定电路小片102、104或110且从特定电路小片102、104或110发送信号，使得可沿着特定缝线连接路径来发送信号，但仅有启用的电路小片将接收信号且进行响应。
如图12中所示的半导体封装160可用作快闪存储器装置。在此类实施例中，在封装160内使用的半导体电路小片102、104和/或110可以是快闪存储器芯片。除了电路小片102、104和110之外，封装160还可包括例如ASIC的控制器，使得封装160可用作快闪存储器装置。在实施例中，完成的封装160可包括如上文所述导线接合的四个存储器电路小片和控制器电路小片。在其它实施例中，完成的封装160可包括如上文所述导线接合的八个存储器电路小片和控制器电路小片。应了解，封装160可包括其它数目的存储器电路小片。
封装160可用于标准快闪存储器外壳中，包括例如SD卡、紧凑式闪存(compactflash)、智能媒体、迷你SD卡、MMC和xD卡或存储棒。其它标准快闪存储器封装也是可能的。在本发明的其它实施例中，封装160或者可包括经配置以执行其它功能的半导体电路小片。
已出于说明和描述的目的呈现本发明的以上详细描述。其并不希望是详尽的或将本发明限于所揭示的精确形式。根据上述教示，许多修改和变化是可能的。选择所描述的实施例以便最佳地解释本发明的原理及其实践应用，从而使所属领域的技术人员能够以各种实施例且在作出适合于所预期的特定用途的各种修改的情况下最佳地利用本发明。希望本发明的范围由本文所附的权利要求书来界定。

Claims (42)

1.一种制造半导体装置的方法，其包含以下步骤：
(a)将第一半导体电路小片贴附到一组件，所述第一半导体电路小片包括用于接纳导线接合的垫；
(b)将第一缝线的第一末端导线接合到所述第一半导体电路小片垫，以在所述第一缝线的所述第一末端与所述第一半导体电路小片垫之间形成导线接合；
(c)将第二半导体电路小片垫贴附到所述第一半导体电路小片，所述第二半导体电路小片包括用于接纳导线接合的垫；
(d)将第二缝线的第一末端导线接合到所述第二半导体电路小片垫；
(e)在所述步骤(d)中导线接合所述第二缝线的所述第一末端之后，将所述第二缝线的第二末端直接导线接合到所述步骤(b)中形成的所述导线接合。
2.根据权利要求1所述的方法，其中所述将第一半导体电路小片贴附到一组件的步骤(a)包含将第一半导体电路小片贴附到衬底的步骤。
3.根据权利要求1所述的方法，其中所述将第一半导体电路小片贴附到一组件的步骤(a)包含将第一半导体电路小片贴附到第三半导体电路小片的步骤。
4.根据权利要求1所述的方法，其中所述将第一缝线的第一末端导线接合到所述第一半导体电路小片垫的步骤(b)包含形成缝线球且将所述缝线球贴附到所述第一半导体电路小片垫的步骤，所述第一缝线的所述第一末端从所述缝线球延伸。
5.根据权利要求4所述的方法，其中所述将所述第二缝线的第二末端直接导线接合到在所述步骤(b)中形成的所述导线接合的步骤(e)包含将所述第二缝线的所述第二末端直接导线接合到所述第一缝线的所述第一末端顶上的步骤。
6.根据权利要求4所述的方法，其中所述将所述第二缝线的第二末端直接导线接合到在所述步骤(b)中形成的所述导线接合的步骤(e)包含将所述第二缝线的所述第二末端直接导线接合到所述第一缝线的所述缝线球顶上的步骤。
7.根据权利要求1所述的方法，其中所述步骤(e)包含抵靠所述第一缝线的所述第一末端与所述第一垫之间的所述导线接合而与所述第二缝线的所述第二末端形成楔形接合的步骤。
8.根据权利要求1所述的方法，其中所述将第二缝线的第一末端导线接合到所述第二半导体电路小片垫的步骤(d)包含形成缝线球且将所述缝线球贴附到所述第二半导体电路小片垫的步骤，所述第二缝线的所述第一末端从所述缝线球延伸。
9.根据权利要求1所述的方法，其中所述将所述第二缝线的第二末端直接导线接合到在所述步骤(b)中形成的所述导线接合的步骤(e)包含以下步骤：抵靠所述第一缝线的所述第一末端挤压所述第二缝线的所述第二末端，以及施加热、电流和超声能中的至少一者。
10.根据权利要求1所述的方法，其进一步包含将至少所述半导体电路小片和缝线包封在模塑料中的步骤。
11.一种制造半导体装置的方法，其包含以下步骤：
(a)将第一半导体电路小片贴附到一组件，所述第一半导体电路小片包括用于接纳导线接合的垫；
(b)在所述第一半导体电路小片与所述组件之间通过前向球形接合工艺形成第一缝线，所述第一缝线的前端接合到所述第一半导体电路小片垫且所述第一缝线的尾端接合到所述组件；
(c)将第二半导体电路小片贴附到所述第一半导体电路小片，所述第二半导体电路小片包括用于接纳导线接合的垫；
(d)在所述第二半导体电路小片与所述第一半导体电路小片之间通过前向球形接合工艺形成第二缝线，使所述第二缝线的前端接合到所述第二半导体电路小片垫且所述第二缝线的尾端直接导线接合到所述第一缝线的所述前端。
12.根据权利要求11所述的方法，其中所述将第一半导体电路小片贴附到一组件的步骤(a)包含将第一半导体电路小片贴附到衬底的步骤。
13.根据权利要求11所述的方法，其中所述在所述第一半导体电路小片垫与所述组件之间通过前向球形接合工艺形成第一缝线的步骤(b)包含形成缝线球且将所述缝线球贴附到所述第一半导体电路小片垫的步骤，所述第一缝线的所述前端从所述缝线球延伸。
14.根据权利要求13所述的方法，其中所述形成第二缝线使得所述第二缝线的尾端直接接合到所述第一缝线的所述前端的步骤(d)包含将所述第二缝线的所述尾端直接导线接合到从所述缝线球延伸的所述第一缝线的所述前端顶上的步骤。
15.根据权利要求13所述的方法，其中所述形成第二缝线使得所述第二缝线的尾端直接接合到所述第一缝线的所述前端的步骤(d)包含将所述第二缝线的所述尾端直接导线接合到所述第一缝线的所述缝线球顶上的步骤。
16.根据权利要求11所述的方法，其中所述步骤(d)包含抵靠所述第一缝线的所述前端而与所述第二缝线的所述尾端形成楔形接合的步骤。
17.根据权利要求11所述的方法，其中所述在所述第一半导体电路小片与所述第二半导体电路小片之间形成第二缝线的步骤(d)包含形成缝线球且将所述缝线球贴附到所述第二半导体电路小片垫的步骤，所述导线接合的所述前端从所述缝线球延伸。
18.一种制造半导体装置的方法，其包含以下步骤：
(a)将第一半导体电路小片贴附到衬底，所述第一半导体电路小片包括用于接纳导线接合的垫；
(b)在第一缝线的前端上形成缝线球；
(c)将在所述步骤(b)中形成的所述缝线球导线接合到所述第一半导体电路小片垫，以在所述第一缝线的所述前端与所述第一半导体电路小片垫之间形成导线接合；
(d)将所述第一缝线的尾端导线接合到所述衬底；
(e)将第二半导体电路小片贴附到所述第一半导体电路小片，所述第二半导体电路小片包括用于接纳导线接合的垫；
(f)在第二缝线的前端上形成缝线球；
(g)将在所述步骤(f)中形成的所述缝线球导线接合到所述第二半导体电路小片，以在所述第二缝线的所述前端与所述第二半导体电路小片垫之间形成导线接合；
(h)在所述步骤(g)中导线接合所述第二缝线的所述前端之后，使用楔形接合将所述第二缝线的尾端直接导线接合到在所述步骤(c)中形成的所述导线接合。
19.根据权利要求18所述的方法，其中所述将所述第二缝线的尾端直接导线接合到在所述步骤(c)中形成的所述导线接合的步骤(h)包含将所述第二缝线的所述尾端直接导线接合到从所述缝线球延伸的所述第一缝线的所述前端顶上的步骤。
20.根据权利要求18所述的方法，其中所述将所述第二缝线的尾端直接导线接合到在所述步骤(c)中形成的所述导线接合的步骤(h)包含将所述第二缝线的所述尾端直接导线接合到在所述步骤(b)中形成的所述缝线球的顶上的步骤。
21.根据权利要求18所述的方法，其进一步包含以下步骤：
(k)将第三半导体电路小片贴附到所述第二半导体电路小片，所述第三半导体电路小片包括用于接纳导线接合的垫；
(l)在第三缝线的前端上形成缝线球；
(m)将在所述步骤(1)中形成的所述缝线球导线接合到所述第三半导体电路小片垫，以在所述第三缝线的所述前端与所述第三半导体电路小片垫之间形成导线接合；
(o)在所述步骤(m)中导线接合所述第三缝线的所述前端之后，使用楔形接合将所述第三缝线的尾端直接导线接合到在所述步骤(g)中形成的所述导线接合。
22.根据权利要求18所述的方法，其中所述将所述第二缝线的第二末端直接导线接合到在所述步骤(b)中形成的所述导线接合的步骤(e)包含抵靠所述第一缝线的所述第一末端挤压所述第二缝线的所述第二末端以及施加热、电流和超声能中的至少一者的步骤。
23.根据权利要求18所述的方法，其进一步包含将至少所述半导体电路小片与缝线包封在模塑料中的步骤。
24.一种半导体装置，其包含：
衬底，其包括多个接触垫；
第一半导体电路小片，其安装到所述衬底，所述第一半导体电路小片包括多个接合垫；
第一组缝线，其导线接合在所述第一半导体电路小片的所述电路小片接合垫与所述衬底的所述接触垫之间；
第二半导体电路小片，其安装在所述第一半导体电路小片上，所述第二半导体电路小片包括多个接合垫；
第二组缝线，其具有接合到所述第二半导体电路小片的所述电路小片接合垫的前端和楔形接合在所述第一组缝线的顶部上的尾端，所述第一组缝线导线接合到所述第一半导体电路小片的所述电路小片接合垫。
25.根据权利要求24所述的半导体装置，其进一步包含包封至少所述第一和第二半导体电路小片以及第一组和第二组缝线的模塑料。
26.根据权利要求24所述的半导体装置，其中所述第一组缝线包括具有贴附到所述第一半导体电路小片的所述电路小片接合垫的缝线球的前端。
27.根据权利要求26所述的半导体装置，其中所述第二组缝线的所述尾端楔形接合到所述第一组缝线的从所述第一组缝线的末端处的所述缝线球延伸的部分。
28.根据权利要求26所述的半导体装置，其中所述第二组缝线的所述尾端楔形接合到所述第一组缝线的末端处的所述缝线球。
29.根据权利要求24所述的半导体装置，其中所述第二组缝线的所述前端包括贴附到所述第二半导体电路小片的所述电路小片接合垫的缝线球。
30.根据权利要求24所述的半导体装置，其中所述第一和第二缝线由金、铝和铜中的一者形成。
31.根据权利要求24所述的半导体装置，其中所述第一和第二半导体电路小片是快闪存储器电路小片。
32.根据权利要求31所述的半导体装置，其进一步包含电耦合到所述衬底的控制器电路小片。
33.根据权利要求24所述的半导体装置，其中所述半导体装置是快闪存储器装置。
34.根据权利要求33所述的半导体装置，其中所述快闪存储器装置是SD卡、紧凑式闪存、智能媒体、迷你SD卡、MMC和xD卡或存储棒中的一者。
35.一种半导体装置，其包含：
衬底，其包括多个接触垫；
第一半导体电路小片，其安装到所述衬底，所述第一半导体电路小片包括多个接合垫；
第一组缝线，其具有形成到缝线球中的前端和楔形接合到所述衬底的尾端，其中所述缝线球接合到所述第一半导体电路小片的所述电路小片接合垫。
第二半导体电路小片，其安装在所述第一半导体电路小片上，所述第二半导体电路小片包括多个接合垫；
第二组缝线，其具有形成到缝线球中的前端和楔形接合到所述第一组缝线的顶部上的尾端，其中所述缝线球接合到所述第二半导体电路小片的所述电路小片接合垫，且所述第一组缝线导线接合到所述第一半导体电路小片的所述电路小片接合垫。
36.根据权利要求35所述的半导体装置，其进一步包含包封至少所述第一和第二半导体电路小片以及第一组和第二组缝线的模塑料。
37.根据权利要求35所述的半导体装置，其进一步包含：
第三半导体电路小片，其包括电路小片接合垫；以及
第三组缝线，其具有形成到缝线球中的前端和楔形接合到所述第二组缝线的顶部上的尾端，其中所述缝线球接合到所述第三半导体电路小片的所述电路小片接合垫，且所述第二组缝线导线接合到所述第二半导体电路小片的所述电路小片接合垫。
38.根据权利要求35所述的半导体装置，其中所述第二组缝线的所述尾端楔形接合到所述第一组缝线的从所述第一组缝线的末端处的所述缝线球延伸的部分。
39.根据权利要求35所述的半导体装置，其中所述第二组缝线的所述尾端楔形接合到所述第一组缝线的末端处的所述缝线球。
40.一种半导体装置，其包含：
衬底，其包括多个接触垫；
多个半导体电路小片，其安装到所述衬底且以偏移配置彼此上下堆叠，所述多个半导体电路小片的每一半导体电路小片包括多个电路小片接合垫；
多个缝线组，每一缝线组中的每一缝线包括前端和尾端，其中所述前端形成到缝线球中且接合到半导体电路小片的所述多个电路小片接合的电路小片接合垫，且所述尾端楔形接合到相邻半导体电路小片的所述电路小片接合垫上的缝线的所述前端。
41.根据权利要求40所述的半导体装置，其中所述缝线的所述尾端楔形接合到所述缝线的从所述相邻半导体电路小片的电路小片接合垫上的所述缝线球延伸的部分。
42.根据权利要求40所述的半导体装置，其中所述缝线的所述尾端楔形接合到所述相邻半导体电路小片的电路小片接合垫上的所述缝线球。
CN200810127580A 2008-06-27 2008-06-27 半导体装置中的导线层叠式缝线接合 Pending CN101615587A (zh)

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