CN101315920A - 芯片堆栈封装结构及其制造方法 - Google Patents

芯片堆栈封装结构及其制造方法 Download PDF

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Publication number
CN101315920A
CN101315920A CNA2007101058298A CN200710105829A CN101315920A CN 101315920 A CN101315920 A CN 101315920A CN A2007101058298 A CNA2007101058298 A CN A2007101058298A CN 200710105829 A CN200710105829 A CN 200710105829A CN 101315920 A CN101315920 A CN 101315920A
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chip
base material
active surface
line layer
package structure
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CN100559582C (zh
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潘玉堂
周世文
林峻莹
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Chipmos Technologies Inc
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Chipmos Technologies Inc
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Abstract

本发明提供一种芯片堆栈封装结构及其制造方法，该封装结构包括：基材、第一芯片、线路基板以及第二芯片。其中该基材具有第一表面与相对的第二表面，且第一芯片位于基材的第一表面，第一芯片具有第一主动面与相对的第一晶背，并与基材以倒装焊封装接合方式电性连接。形成于第一晶背上的线路基板，包括配置于第一晶背上的介电层，以及形成于介电层上的图案化线路层，并通过打线使图案化线路层与基材电性连结。第二芯片位于图案化线路层上，具有第二主动面以及配置于第二主动面上的至少一个第二焊垫，其中焊垫与图案化线路层电性连接，再经由打线与基材电性连接。

Description

芯片堆栈封装结构及其制造方法
技术领域
本发明涉及一种半导体封装结构，且尤其涉及一种堆栈封装结构及其制造方法。
背景技术
随着电子产品功能与应用的需求的急遽增加，封装技术也朝着高密度微小化、单芯片封装到多芯片封装、二维尺度到三维尺度的方向发展。其中系统化封装技术(SystemIn Package)一种可整合不同电路功能芯片的较佳方法，利用表面粘着(Surface Mount Technology；SMT)工艺将不同的芯片堆栈整合于同一基板上，借以有效缩减封装面积。具有体积小、高频、高速、生产周期短与低成本的优点。
请参照图4，图4为根据一现有的芯片堆栈封装结构400所绘示的结构剖面图。芯片堆栈封装结构400包括基板410、第一芯片420、第二芯片430以及多条打线440和450。其中第一芯片420固设于基材410之上，并通过打线440与基材410电性连接。第二芯片430堆栈于第一芯片420之上，且通过打线450与基板410电性连接。
然而，由于迭设于上层的芯片，例如第二芯片430，必须迁就下层芯片(第一芯片420)的打线(打线440)配置，因此上层芯片(第二芯片430)尺寸必须小于下层芯片。因此也限制了芯片堆栈的数量与弹性。又因为上层芯片的尺寸较小，必须延长打450的配线长度并扩大其线弧，方能使其与基材410电性连接。当后续进行压模工艺时，该些被延长的打线容易受到冲移，而出现短路的现象，影响工艺良率。
请参照图5，图5为根据另一种芯片堆栈封装结构500所绘示的结构剖面图。芯片堆栈封装结构500包括基板510、第一芯片520、第二芯片530、多条打线540和550以及位于第一芯片520和第二芯片530的间的虚拟芯片560。其中第一芯片520迭设于基板510上，并通过打线540使第一焊垫570与基材510电性连接；虚拟芯片560迭设于第一芯片520之上；第二芯片则迭设于虚拟芯片560之上，并通过打线550使第二焊垫580与基材510电性连接。通过尺寸小于第一芯片520的虚拟芯片560的设置，不仅可在第一芯片520和第二芯片530之间，提供足够的布线空间与线弧高度，以容纳打线540，而且不会限制上层芯片(第二芯片530)的堆栈尺寸。因此第二芯片530的尺寸实质等于第一芯片520的尺寸。
然而虚拟芯片的设置，不仅会增加芯片堆栈的厚度，且徒增工艺成本，更限制了装结构微小化与高密度的趋势。
因此，有需要提供一种良率高、工艺低廉且不会限制封装密度的芯片堆栈封装结构。
发明内容
本发明所要解决的技术问题在于提供一种芯片堆栈封装结构包以解决现有技术技术中电性连接上层芯片与基材的打线配线长度过长以及线弧过大的问题，从而解决现有技术芯片堆栈封装结构良率封及封装密度不高的问题。
为实现上述目的，该芯片堆栈封装结构包括：基材、第一芯片、线路基板、第二芯片以及封胶树脂(molding compound)。其中该基材具有第一表面与相对的第二表面，且第一芯片位于基材的第一表面，第一芯片具有第一主动面与相对的第一晶背，第一主动面面对基材，并与基材以倒装焊封装接合方式电性连接。位于第一晶背上的线路基板包括配置于第一晶背上的介电层，以及形成于介电层上的图案化线路层，并通过打线使图案化线路层与基材电性连结。第二芯片位于图案化线路层上，具有第二主动面以及配置于第二主动面上的至少一个第二焊垫，其中第二焊垫与图案化线路层电性连接，再经由打线与基材电性连接。封胶树脂则填充于基材、第一芯片、线路基板及第二芯片之间，最后再于基材的第二表面形成多个外部端子，这些外部端子较佳可以是，例如锡球。通过这些外部端子，得以使芯片堆栈封装结构电性连接至其它外部电路。
本发明的又一目的在提供一种芯片堆栈封装结构的制造方法，以解决现有技术技术中电性连接上层芯片与基材的打线配线长度过长以及线弧过大的问题，从而解决现有技术芯片堆栈封装结构良率封及封装密度不高的问题。
为实现上述目的，该芯片堆栈封装结构的制造方法，包括下述步骤：首先提供一基材，其中该基材具有第一表面与相对的第二表面，于基材的第一表面配置第一芯片，使第一芯片面对基材的第一主动面与基材以倒装焊封装方式电性连接。接着，于第一芯片相对于第一主动面的第一晶背上形成线路基板，使线路基板包括位于晶背上的介电层，以及形成于介电层上的图案化线路层，其中图案化线路层包括至少一条导线，与欲堆栈于图案化线路层上的第二芯片的至少一个第二焊垫电性匹配。然后，形成至少一条打线，借以电性连结图案化线路层与基材。再于图案化线路层之上配置第二芯片，并使第二芯片的焊垫电性连接至图案化线路层的导线，再经由打线与基材电性连接。接着，使用封胶体封装基材、第一芯片、线路基板及第二芯片，最后再于基材的第二表面形成多个外部端子，这些外部端子较佳可以是，例如锡球。通过这些外部端子，得以使芯片堆栈封装结构电性连接至其它外部电路。
根据以上所述的实施例，本发明的技术特征在倒装焊封装堆栈的下层芯片的晶背上，形成一个图案化线路层，使图案化线路层的布线和后续堆栈于其上的上层芯片的焊垫电性匹配。接着，再将上层芯片倒装焊封装堆栈于图案化线路层上。通过图案化线路层的布线，将上层芯片的焊垫的打线位置重新分配，使其分散至上层芯片的边缘，再通过打线使图案化线路层与基材电性连接。借此，解决现有技术中，电性连接上层芯片与基材的打线配线长度过长以及线弧过大的问题。
因此，通过本发明所提供的技术优势，可以解决现有芯片堆栈封装结构良率封及封装密度不高的问题。
附图说明
为让本发明之上述和其它目的、特征、优点与实施例能更明显易懂，所附附图的详细说明如下：
图1为根据本发明的第一较佳实施例所绘示的芯片堆栈封装结构100的剖面示意图；
图2为根据本发明的第二较佳实施例所绘示的芯片堆栈封装结构200的剖面示意图；
图3为根据本发明的第三较佳实施例所绘示的芯片堆栈封装结构300的剖面示意图；
图4为根据一习知的芯片堆栈封装结构400所绘示的结构剖面图；
图5为根据另一种芯片堆栈封装结构500所绘示的结构剖面图。
其中，附图标记：
100：芯片堆栈封装结构    101：基材
102：第一芯片            103：第一主动面
104：第一晶背            105：图案化线路层
105a：导线               105b：导线
106：打线                107：第二芯片
108：第二主动面          109：第二焊垫
110：凸块                111：外部连接端子
113：凸块
114：底胶                115：第一焊垫
116：基材第一表面        117：基材第二表面
120：封胶树脂            123：线路基板
200：芯片堆栈封装结构    201：基材
202：第一芯片            203：第一主动面
204：第一晶背            205：图案化线路层
205a：导线               205b：导线
206：打线                207：第二芯片
208：第二主动面          209：焊垫
210：凸块                211：外部连接端子
213：凸块                214：底胶
215：焊垫                216：散热鳍片
217：贯穿开口            218：基材第一表面
219：基材第二表面        220：封胶树脂
223：线路基板            300：芯片堆栈封装结构
301：基材                302：第一芯片
303：第一主动面          304：第一晶背
305：图案化线路层        305a：导线
305b：导线               306：打线
307：第二芯片            308：第二主动面
309：焊垫                310：凸块
311：外部连接端子        313：凸块
314：底胶                315：焊垫
316：基材第一表面        317：贯穿开口
318：打线                319：基材第二表面
320：封胶树脂            323：线路基板
400：芯片堆栈封装结构    410：基板
420：第一芯片            430：第二芯片
440：打线                450：打线
510：基板                520：第一芯片
530：第二芯片            540：打线
550：打线                560：虚拟芯片
570：焊垫                580：焊垫
具体实施方式
为让本发明之上述和其它目的、特征、优点与实施例能更明显易懂，特提供数种芯片堆栈封装结构作为较佳实施例来进一步说明。
请参照图1，图1为根据本发明的第一较佳实施例所绘示的芯片堆栈封装结构100的剖面示意图。
芯片堆栈封装结构100包括：基材101第一芯片102、线路基板123、第二芯片107以及封胶树脂120。
首先提供一基材101，该基材具有一第一表面116以及相对的第二表面117。在本发明的较佳实施例之中，基材101由导线架(Lead Frame)、印刷电路板(Printing Circuit Board)或晶粒承载器(Carrier)所构成。而在本实施例之中，基材101为一印刷电路板，其材质例如是BT或者是FR4电路板或者是其它软性电路板。
接着将第一芯片102倒装焊封装接合于基材101的第一表面，使第一芯片102面对基材101的第一主动面103与基材101电性连接。在本实施例之中，第一芯片102另具有与第一主动面103相对的第一晶背104，且第一主动面103具有多个第一焊垫115，并通过多个凸块113，将这些第一焊垫115与基材101电性连接。另外，在将第一芯片102迭设于基材101的第一表面之后，还包括使用一底胶114将凸块包覆，并借以将第一主动面103固定于基材101的第一表面118。
接着，于第一芯片102的第一晶背104上形成一线路基板123。其中线路基板123包括位于第一晶背104上的介电层120，以及形成于介电层120上的图案化线路层105，并通过至少一条打线106使图案化线路层105与基材101电性连结。其中图案化线路层105为一重布线路层(Redistribution-Layer，RDL)，且图案化线路层105包括多条导线，例如导线105a和105b，每一条导线(例如导线105a)的一端，设计用来与即将迭设于图案化线路层105上的第二芯片107中的一第二焊垫109电性匹配，另一端则往第一晶背104的其它位置延伸，例如往晶背的边缘延伸。
然后，将第二芯片107以倒装焊封装接合方式电性连接于图案化线路层105。第二芯片107具有第二主动面108以及配置于第二主动面108上的第二焊垫109，其中每一个第二焊垫109通过锡球或导电凸块110，与图案化线路层105的导线105a或105b电性连接。在其它实施例之中，图案化线路层105可以配合不同芯片的焊垫配置改变配线图案。
之后，使用封胶树脂120来封装基材101、第一芯片102、线路基板223及第二芯片107，使封胶树脂120填充于基材101、第一芯片102、线路基板223及第二芯片107之间。最后再于基材101的第二表面117形成多个外部连接端子111，这些外部端子111较佳可以是，例如锡球。通过这些外部连接端子111，得以使芯片堆栈封装结构100电性连接至其它外部电路。
由于第二芯片107的至少一第二焊垫109会与图案化线路层105的其中一条导线，例如导线105a或105b电性匹配，因此，当具有与第一芯片102相同尺寸的第二芯片107与第一芯片102相互堆栈时，图案化线路层105的导线可以将原来靠近第二芯片107中心的第二焊垫109重新布线，使其分散至第二芯片107的其它位置，例如分散至第二芯片107的边缘，再经由打线106使第二焊垫109与基材101电性连结。
请参照图2，图2为根据本发明的第二较佳实施例所绘示的芯片堆栈封装结构200的剖面示意图。
芯片堆栈封装结构200包括：基材201、第一芯片202、线路基板223、第二芯片207，封胶树脂220。
首先提供基材201，且该基材201具有第一表面218以及相对于第一表面218的第二表面219。在本发明的较佳实施例之中，基材201较佳由导线架、印刷电路板或晶粒承载器所构成。而在本实施例之中，基材201为一晶粒承载器，其材质例如是BT或者是FR4电路板或者是其它软性电路板。
接着在基材201上形成一个贯穿开口217。再将第一芯片202倒装焊封装接合于基材201的第一表面218，使第一芯片202面对基材201的第一主动面203与基材201电性连接。在本实施例中，第一芯片202另具有与第一主动面203相对的第一晶背204，且第一主动面203具有多个第一焊垫215，而这些第一焊垫215则通过多个凸块213与基材201电性连接。另外，在本实施例之中，在将第一芯片202倒装焊封装接合于基材201的第一表面218后，还包括使用底胶214将多个凸块213包覆，并借以将第一主动面203固定于基材201的第一表面218上。
由于有一部分的第一主动面203，会通过基材201的贯穿开口217暴露出来。因此在本实施例之中，还包括在第一主动面203上形成一个散热鳍片216，使其并经由该贯穿开口217向外延伸，借此增加芯片堆栈封装结构200的散热效果。
然后，于第一芯片202的第一晶背204上形成一线路基板223。其中线路基板223包括位于第一晶背204上的介电层220，以及形成于介电层220上的图案化线路层205，并通过至少一条打线206使图案化线路层205与基材电性连结。其中图案化线路层205一重布线路层。且图案化线路层205包括多条导线，例如导线205a和205b，且每一条导线(例如导线205a)的一端，设计用来与即将迭设于图案化线路层205上的第二芯片207其中的一个第二焊垫209电性匹配，另一端则往第一晶背204的其它位置延伸，例如往第一晶背204的边缘延伸。
再将第二芯片207以倒装焊封装接合方式电性连接于图案化线路层205。第二芯片207具有第二主动面208以及配置于第二主动面208上的第二焊垫209，其中至少一个第二焊垫209通过锡球或导电凸块210与图案化线路层205的导线205a或205b电性连接。在其它实施例之中，图案化线路层205可以配合不同芯片的焊垫配置改变配线图案。
之后，使用封胶树脂220来封装基材201、第一芯片202、线路基板223及第二芯片207，使封胶树脂220填充于基材201、第一芯片202、线路基板223及第二芯片207之间。最后再于基材201的第二表面219形成多个外部端子211，这些外部端子较佳可以是，例如锡球。通过这些外部端子211，得以使芯片堆栈封装结构200电性连接至其它外部电路。
由于第二芯片207的至少一个第二焊垫209会与图案化线路层205的其中一条导线，例如导线205a或205b电性匹配，因此，当具有与第一芯片202相同尺寸的第二芯片207与第一芯片202相互堆栈时，图案化线路层205的导线可以将原来靠近第二芯片207中心的第二焊垫209重新布线，使其分散至第二芯片207的其它位置，例如分散至第二芯片207的边缘，再经由打线206使第二焊垫209与基材201电性连结。
请参照图3，图3根据本发明的第三较佳实施例所绘示的芯片堆栈封装结构300的剖面示意图。
芯片堆栈封装结构300，包括：基材301、第一芯片302、线路基板323、第二芯片307、封胶树脂320。
首先提供基材301，使基材301具有一第一表面316以及相对的第二表面319。在本实施例之中，基材301较佳由导线架、印刷电路板或晶粒承载器所构成。而在本实施例之中，基材301一晶粒承载器，其材质例如是BT或者是FR4电路板或者是其它软性电路板。
接着在基材301上形成一个贯穿开口317。再将第一芯片302倒装焊封装接合于基材301的第一表面316，使第一芯片302面对基材301的第一主动面303与基材301电性连接。
在本实施例之中，第一主动面303还具有与第一主动面303相对的第一晶背304，且一部分的第一主动面303通过基材301的贯穿开口317暴露出来。第一芯片302具有多个第一焊垫309第一焊垫309，位于第一主动面303由贯穿开口317暴露出来的区域中。而这些第一焊垫309第一焊垫309则通过穿过贯穿开口317的打线318，与基材301电性连接。
然后，于第一芯片302的第一晶背304上形成一线路基板323。其中线路基板323包括位于第一晶背304上的介电层320，以及形成于介电层320上的图案化线路层305，并通过至少一条打线306使图案化线路层305与基材301电性连结。其中图案化线路层305为一重布线路层。且图案化线路层305包括多条导线，例如导线305a和305b，且每一条导线(例如导线305a)的一端设计用来与即将迭设于图案化线路层305上的第二芯片307中的一个第二焊垫309电性匹配，另一端则往第一晶背304的其它位置例如是第一晶背边缘延伸。
再将第二芯片307以倒装焊封装接合方式电性连接于图案化线路层305。第二芯片307具有第二主动面308以及配置于第二主动面308上的第二焊垫309，其中至少一个第二焊垫309通过锡球或导电凸块310与图案化线路层305的导线305a或305b电性连接。在其它实施例之中，图案化线路层305可以配合不同芯片的焊垫配置改变配线图案。之后，使用封胶树脂320来封装基材301、第一芯片302、线路基板323及第二芯片307，使封胶树脂320填充于基材301、第一芯片302、线路基板323及第二芯片307之间，最后再于基材301的第二表面319形成多个外部端子311，这些外部端子较佳可以是，例如锡球。并通过这些外部端子311，芯片堆栈封装结构300可以电性连接至其它外部电路。
由于第二芯片307的每一个第二焊垫309会与图案化线路层305的其中一条导线，例如导线305a或305b匹配，因此当具有与第一芯片302相同尺寸的第二芯片307与第一芯片102相互堆栈时，图案化线路层305的导线可以将原来靠近第二芯片307中心的第二焊垫309重新布线，使其分散至第二芯片307的其它位置，例如分散至第二芯片307的边缘，再经由打线306使第二焊垫309与基材电性连结。
借此不仅缩短用来电性连结上层芯片与基材之间的打线长度及线弧，还可以配合不同上层芯片的焊垫设计来改电图案化线路层中的布线，以提高堆栈封装的工艺弹性。由于无需使用虚拟芯片，还可大幅降低堆栈厚度度及工艺成本，同时提高封装密度。
根据以上所述的实施例，本发明的技术特征是在倒装焊封装堆栈的下层芯片的晶背上，形成一个具有图案化线路层的线路基板，使图案化线路层的布线和后续堆栈于其上的上层芯片的焊垫匹配。接着，再将上层芯片倒装焊封装堆栈于图案化线路层上。通过图案化线路层的布线，将上层芯片的焊垫的打线位置重新分配，使其分散至上层芯片的边缘，再通过打线使图案化线路层与基材电性连接。
因此，通过本发明所提供的技术优势，可以解决现有积水撒的芯片堆栈封装结构良率封及封装密度不高的问题。
当然，本发明还可有其它多种实施例，在不背离本发明精神及其实质的情况下，熟悉本领域的普通技术人员当可根据本发明做出各种相应的改变和变形，但这些相应的改变和变形都应属于本发明所附的权利要求的保护范围。

Claims (10)

1.一种芯片堆栈封装结构，其特征在于，包括：
一基材，该基材具有一第一表面与相对的第二表面；
一第一芯片，位于该基材的第一表面，该第一芯片具有一第一主动面与一相对的第一第一晶背与至少一第一焊垫，其中该第一主动面面对该基材，并且该第一焊垫与该基材电性连接；
一线路基板，位于该第一晶背上，该线路基板包括：
一介电层，配置于第一晶背上；以及
一图案化线路层，形成于该介电层上，并通过一打线与该基材电性连结；
一第二芯片，位于该图案化线路层上，具有一第二主动面，以及配置于该第二主动面上的至少一第二焊垫，其中该第二焊垫与该图案化线路层电性连接，再经由该打线与该基材电性连接；以及
一封胶树脂，填充于该基材、该第一芯片、该线路基板及该第二芯片之间。
2.根据权利要求1所述的堆栈封装结构，其特征在于，该第一主动面具有多个第一焊垫，并通过多个凸块，将该些第一焊垫电性连接于该基材。
3.根据权利要求2所述的堆栈封装结构，其特征在于，该基材具有一贯穿开口，将该第一芯片的部分的该第一主动面暴露出来，且该第一主动面上配置有一散热鳍片，并经由该贯穿开口向外延伸。
4.根据权利要求1所述的堆栈封装结构，其特征在于，该基材具有一贯穿开口，将该第一芯片的部分的该第一主动面暴露出来，且该第一主动面具有多个第一焊垫，并通过穿过该贯穿开口的至少一打线电性连接至该基材。
5.根据权利要求1所述的堆栈封装结构，其特征在于，该图案化线路层包括多条导线，且每一该些导线的一端，与该些第二焊垫的一者匹配并电性连接，另一端则往该介电层的边缘延伸。
6.一种芯片堆栈封装结构的制造方法，其特征在于，包括：
提供一基材，该基材具有一第一表面与相对的第二表面；
于该基材的第一表面配置一第一芯片，使该第一芯片面对该基材的一第一主动面与该基材电性连接；
于该第一芯片相对于该第一主动面的一第一晶背上形成一线路基板，该线路基板包括位于该晶背上的一介电层，以及形成于该介电层上的一图案化线路层，该图案化线路层包括至少一导线，与欲堆栈于该图案化线路层上的一第二芯片的至少一第二焊垫电性匹配；
形成至少一打线，借以电性连结该图案化线路层与该基材；
于该图案化线路层上配置该第二芯片，并使该第二焊垫电性连接该导线，再经由该打线与该基材电性连接；以及
使用一封胶体封装该基材、该第一芯片、该线路基板及该第二芯片。
7.根据权利要求6所述的堆栈封装结构的制造方法，其特征在于，于该基材之上配置该第一芯片的步骤，包括：
形成多个凸块，将位于该第一主动面的多个第一焊垫，电性连接于该基材；以及
采用一底胶包覆于该些凸块。
8.根据权利要求6所述的堆栈封装结构的制造方法，其特征在于，提供该基材的步骤还包括：于该基材中形成一贯穿开口，用以将一部分的该第一主动面暴露出来。
9.根据权利要求8所述的堆栈封装结构的制造方法，其特征在于，于该基材之上配置该第一芯片的步骤包括：
形成多个凸块，将位于该第一主动面的多个第一焊垫，电性连接于该基材；
采用一底胶包覆于该些凸块以及
于该第一主动面上配置一散热鳍片，并经由该贯穿开口向外延伸。
10.根据权利要求8所述的堆栈封装结构的制造方法，其特征在于，于该基材之上配置该第一芯片的步骤包括：
将该第一芯片固设于该基材的第一表面，并使位于该第一主动面的多个第一焊垫，由该贯穿开口暴露出来；以及
在至少一第一焊垫上形成至少一打线，穿过该贯穿开口，以电性连接至该基材。
CNB2007101058298A 2007-05-30 2007-05-30 芯片堆栈封装结构及其制造方法 Expired - Fee Related CN100559582C (zh)

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CN102194779A (zh) * 2010-03-02 2011-09-21 日月光半导体制造股份有限公司 封装结构
CN103179787A (zh) * 2011-12-21 2013-06-26 美新半导体（无锡）有限公司 三轴传感器的封装结构及其封装方法
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CN102194779A (zh) * 2010-03-02 2011-09-21 日月光半导体制造股份有限公司 封装结构
CN102194779B (zh) * 2010-03-02 2013-04-17 日月光半导体制造股份有限公司 封装结构
CN103179787A (zh) * 2011-12-21 2013-06-26 美新半导体（无锡）有限公司 三轴传感器的封装结构及其封装方法
CN103179787B (zh) * 2011-12-21 2016-02-24 美新半导体（无锡）有限公司 三轴传感器的封装结构及其封装方法
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