CN103250246A - 具有线上膜及铜线的薄型多晶片堆迭封装件的方法及系统 - Google Patents

具有线上膜及铜线的薄型多晶片堆迭封装件的方法及系统 Download PDF

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CN103250246A
CN103250246A CN2011800416026A CN201180041602A CN103250246A CN 103250246 A CN103250246 A CN 103250246A CN 2011800416026 A CN2011800416026 A CN 2011800416026A CN 201180041602 A CN201180041602 A CN 201180041602A CN 103250246 A CN103250246 A CN 103250246A
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chip
copper cash
film
substrate
microns
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Inventor
赖玉清
F·Y·何
W·K·纳姆
涂莉莉
S·冯
关凯澄
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Cypress Semiconductor Corp
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Spansion LLC
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Abstract

本发明揭露一种具有线上膜及铜线的薄型多晶片堆迭封装件的系统及方法。该封装件包括衬底以及设于该衬底上方的第一芯片。铜线电性连接该第一芯片至该衬底。膜设于该第一芯片及该铜线的部分上方。另外，该膜将第二芯片粘结至该第一芯片。该膜还将该铜线与该第二芯片电性绝缘。

Description

具有线上膜及铜线的薄型多晶片堆迭封装件的方法及系统
技术领域
本发明一般涉及集成电路，尤其涉及集成电路的封装结构。
背景技术
半导体工业一直致力于使集成电路（integrated circuit；IC）具有更高的性能、更低的成本、更加微型化的组件以及更高的封装密度。随着新一代集成电路产品的发布，其功能性增加而生产该些产品所需的组件数量下降。
可透过包括若干沉积、掩膜、扩散、蚀刻以及注入步骤的工艺由硅或砷化镓晶圆(wafer)制造半导体装置。通常，许多单个装置制造于同一晶圆上。当该些装置被分离成单个矩形单元时，每一个为一IC芯片(die)。为将一芯片与其它电路接口，通常将该芯片接置于衬底上。各芯片具有焊垫，其利用极细的金线或铝线通过打线操作将焊垫与衬底连接。接着例如在模压塑料或陶瓷体中对其单独封装。
集成电路封装技术增加了半导体晶片(chip)的密度（单个电路板或衬底上接置的晶片的数量），相应降低了电路所需组件的数量。此结果导致更简洁的封装设计、更紧凑的外形尺寸（装置的物理尺寸及形状）以及总体集成电路密度的显着增加。不过，集成电路密度持续受在衬底上接置个别芯片的可用空间（或有效面积）限制。
为进一步压缩个别装置的封装，已开发出多晶片封装件，其中，在同一封装件中可包括一个以上的装置（例如IC芯片）。对于此类复杂封装设计重要的是考虑输入/输出引脚数、散热、主板与其贴附组件之间的热膨胀及收缩匹配、制造成本、集成至自动制造设备的容易度、封装可靠性以及封装件与额外封装接口，例如印刷电路板（printedcircuit board；PCB），的易适应度。
在一些情况下，与包括相同特征及功能的相应单个IC芯片相比，制造多晶片装置更快且更便宜。许多此类多晶片模组大大增加了电路密度及微型化程度，提升了信号传输速度，降低了总体的装置尺寸及重量，提升了性能且降低了成本-半导体工业的所有目标。
不过，此类多晶片模组可能体积大。集成电路封装密度由在电路板上接置芯片或模组所需的面积决定。一种减少多晶片模组的板尺寸的方法是在模组或封装件内垂直堆迭芯片或芯片。如此增加其有效密度。
两种常用的芯片堆迭方法为：（a）较大的下方芯片结合较小的上方芯片；以及（b）相同尺寸的芯片堆迭。对于前者，由于下方芯片的周边的电性焊垫延伸于顶部较小芯片的边缘以外，因此芯片在垂直方向可非常接近。对于相同尺寸的芯片堆迭，上方芯片和下方芯片在垂直方向隔开较远距离，以提供充足的间隙供下方芯片打线。然后，一旦接置芯片，即附着金焊线或铝焊线以连接上方芯片及下方芯片的打线焊垫与其相关导线架引脚延伸的末端。
在单个多晶片封装件中接置多个半导体IC晶片的其它设计包括：在导线架盘(leadframe paddle)的相对侧接置一对IC芯片；在两导线架盘上接置两晶片；一晶片接置于盘上方且一下方晶片接置于板上；一椭圆形晶片旋转贴附至另一椭圆形晶片的顶部且该另一椭圆形晶片贴附至下方的盘上；一晶片偏移贴附至另一晶片的顶部且该另一晶片贴附至下方的盘；一晶片通过其与盘之间的独立间隔物而附着于另一晶片上方；以及上述设计的各种组合。此类配置已延伸至包括在单个封装件中垂直接置三个或更多晶片。
不幸的是，此类堆迭及重迭芯片的实施严重限制打线。这些堆迭布局通常需要在下方芯片的主动面上或紧接上方贴附上方芯片。此类堆迭配置覆盖或遮挡下方芯片的焊垫的侧边的其中一些或全部。因此，所接置的上方芯片妨碍了下方芯片的打线路线。结果导致此类上方及下方半导体芯片无法打线。
发明内容
本发明实施例提供一种具有线上膜及铜线的薄型多晶片堆迭封装件的方法及系统。在一实施例中，堆迭芯片封装件包括利用粘结剂(adhesive)贴附至衬底的第一芯片。线上膜设于该第一芯片及至少第一芯片铜线的部分上方。第二芯片设于该线上膜上方。该第一芯片铜线电性连接该第一芯片至该衬底。第二芯片铜线电性连接该第二芯片至该衬底。封装胶体(encapsulant)包覆该第一芯片、该衬底、该粘结剂、该第一芯片铜线、该线上膜、该第二芯片以及该第二芯片导线。
在一些实施例中，该铜线的直径在25微米(μm)与13微米之间。在一些实施例中，该铜线为超低弧形(ultra low loop formation)。在一些实施例中，该线上膜的厚度在60微米与25微米之间。
在一些实施例中，第二膜设于该第二芯片及该第二芯片铜线的部分上方。第三芯片设于该第二芯片膜上方，且该第二芯片膜将该第二芯片铜线与该第三芯片电性绝缘。
在阅读各附图所示实施例的详细说明后，本领域的技术人员将了解本发明各实施例的上述及其它目的。
附图说明
附图示例而非限制本发明，且其中，附图中类似的附图标记代表类似的组件。
图1为依据本发明一实施例的堆迭芯片封装件的剖视图；
图2为处于早期制造阶段中的该堆迭芯片封装件的剖视图；
图3为贴附第二芯片时的该堆迭芯片封装件的剖视图；
图4为贴附该第二芯片后的该堆迭芯片封装件的剖视图；
图5为添加导线电性连接该第二芯片后该堆迭芯片封装件的剖视图；
图6为封装于封装胶体后的该堆迭芯片封装件的剖视图；
图7为依据本发明一替代实施例的堆迭三芯片封装件的剖视图；以及
图8为依据本发明一实施例的堆迭芯片封装系统的示例流程图。
具体实施方式
下面详细参照本发明的实施例，其示例显示于附图中。尽管将结合该些实施例说明本发明，但应当理解，其并非意图将本发明限于该些实施例。相反，本发明意图覆盖替代、修改及等同。这些替代、修改及等同包括于由所附权利要求定义的本发明的精神及范围内。而且，在下面对本发明实施例的详细说明中提供大量特定细节，以帮助充分理解本发明。不过，本领域的技术人员将了解，本发明可在没有这些特定细节的情况下实施。在其它情况下，为避免不必要地模糊本发明实施例的态样，对已知的方法、程序、组件及电路未作详细描述。
显示系统实施例的附图为半示意图，并非按比例绘制。尤其，一些尺寸出于清楚描述目的而在附图中放大显示。另外，对于所揭露并描述的多个实施例的共同特征，出于清楚及简化描述、说明及理解目的，类似的特征通常采用类似的附图标记。
这里将所用的术语“水平面”定义为与衬底的平面或表面平行的平面，而无关其方位。术语“垂直”指垂直于刚才所定义的水平面的方向。例如“上面”、“上方”、“下方”、“底部”、“顶部”、“侧面”（“侧壁”）、“较高”、“较低”、“较上”、“垂直上方”以及“垂直下方”等术语都相对水平面定义。
这里所用的术语“处理”包括形成所述结构所需的材料或光阻沉积、图案化、曝光、显影、蚀刻、清洗和/或材料移除等。
图1为依据本发明一实施例的堆迭芯片封装件100的剖视图。堆迭芯片封装件100为一装置，其包括利用粘结剂106贴附至衬底104的第一芯片102。线上膜（film on wire）110设于第一芯片102以及至少第一芯片铜线108的部分上方。第二芯片112设于线上膜110上方。第一芯片铜线108电性连接第一芯片102至衬底104。另外，第二芯片导线114电性连接第二芯片112至衬底104。封装胶体116包覆第一芯片102、衬底104、粘结剂106、第一芯片铜线108、线上膜110、第二芯片112以及第二芯片导线114。
图2为处于早期制造阶段中的堆迭芯片封装件100的剖视图。第一芯片102设于衬底104上方，且利用粘结剂106贴附至衬底104。粘结剂106可例如为晶圆背面压合膜粘结剂或点胶的环氧树脂。第一芯片铜线108电性连接第一芯片102至衬底104。
在当前的实施例中，第一芯片铜线108为超低弧形，例如折弧形(folded loop formation)或逆弧形(reverse loop formation)。不过，在替代实施例中，第一芯片铜线108可以其它低侧面形状配置。另外，在当前的实施例中，第一芯片铜线108的直径为13微米至25微米。不过，在替代实施例中，第一芯片铜线108的直径可小于13微米。
图3为进一步处理后的堆迭芯片封装件100的剖视图。第二芯片112正被贴附于第一芯片102。在贴附第二芯片112期间，线上膜110粘结连接第二芯片112至第一芯片102以及第一芯片铜线108。另外，线上膜110将第一芯片铜线108与第二芯片112电性隔离。
在当前的实施例中，线上膜110为第二芯片112的晶圆背面压合膜粘结剂。但是，在替代实施例中，线上膜110被预切割至预定宽度、长度及厚度，接着加工于第一芯片102以及第一芯片铜线108上。在另一实施例中，以液体粘结剂形式施加线上膜110。
图4为进一步处理后的堆迭芯片封装件100的剖视图。线上膜110设于第一芯片102上方。线上膜110粘结且覆盖第一芯片102以及至少第一芯片铜线108的部分的顶部。线上膜110为电性绝缘体，其通过将第一芯片铜线108与第二芯片112电性绝缘而將第一芯片铜线108与第二芯片112隔离。
确定线上膜110的厚度以使线上膜110的高度略高于第一芯片铜线108。例如，在当前实施例中，线上膜110的厚度为25微米至60微米。不过，在替代实施例中，线上膜110的厚度可小于25微米。
图5为进一步处理后的堆迭芯片封装件100的剖视图。第二芯片导线114电性连接第二芯片112至衬底104。在当前的实施例中，第二芯片导线114为铜。不过，在替代实施例中，第二芯片导线114可由任意导电材料构成，例如金或铝。
图6为进一步处理后的堆迭芯片封装件100的剖视图。封装胶体116包覆第一芯片102、衬底104、粘结剂106、第一芯片铜线108、线上膜110、第二芯片112以及第二芯片导线114。
图7为依据本发明一替代实施例的三堆迭芯片封装件700的剖视图。在当前的实施例中，三个芯片堆迭于三堆迭芯片封装件700中。不过，在替代实施例中，可在封装件中堆迭三个以上芯片。
三堆迭芯片封装件700为一装置，其包括利用粘结剂706贴附至衬底704的第一芯片702。第一线上膜710设于第一芯片702及至少第一芯片铜线708的部分上方。第二芯片712设于第一线上膜710上方。第一芯片铜线708电性连接第一芯片702至衬底704。另外，第二芯片铜线714电性连接第二芯片712至衬底704。
三堆迭芯片封装件700还包括设于第二芯片712及至少第二芯片铜线714的部分上方的第二线上膜716。第三芯片718设于第二线上膜716上方。另外，第三芯片导线720电性连接第三芯片718至衬底704。封装胶体722包覆第一芯片702、衬底704、粘结剂706、第一芯片铜线708、第一线上膜710、第二芯片712、第二芯片铜线714、第二线上膜716、第三芯片718以及第三芯片导线720。
在当前的实施例中，第一芯片铜线708及第二芯片铜线714为超低弧形，例如折弧形或逆弧形。不过，在替代实施例中，第一芯片铜线708及第二芯片铜线714可以其它低侧面形状配置。另外，在当前的实施例中，第一芯片铜线708及第二芯片铜线714的直径为13微米至25微米。不过，在替代实施例中，第一芯片铜线708及第二芯片铜线714的直径可小于13微米。在当前的实施例中，第三芯片导线720为铜。不过，在替代实施例中，第三芯片导线720还可由任意导电材料构成，例如金或铝。
第一线上膜710粘结且覆盖第一芯片702及至少第一芯片铜线708的部分的顶部。而且，第二线上膜716粘结且覆盖第二芯片712及至少第二芯片铜线714的部分的顶部。另外，第一线上膜710粘结连接第二芯片712至第一芯片702，以及第二线上膜716粘结连接第三芯片718至第二芯片712。
第一线上膜710及第二线上膜716为电性绝缘体，其通过将第一芯片铜线708与第二芯片712电性绝缘以及将第二芯片铜线714与第三芯片718电性绝缘而将第一芯片铜线708与第二芯片712隔离以及将第二芯片铜线714与第三芯片718隔离。因此，第一线上膜710将第一芯片铜线708与第二芯片712电性隔离。另外，第二线上膜716将第二芯片铜线714与第三芯片718电性隔离。
确定第一线上膜710的厚度以使第一线上膜710的高度略高于第一芯片铜线708。另外，确定第二线上膜716的厚度以使第二线上膜716的高度略高于第二芯片铜线714。例如，在当前的实施例中，各第一线上膜710及第二线上膜716的厚度为25微米至60微米。不过，在替代实施例中，各第一线上膜710及第二线上膜716的厚度可小于25微米。
图8显示依据本发明实施例形成堆迭芯片封装件的示例流程800。尽管该流程中揭露特定的步骤，但此类步骤为示例性质。亦即，本发明的实施例适合执行多种其它步骤或流程所示步骤的变更。
在步骤802中，利用粘结剂将第一芯片贴附至衬底。在步骤804中，利用第一芯片铜线电性连接该第一芯片至该衬底。该第一芯片铜线的直径小于或等于25微米且大于或等于13微米。在步骤806中，将第一线上膜贴附至第二芯片。该第一线上膜的厚度小于或等于60微米且大于或等于25微米。
在步骤808中，利用该第一线上膜将第二芯片贴附至该第一芯片及该第一芯片铜线。该第一线上膜将该铜线与该第二芯片电性绝缘。在步骤810中，利用第二芯片铜线电性连接该第二芯片至该衬底。
在步骤812中，将第二线上膜贴附至第三芯片。在步骤814中，利用该第二线上膜将该第三芯片贴附至该第二芯片以及该第二芯片铜线。该第二线上膜将该第二芯片铜线与该第三芯片电性绝缘。在步骤816中，将该衬底、该第一芯片、该粘结剂、该第一芯片铜线、该第一线上膜、该第二芯片、该第二芯片铜线、该第二线上膜、该第三芯片以及第三芯片导线包覆于封装胶体中。
这里出于解释目的而参照特定实施例作了上述说明。不过，上面所示实施例并非意图穷尽或将本发明限于所揭露的精确形式。针对上面的教导可进行大量修改及变更。对实施例加以选择并描述是为了最佳解释本发明的原理及其实际应用，从而使本领域的技术人员能够最佳利用本发明及不同实施例并进行各种变更以适于特定应用。

Claims (20)

1.一种装置，包括：
衬底；
第一芯片，其设于该衬底上方；
铜线，其电性连接该第一芯片至该衬底；
膜，其设于该第一芯片及该铜线的部分上方；以及
第二芯片，其设于该膜上方，
其中，该膜将该铜线与该第二芯片电性绝缘。
2.如权利要求1所述的装置，其中，该铜线的直径小于或等于25微米，且该膜的厚度小于或等于60微米。
3.如权利要求1所述的装置，其中，该铜线的直径小于或等于13微米，且该膜的厚度小于或等于25微米。
4.如权利要求1所述的装置，其中，该铜线为折弧形。
5.如权利要求1所述的装置，其中，该铜线为逆弧形。
6.如权利要求1所述的装置，进一步包括封装胶体，其包覆该衬底、该第一芯片、该铜线、该膜以及该第二芯片。
7.如权利要求1所述的装置，进一步包括：
第二芯片铜线，其电性连接该第二芯片至该衬底；
第二芯片膜，其设于该第二芯片及该第二芯片铜线的部分上方；以及
第三芯片，其设于该第二芯片膜上方，
其中，该第二芯片膜将该第二芯片铜线与该第三芯片电性绝缘。
8.一种装置，包括：
衬底；
第一芯片，其设于该衬底上方；
粘结剂，其将该第一芯片贴附至该衬底；
铜线，其电性连接该第一芯片至该衬底；
电性绝缘体，其设于该第一芯片上方；
该电性绝缘体覆盖该铜线的部分；
第二芯片，其设于该电性绝缘体上方；
第二芯片导线，其电性连接该第二芯片至该衬底，
其中，该电性绝缘体将该铜线与该第二芯片电性隔离。
9.如权利要求8所述的装置，其中，该第二芯片导线包括铜。
10.如权利要求8所述的装置，其中，该电性绝缘体粘结连接该第二芯片至该第一芯片。
11.如权利要求8所述的装置，其中，该铜线的直径小于或等于25微米且大于或等于13微米，以及该电性绝缘体的厚度小于或等于60微米且大于或等于25微米。
12.如权利要求8所述的装置，其中，该铜线为超低弧形。
13.如权利要求8所述的装置，进一步包括模压复合材料，其包覆该衬底、该第一芯片、该粘结剂、该铜线、该电性绝缘体、该第二芯片以及该第二芯片导线。
14.如权利要求8所述的装置，进一步包括：
第二电性绝缘体，其设于该第二芯片及该第二芯片导线的部分上方；以及
第三芯片，其设于该第二电性绝缘体上方，
其中，该第二电性绝缘体将该第二芯片导线与该第三芯片电性绝缘。
15.一种方法，包括：
利用粘结剂将第一芯片贴附至衬底；
利用铜线电性连接该第一芯片至该衬底；
将膜贴附至第二芯片；
将该膜贴附至该第一芯片及该铜线，其中，该膜将该铜线与该第二芯片电性绝缘；以及
电性连接该第二芯片至该衬底。
16.如权利要求15所述的方法，其中，电性连接该第二芯片至该衬底包括利用铜线电性连接该第二芯片至该衬底。
17.如权利要求15所述的方法，其中，利用铜线电性连接该第一芯片至该衬底包括利用直径小于或等于25微米且大于或等于13微米的铜线电性连接该第一芯片至该衬底。
18.如权利要求15所述的方法，其中，将膜贴附至该第一芯片及该铜线包括将厚度小于或等于60微米且大于或等于25微米的膜贴附至该第一芯片及该铜线。
19.如权利要求15所述的方法，进一步包括将该衬底、该第一芯片、该粘结剂、该铜线、该膜以及该第二芯片包覆于封装胶体中。
20.如权利要求15所述的方法，其中，电性连接该第二芯片至该衬底包括利用第二芯片铜线电性连接该第二芯片至该衬底，以及
进一步包括：
将第二膜贴附至第三芯片；以及
将该第二膜贴附至该第二芯片及该第二芯片铜线，其中，该第二膜将该第二芯片铜线与该第三芯片电性绝缘。
CN2011800416026A 2010-06-29 2011-06-29 具有线上膜及铜线的薄型多晶片堆迭封装件的方法及系统 Pending CN103250246A (zh)

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