CN101414603B - 层叠半导体封装及其制造方法 - Google Patents

层叠半导体封装及其制造方法 Download PDF

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CN101414603B
CN101414603B CN2008100016127A CN200810001612A CN101414603B CN 101414603 B CN101414603 B CN 101414603B CN 2008100016127 A CN2008100016127 A CN 2008100016127A CN 200810001612 A CN200810001612 A CN 200810001612A CN 101414603 B CN101414603 B CN 101414603B
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semiconductor chip
range
adhesion parts
semiconductor
bonding pads
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CN101414603A (zh
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赵哲浩
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SK Hynix Inc
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Hynix Semiconductor Inc
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Abstract

本发明公开了一种层叠半导体封装及其制造方法。该层叠半导体封装包括具有第一接触焊垫和第二接触焊垫的基板。第一层叠封装组布置于基板上，且该第一层叠封装组包括层叠成阶梯形状以露出第一边缘接触焊垫的第一半导体芯片。第一导电引线用于电学耦合第一边缘结合焊垫和第一接触焊垫。粘着部件布置于最上面的第一半导体芯片上，第二层叠封装组布置于该粘着部件上。第二层叠封装组包括层叠成阶梯形状以露出第二边缘结合焊垫的第二半导体芯片。当第二层叠封装组布置于粘着部件上时，最下面的第二半导体芯片与最上面的第一半导体芯片对齐。第二导电引线电学用电学耦合第二边缘结合焊垫和第二接触焊垫。

Description

层叠半导体封装及其制造方法
技术领域
本发明涉及一种层叠半导体封装及其制造方法，且更具体而言涉及一种半导体芯片以阶梯方式形成来防止损坏的层叠半导体封装及其制造方法。
背景技术
在半导体制造技术的最近发展已经导致各式各样的半导体封装，其中半导体装置适于在短时间内处理更多的数据。
半导体封装通过下述的多个工艺来制造：半导体芯片制造工艺，制造在由高纯度硅制成的晶片上具有半导体装置的半导体芯片；管芯分类工艺，对半导体芯片进行电学测试；封装工艺，封装优质半导体芯片。
半导体封装技术的最近发展包括：芯片级(chip scale)封装，其中半导体封装的尺寸仅为半导体芯片尺寸的100％到105％；以及层叠半导体封装，其中多个半导体芯片互相层叠以改善半导体装置的数据容量和处理速度。
另外的技术发展已经导致：通过增加半导体芯片的集成密度以增加数据容量和处理速度的半导体产品，以及通过层叠多个半导体芯片以增加数据容量和处理速度的半导体产品。
现在转向具有多个层叠半导体芯片的层叠半导体封装，当使用导电引线来耦合该层叠半导体芯片的结合焊垫与基板的接触焊垫时，需要一种高水平的技术。
当层叠半导体芯片以改进数据容量和处理速度时，半导体芯片的厚度逐渐变薄。因此，近来的半导体芯片厚度仅为数十微米(μm)到数百微米(μm)。
但是，当层叠厚度为数十微米到数百微米的半导体芯片时，会发生若干问题。当层叠半导体芯片的结合焊垫被结合到基板的接触焊垫时，引线结合设备将利用引线结合毛细管。半导体芯片会因为由毛细管施加于该半导体芯片的过度碰撞而损坏。
发明内容
本发明中提供了一种能够层叠多个半导体芯片的层叠半导体芯片封装，其可防止在引线结合该半导体芯片的结合焊垫与基板的接触焊垫时对半导体芯片的损坏。
再者，本发明例如提供了一种用于制造该层叠半导体芯片封装的方法。
本发明的实施例提供一种层叠半导体封装，包括：基板，具有第一接触焊垫和第二接触焊垫；第一层叠封装组，布置于该基板上并将第一半导体芯片层叠成阶梯形状以露出形成于第一半导体芯片的上表面上的第一边缘结合焊垫；第一导电引线，电学耦合第一边缘结合焊垫和第一接触焊垫；粘着部件，布置于最上面的第一半导体芯片上；第二层叠封装组，布置于粘着部件上并将第二半导体芯片层叠成阶梯形状以露出位于第二半导体芯片的上表面上的第二边缘结合焊垫，且其中最下面的第二半导体芯片与最上面的第一半导体芯片对齐；以及第二导电引线，电学耦合第二边缘结合焊垫和第二接触焊垫。
该层叠半导体封装的第一半导体芯片沿着第一方向附着成阶梯形状，第二半导体芯片沿着与第一方向相反的第二方向附着成阶梯形状。
具有第一厚度的第一粘着部件夹置于该层叠半导体封装的第一半导体芯片之间。形成于最上面的第一半导体芯片上的粘着部件具有第二厚度，该第二厚度大于该第一厚度。
具有第一厚度的第二粘着部件夹置于该层叠半导体封装的第二半导体芯片之间。形成于最上面的第一半导体芯片上的粘着部件具有第二厚度，该第二厚度大于该第一厚度。
该层叠半导体封装的多个第一层叠半导体封装组和第二层叠半导体封装群可以交替地布置。
该层叠半导体封装的粘着部件覆盖第一导电引线的回弯(loop)部分，该第一导电引线电学耦合第一上半导体芯片的边缘结合焊垫和第一接触焊垫。
根据本发明一实施例，还提供了一种层叠半导体封装的制造方法，包括步骤：通过在包括第一接触焊垫和第二接触焊垫的基板上层叠第一半导体芯片来形成第一层叠封装组，其中该第一半导体芯片层叠为使得半导体芯片的第一边缘结合焊垫露出；使用第一导电引线电学耦合该第一边缘结合焊垫和该第一接触焊垫；在该第一层叠封装组的最上面的第一半导体芯片上形成粘着部件；通过在该粘着部件上形成包括层叠成阶梯形状的第二半导体芯片来形成第二层叠封装组；其中最下面的第二半导体芯片与最上面的第一半导体芯片对齐；以及通过第二导电引线电学耦合该第二边缘结合焊垫和该第二接触焊垫。
在层叠半导体封装的制造方法中，第一半导体芯片沿着第一方向附着成阶梯形状，第二半导体芯片沿着与第一方向相反的第二方向附着成阶梯形状。
在形成第一层叠封装组的步骤中，第一粘着部件夹置于第一半导体芯片之间。
在层叠半导体封装的制造方法中，第一粘着部件具有第一厚度，该粘着部件具有第二厚度，该第二厚度大于该第一厚度。
在层叠半导体封装的制造方法中，第二粘着部件夹置于第二半导体芯片之间。
在层叠半导体封装的制造方法中，第二粘着部件具有第一厚度，且该粘着部件第二厚度，该第二厚度大于该第一厚度。
在形成粘着部件的步骤中，粘着部件覆盖第一导电引线的回弯部分，该第一导电引线耦合到第一上半导体芯片的第一边缘结合焊垫。
附图说明
图1为依据本发明的实施例的层叠半导体封装的剖面视图。
图2为示出图1所示的层叠半导体封装的第一半导体芯片的平面视图。
图3为图1中′A′部分的局部放大图。
图4为示出图1所示的第二层叠封装组的第二半导体芯片的平面视图。
图5和6为示出依据本发明的实施例的层叠半导体封装的制造方法的剖面视图。
具体实施方式
图1为描述依据本发明一个实施例的层叠半导体封装的剖面视图，图2为显示图1所示层叠半导体封装的第一半导体芯片之一的平面视图。
参考图1和2，层叠半导体封装100包括基板10、第一层叠封装组20、第一导电引线30、粘着部件40、第二层叠封装组50、以及第二导电引线60。
基板10在从水平面观看时具有长方形的平行六面体的平板形状。例如，基板10可以是印刷电路板。
基板10包括第一接触焊垫12、第二接触焊垫14、以及球焊座(ball land)16。
第一接触焊垫12和第二接触焊垫14布置于基板10的上表面，球焊座16布置于基板10的下表面，该下表面与上表面相对。
第一接触焊垫12布置于基板10上表面一侧的边缘上，第二接触焊垫14布置于基板10上表面另一侧的边缘上，该另一侧与前面一侧相对。球焊座16电学耦合到第一接触焊垫12与/或第二接触焊垫14。
第一层叠封装组20附着到基板10的上表面。第一层叠封装组20包括第一半导体芯片21、22、23和24，以及用于将第一半导体芯片21、22、23和24相互附着的第一粘着部件25。
参考图2，第一半导体芯片21、22、23和24包括芯片区域(CR)和结合区域(BR)。结合区域(BR)布置为毗邻芯片区域(CR)。
边缘结合焊垫26布置在结合区域BR内。在图2中，边缘结合焊垫26布置为沿着与图2中Y轴平行的方向。
第一半导体芯片21、22、23和24的每个边缘结合焊垫26(其位于附着在基板10上的第一层叠封装组20内)配置为毗邻第一接触焊垫12。
第一粘着部件25布置于成对的相邻第一半导体芯片21、22、23和24之间。例如，第一粘着部件25可以是双面粘着胶带或为粘着剂。
第一层叠封装组20的第一半导体芯片21、22、23和24层叠使得沿着第一方向(FD)交叠成阶梯形状。结果，第一半导体芯片21、22、23和24的结合区域(BR)内的边缘结合焊垫26露出。
第一导电引线30将第一半导体芯片21、22、23和24的每个边缘结合焊垫26(置为彼此相邻)电学耦合到基板10的每个第一接触焊垫12。
图3为图1中“A”部分的局部放大图。
参考图1和3，粘着部件40直接布置在第一层叠封装组20的最上面的第一半导体芯片24上。在本实施例中，粘着部件40具有与第一半导体芯片24相同的形状和面积，粘着部件40覆盖第一导电引线30内的回弯部分32的一部分(其电学耦合到第一半导体芯片24的边缘结合焊垫26)。粘着部件40将第一导电引线30的回弯部分32与第二层叠封装组50(在下文描述)绝缘。
再参考图1，第二层叠封装组50附着在粘着部件40上。第二层叠封装组50包括多个半导体芯片51、52、53和54和第二粘着部件55。
图4为显示图1的第二层叠封装组的第二半导体芯片的平面视图。
参考图4，第二半导体芯片51、52、53和54包括芯片区域(CR)和结合区域(BR)。结合区域(BR)布置为毗邻芯片区域(CR)。边缘结合焊垫56布置于结合区域(BR)内。在图4中，边缘结合焊垫56布置为沿着与图4中Y轴平行的方向。
第二半导体芯片51、52、53和54的每个边缘结合焊垫56(位于附着到粘着部件40的第二层叠封装组50内)布置为毗邻基板10的第二接触焊垫14。在实施例中，第二半导体芯片51、52、53和54的形状和尺寸与第一半导体芯片21、22、23和24的形状和尺寸基本上相同。
第二层叠封装组50的第二半导体芯片51、52、53和54层叠使得沿着第二方向(SD)(与第一方向(FD)相反)相互交叠成阶梯形状，第二半导体芯片51、52、53和54的结合区域(BR)内的边缘结合焊垫56由此露出。
第二粘着部件55布置于相邻的第二半导体芯片51、52、53和54之间。例如，第二粘着部件55可以是粘着剂或双面粘着胶带。
在本实施例中，第二半导体芯片51为直接附着到粘着部件40的第二半导体芯片，该第二半导体芯片51与第一层叠封装组20的第一半导体芯片24对齐。换言之，在布置于粘着部件两侧上的第一半导体芯片24和第二半导体芯片51内，第一层叠封装组20的第一半导体芯片24的边缘和第二层叠封装组50的第二半导体芯片51的边缘对齐。
当第一层叠封装组20的第一半导体芯片24和第二层叠封装组50的第二半导体芯片51对齐时，粘着部件40和第一半导体芯片24支撑第二半导体芯片51。因此，当引线结合设备的毛细管用于引线结合第二半导体芯片51的边缘结合焊垫56和第二导电引线60时，通常因毛细管对第二半导体芯片51造成的损坏可被避免。
另一方面，如果第二层叠封装组50的第二半导体芯片51形成为从第一层叠封装组20的第一半导体芯片24突出，则当第二导电引线60结合到第二半导体芯片51的边缘结合焊垫56时，会造成因毛细管引起的对第二半导体芯片51的损坏。
第二导电引线60将第二接触焊垫14电学耦合到第二半导体芯片51、52、53和54的每个边缘结合焊垫56(其布置为毗邻第二接触焊垫14)。
在本实施例中，至少两个第一层叠封装组20和第二层叠封装组50在布置时是交替的，使得约20个第一和第二半导体芯片可层叠在该层叠半导体封装100中。
成型部件70形成于层叠在基板10上的第一层叠封装组20和第二层叠封装组50的上方，并形成于第一导电引线30与第二导电引线60的上方。可用于成型部件70的材料包括环氧树脂等。
图5和6为示出依据本发明一个实施例的层叠半导体封装的制造方法的剖面视图。
参考图5，第一层叠封装组20布置于基板10上从而制造层叠半导体封装。
基板10在从水平面观看时具有长方形的平行六面体的平板形状。例如，基板10可以是包括第一接触焊垫12、第二接触焊垫14、以及球焊座16的印刷电路板。
第一接触焊垫12布置于基板10上表面一侧的边缘处，第二接触焊垫14布置于基板10上表面对立侧的边缘处。球焊座16布置于基板10下表面(与上表面相对)。球焊座16电学耦合到第一接触焊垫12和/或第二接触焊垫14。
第一半导体芯片21、22、23和24制备以形成基板10上的第一层叠封装组20。
第一半导体芯片21、22、23和24的每个均具如上所述的芯片区域和结合区域。边缘结合焊垫26布置于每个第一半导体芯片21、22、23和24的结合区域中。
第一半导体芯片22附着到第一半导体芯片21的芯片区域上的第一半导体芯片21上表面。第一半导体芯片21和22利用第一粘着部件25被附着，且第一半导体芯片21的边缘结合焊垫26露出。
另一第一半导体芯片23随后附着到该芯片区域内的另一个第一半导体芯片22的上表面。同样，这些第一半导体芯片22和23利用粘着部件25被附着，且另一个第一半导体芯片22的边缘结合焊垫26露出。
之后，最后第一半导体芯片24附着到该另一第一半导体芯片23的芯片区域内的该另一第一半导体芯片23的上表面。第一半导体芯片23和24利用粘着部件25被附着，且另一第一半导体芯片23的边缘结合焊垫26和最后第一半导体芯片24露出。
在本实施例中，第一粘着部件25具有第一厚度，且第一粘着部件25例如可以是双面粘着胶带或为粘着剂。
如上所述，当第一半导体芯片21、22、23和24层叠时，第一半导体芯片21、22、23和24层叠为使得朝第一方向(FD)交叠成阶梯形状，如图5所示。
在第一层叠封装组20形成于基板10上后，基板10的第一接触焊垫12与第一半导体芯片21、22、23和24的每个边缘结合焊垫26通过第一导电引线30而电学耦合。
参考图6，在第一半导体芯片21、22、23和24的边缘结合焊垫26与基板10的第一接触焊垫12通过第一导电引线30而电学耦合之后，粘着部件40布置于第一层叠封装组20的最上面的第一半导体芯片24上。
例如，粘着部件40可以是一种涂布在第一半导体芯片24上表面上的流动粘着剂。备选地，粘着部件40可以是一种贴在第一半导体芯片24上表面上的粘着胶带。粘着部件40的附着面积与第一半导体芯片24的面积基本上相同。
在本实施例中，粘着部件40覆盖在第一导电引线30的回弯部分32(其电学耦合到第一半导体芯片24的边缘结合焊垫26)。在本实施例中，粘着部件40具有第二厚度，粘着部件40的第二厚度例如可以大于第一粘着部件25的第一厚度。
电学耦合到第一半导体芯片24的边缘结合焊垫26的第一导电引线30，通过粘着部件40与第二层叠封装组20的第二半导体芯片51电学绝缘(在下文描述)。
在粘着部件40布置于第一层叠封装组20的第一半导体芯片24上后，第二层叠封装组50布置于粘着部件40上。
第二层叠封装组50包括第二半导体芯片51、52、53和54。
每个第二半导体芯片51、52、53和54具有芯片区域和结合区域，且多个边缘结合焊垫56布置于第二半导体芯片51、52、53和54的每个结合区域中。
第二半导体芯片51、52、53和54中的第二半导体芯片51直接附着在粘着部件40上。
第二层叠封装组50的第二半导体芯片51与第一层叠封装组20的第一半导体芯片24严格对齐。
在本实施例中，由于第二半导体芯片51与第一半导体芯片24严格对齐，在引线结合工艺中对第二半导体芯片51的损坏得以避免。
另一第二半导体芯片52在第二半导体芯片51的芯片区域内附着到该第二半导体芯片51的上表面。第二半导体芯片51和52利用粘着部件55被附着，且第二半导体芯片51的边缘结合焊垫56露出。
再一第二半导体芯片53随后在另一半导体芯片52的芯片区域内附着到该另一第二半导体芯片52的上表面。第二半导体芯片52和53利用第二粘着部件55被附着，且该另一第二半导体芯片52的边缘结合焊垫56露出。
最后第二半导体芯片54随后在再一第二半导体芯片53的芯片区域内附着到该再一第二半导体芯片53的上表面。第二半导体芯片53和54利用第二粘着部件55被附着，且再一第二半导体芯片52的边缘结合焊垫56和最后第二半导体芯片54露出。
在本实施例中，第二粘着部件55具有第一厚度，且第二粘着部件55例如可以为双面粘着胶带或为粘着剂。
如上所述，当第二半导体芯片51、52、53和54层叠时，第二半导体芯片51、52、53和54层叠使得朝第二方向(SD)交叠为阶梯形状，如图6所示，其中该第二方向与第一方向(FD)相反。
在第二层叠封装组50形成于粘着部件40上后，基板10的第二接触焊垫14与第二半导体芯片51、52、53和54的边缘结合焊垫56通过第二导电引线60电学耦合。
此时，第二层叠封装组50的第二半导体芯片51由粘着部件40和第一层叠封装组20的第一半导体芯片24支撑，使得当第二导电引线60结合到第二半导体芯片51时，可避免对第二半导体芯片51的损坏。
根据前述方法，第一和第二层叠封装组20、50与第一和第二导电引线30、60可以交替多次。例如，本发明的层叠半导体封装100可以容易地层叠约20至30个半导体芯片。
再参考图1，在第一和第二层叠封装组20、50布置于基板10上后，第一和第二层叠封装组20、50与第一和第二导电引线30、60可通过成型部件70来成型，且层叠半导体封装100如此制造完成。
依据如上详细描述，通过将半导体芯片朝第一方向布置成阶梯形状来形成第一层叠封装组，随后通过将半导体芯片朝相反的第二方向布置成阶梯形状来形成第二层叠封装组，并利用粘着部件将第二层叠封装组附着到第一层叠封装组，第一层叠封装组的上半导体芯片与第二层叠封装组的下半导体芯片对齐，使得在引线结合工艺中对半导体芯片的损坏可得到避免。这使得可以容易地层叠多个半导体芯片。
虽然已经出于说明的目的描述了本发明的具体实施例，但是本领域技术人员将理解，可以进行各种改进、添加和替换而不背离权利要求所披露的本发明的范围和精神。
本申请主张2007年10月16日提出的韩国专利申请No.10-2007-0103880的优先权，其全文引用结合于此。

Claims (13)

1. 一种层叠半导体封装，包括：
基板，具有第一接触焊垫和第二接触焊垫；
第一层叠封装组，配置在所述基板上且包括多个第一半导体芯片，每个第一半导体芯片具有形成于所述第一半导体芯片的上表面的第一边缘上的多个第一边缘结合焊垫，其中所述第一半导体芯片层叠使得所述第一半导体芯片交叠成阶梯形状以露出所述第一边缘结合焊垫；
第一导电引线，电学耦合所述第一边缘结合焊垫和所述第一接触焊垫；
粘着部件，配置在最上面的第一半导体芯片上；
第二层叠封装组，配置在所述粘着部件上且包括第二半导体芯片，所述第二半导体芯片具有形成于所述第二半导体芯片的上表面的第二边缘上的多个第二边缘结合焊垫，其中所述第二半导体芯片层叠以交叠成阶梯形状以露出所述第二边缘结合焊垫，其中最下面的第二半导体芯片与最上面的第一半导体芯片对齐；以及
第二导电引线，电学耦合所述第二边缘结合焊垫和所述第二接触焊垫。
2. 如权利要求1所述的层叠半导体封装，其中所述第一半导体芯片的第一边缘与所述第二半导体芯片的第二边缘相对，且所述第一半导体芯片沿着第一方向附着成阶梯形状，所述第二半导体芯片沿着与所述第一方向相反的第二方向附着成阶梯形状。
3. 如权利要求1所述的层叠半导体封装，其中所述第一层叠封装组还包括第一粘着部件，所述第一粘着部件具有第一厚度且夹置于所述第一半导体芯片之间，以及所述第二层叠封装组还包括第二粘着部件，所述第二粘着部件具有所述第一厚度且夹置于所述第二半导体芯片之间。
4. 如权利要求3所述的层叠半导体封装，其中布置于最上面的第一半导体芯片上的所述粘着部件具有第二厚度，且所述粘着部件的所述第二厚度大于所述第二粘着部件的所述第一厚度。
5. 如权利要求1所述的层叠半导体封装，其中多个第一层叠半导体封装组和第二层叠半导体封装组交替布置。
6. 如权利要求1所述的层叠半导体封装，其中所述层叠半导体封装的粘着部件覆盖所述第一导电引线的回弯部分。
7. 一种层叠半导体封装的制造方法，包括步骤：
通过在包括第一接触焊垫和第二接触焊垫的基板上层叠第一半导体芯片使得所述第一半导体芯片交叠成阶梯形状来形成第一层叠封装组，其中所述第一半导体芯片包括形成于所述第一半导体芯片的上表面的第一边缘上的第一边缘结合焊垫，且其中所述第一边缘结合焊垫露出；
通过第一导电引线来电学耦合所述第一边缘结合焊垫和所述第一接触焊垫；
在最上面的第一半导体芯片上形成粘着部件；
通过在所述粘着部件上层叠第二半导体芯片使得所述第二半导体芯片交叠成阶梯形状来形成第二层叠封装组，其中所述第二半导体芯片包括形成于所述第二半导体芯片的上表面的第二边缘上的第二边缘结合焊垫，且其中所述第二边缘结合焊垫露出；
其中，当形成所述第二层叠封装组时，最下面的第二半导体芯片与最上面的第一半导体芯片对齐；以及
通过第二导电引线电学耦合所述第二边缘结合焊垫和所述第二接触焊垫。
8. 如权利要求7所述的制造方法，其中所述第一半导体芯片的第一边缘与所述第二半导体芯片的第二边缘相对，且所述第一半导体芯片沿着第一方向附着成阶梯形状，且所述第二半导体芯片沿着与所述第一方向相反的第二方向附着成阶梯形状。
9. 如权利要求7所述的制造方法，其中形成第一层叠封装组的步骤还包括：将第一粘着部件夹置于层叠的第一半导体芯片之间。
10. 如权利要求9所述的制造方法，其中所述第一粘着部件具有第一厚度，布置于最上面的第一半导体芯片上的所述粘着部件具有第二厚度，且所述第二厚度大于所述第一厚度。
11. 如权利要求7所述的制造方法，其中形成第二层叠封装组的步骤还包括：将第二粘着部件夹置于所述第二半导体芯片之间。
12. 如权利要求11所述的制造方法，其中所述第二粘着部件具有第一厚度，形成于最上面的第一半导体芯片上的所述粘着部件具有第二厚度，且所述第二厚度大于所述第一厚度。
13. 如权利要求7所述的制造方法，其中所述粘着部件形成为覆盖所述第一导电引线的回弯部分。
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