JP4498403B2 - 半導体装置と半導体記憶装置 - Google Patents
半導体装置と半導体記憶装置 Download PDFInfo
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- JP4498403B2 JP4498403B2 JP2007255633A JP2007255633A JP4498403B2 JP 4498403 B2 JP4498403 B2 JP 4498403B2 JP 2007255633 A JP2007255633 A JP 2007255633A JP 2007255633 A JP2007255633 A JP 2007255633A JP 4498403 B2 JP4498403 B2 JP 4498403B2
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- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H01L2924/1904—Component type
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Description
Claims (7)
- 素子搭載部と接続パッドとを備える配線基板と、
外形の一辺に沿って配列された電極パッドを有する複数の半導体素子を備え、前記複数の半導体素子は前記配線基板の前記素子搭載部上にパッド配列辺を同方向に向け、かつ前記電極パッドが露出するように階段状に積層されている第1の素子群と、
外形の一辺に沿って配列された電極パッドを有する複数の半導体素子を備え、前記複数の半導体素子は前記第1の素子群上にパッド配列辺を同方向に向け、かつ前記電極パッドが露出するように前記第1の素子群の階段方向とは逆方向に向けて階段状に積層されている第2の素子群と、
前記第1の素子群を構成する前記複数の半導体素子の前記電極パッドと前記配線基板の前記接続パッドとを電気的に接続する第1の金属ワイヤと、
前記第2の素子群を構成する前記複数の半導体素子の前記電極パッドと前記配線基板の前記接続パッドとを電気的に接続する第2の金属ワイヤと、
前記第1および第2の素子群を前記第1および第2の金属ワイヤと共に封止するように、前記配線基板の前記第1の主面上に形成された封止樹脂層とを具備し、
前記第2の素子群を構成する前記複数の半導体素子のうち、最下段の半導体素子の厚さは他の半導体素子の厚さより厚いことを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記第2の素子群の前記最下段の半導体素子は前記電極パッドの下方が中空部とされており、前記中空部には絶縁樹脂が充填されていることを特徴とする半導体装置。 - 素子搭載部と接続パッドとを備える第1の主面と、前記第1の主面とは反対側の第2の主面とを有する配線基板と、
前記配線基板の前記第2の主面に形成された外部接続端子と、
外形の一辺に沿って配列された電極パッドを有する複数の半導体メモリ素子を備え、前記複数の半導体メモリ素子は前記配線基板の前記素子搭載部上にパッド配列辺を同方向に向け、かつ前記電極パッドが露出するように階段状に積層されている第1のメモリ素子群と、
外形の一辺に沿って配列された電極パッドを有する複数の半導体メモリ素子を備え、前記複数の半導体メモリ素子は前記第1の素子群上にパッド配列辺を同方向に向け、かつ前記電極パッドが露出するように前記第1のメモリ素子群の階段方向とは逆方向に向けて階段状に積層されている第2のメモリ素子群と、
前記第2のメモリ素子群上に積層され、少なくとも外形の一辺に沿って配列された電極パッドを有するコントローラ素子と、
前記第1のメモリ素子群を構成する前記複数の半導体メモリ素子の前記電極パッドと前記配線基板の前記接続パッドとを電気的に接続する第1の金属ワイヤと、
前記第2のメモリ素子群を構成する前記複数の半導体メモリ素子の前記電極パッドと前記配線基板の前記接続パッドとを電気的に接続する第2の金属ワイヤと、
前記コントローラ素子の前記電極パッドと前記配線基板の前記接続パッドとを電気的に接続する第3の金属ワイヤと、
前記第1および第2のメモリ素子群と前記コントローラ素子を前記第1、第2および第3の金属ワイヤと共に封止するように、前記配線基板の前記第1の主面上に形成された封止樹脂層とを具備し、
前記第2のメモリ素子群を構成する前記複数の半導体メモリ素子のうち、最下段の半導体メモリ素子の厚さは他の半導体メモリ素子の厚さより厚いことを特徴とする半導体記憶装置。 - 請求項3記載の半導体記憶装置において、
前記最下段の半導体メモリ素子の厚さをT1、前記他の半導体メモリ素子の厚さをT2としたとき、前記第2のメモリ素子群はT1>T2、T1=50〜150μm、T2=10〜50μmの条件を満足することを特徴とする半導体記憶装置。 - 請求項3または請求項4記載の半導体記憶装置において、
前記第1のメモリ素子群を構成する前記複数の半導体メモリ素子のうち、最下段の半導体メモリ素子の厚さをT3、他の半導体メモリ素子の厚さをT4としたとき、前記第1のメモリ素子群はT3>T4、T3=50〜150μm、T2=10〜50μmの条件を満足することを特徴とする半導体記憶装置。 - 請求項3ないし請求項5のいずれか1項記載の半導体記憶装置において、
前記第1のメモリ素子群は4個以上の前記半導体メモリ素子を有し、前記第2のメモリ素子群は4個以上の前記半導体メモリ素子を有することを特徴とする半導体記憶装置。 - 請求項3ないし請求項6のいずれか1記載の半導体記憶装置において、
前記第2の素子群の前記最下段の半導体メモリ素子は前記電極パッドの下方が中空部とされており、前記中空部には絶縁樹脂が充填されていることを特徴とする半導体記憶装置。
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