JP2009182104A - 半導体パッケージ - Google Patents
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- JP2009182104A JP2009182104A JP2008019005A JP2008019005A JP2009182104A JP 2009182104 A JP2009182104 A JP 2009182104A JP 2008019005 A JP2008019005 A JP 2008019005A JP 2008019005 A JP2008019005 A JP 2008019005A JP 2009182104 A JP2009182104 A JP 2009182104A
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Abstract
【解決手段】半導体パッケージ1は、外部接続用端子3を備える第1の主面2aと、素子搭載部と内部接続用端子とを備える第2の主面2bとを有する配線基板2を具備する。配線基板2の素子搭載部上には電極パッドを有する半導体素子8が搭載される。半導体素子8の電極パッドと配線基板2の内部接続用端子とは接続部材を介して電気的に接続される。半導体素子は接続部材と共に封止樹脂層で一体的に封止される。外部接続用端子3A、3Bは配線基板2の外形辺のうちの対向する二辺13a、13bに沿って配列されており、かつ端子配列辺13a、13bに向かう方向に伸びた長方形形状を有する。
【選択図】図2
Description
Claims (5)
- 外部接続用端子を備える第1の主面と、素子搭載部と内部接続用端子とを備え、前記第1の主面とは反対側の第2の主面とを有する配線基板と、
前記配線基板の前記素子搭載部上に搭載され、少なくとも外形の一辺に沿って配列された電極パッドを有する半導体素子と、
前記半導体素子の前記電極パッドと前記配線基板の前記内部接続用端子とを電気的に接続する接続部材と、
前記半導体素子を前記接続部材と共に封止するように、前記配線基板の前記第2の主面上に設けられた封止樹脂層とを具備し、
前記外部接続用端子は前記配線基板の外形辺のうちの対向する二辺に沿って配列されており、かつ前記外部接続用端子が配列された辺に向かう方向に伸びた長方形形状を有することを特徴とする半導体パッケージ。 - 外部接続用端子を備える第1の主面と、素子搭載部と内部接続用端子とを備え、前記第1の主面とは反対側の第2の主面とを有する配線基板と、
前記配線基板の前記素子搭載部上に積層されて搭載され、少なくとも外形の一辺に沿って配列された電極パッドを有する複数の半導体素子を備える半導体素子群と、
前記複数の半導体素子の前記電極パッドと前記配線基板の前記内部接続用端子とを電気的に接続する接続部材と、
前記半導体素子群を前記接続部材と共に封止するように、前記配線基板の前記第2の主面上に形成された封止樹脂層とを具備し、
前記外部接続用端子は前記配線基板の外形辺のうちの対向する二辺に沿って配列されており、かつ前記外部接続用端子が配列された辺に向かう方向に伸びた長方形形状を有することを特徴とする半導体パッケージ。 - 請求項1または請求項2記載の半導体パッケージにおいて、
さらに、前記外部接続用端子上に配置された突起状端子を具備することを特徴とする半導体パッケージ。 - 請求項3記載の半導体パッケージにおいて、
前記長方形形状を有する外部接続用端子の形成ピッチをP、短辺の長さをW、長辺の長さをLとしたとき、前記外部接続用端子は0.4P≦W≦0.6P、W<L≦2Wの条件を満足する長方形形状を有することを特徴とする半導体パッケージ。 - 請求項1ないし請求項4のいずれか1項記載の半導体パッケージにおいて、
前記配線基板の前記第1の主面には、前記外部接続用端子の形成領域を除く内側領域にテスト用端子が設けられていることを特徴とする半導体パッケージ。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008019005A JP2009182104A (ja) | 2008-01-30 | 2008-01-30 | 半導体パッケージ |
US12/361,083 US7968997B2 (en) | 2008-01-30 | 2009-01-28 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008019005A JP2009182104A (ja) | 2008-01-30 | 2008-01-30 | 半導体パッケージ |
Publications (2)
Publication Number | Publication Date |
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JP2009182104A true JP2009182104A (ja) | 2009-08-13 |
JP2009182104A5 JP2009182104A5 (ja) | 2011-02-03 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2008019005A Pending JP2009182104A (ja) | 2008-01-30 | 2008-01-30 | 半導体パッケージ |
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US (1) | US7968997B2 (ja) |
JP (1) | JP2009182104A (ja) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP2503594A1 (en) * | 2011-03-21 | 2012-09-26 | Dialog Semiconductor GmbH | Signal routing optimized IC package ball/pad layout |
JP6076068B2 (ja) * | 2012-12-17 | 2017-02-08 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置 |
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US20090189158A1 (en) | 2009-07-30 |
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