JP2002043503A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JP2002043503A
JP2002043503A JP2000224437A JP2000224437A JP2002043503A JP 2002043503 A JP2002043503 A JP 2002043503A JP 2000224437 A JP2000224437 A JP 2000224437A JP 2000224437 A JP2000224437 A JP 2000224437A JP 2002043503 A JP2002043503 A JP 2002043503A
Authority
JP
Japan
Prior art keywords
semiconductor chip
semiconductor device
electrode pad
relay terminal
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
JP2000224437A
Other languages
English (en)
Inventor
Naoto Kimura
直人 木村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Kyushu Ltd
Original Assignee
NEC Kyushu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Kyushu Ltd filed Critical NEC Kyushu Ltd
Priority to JP2000224437A priority Critical patent/JP2002043503A/ja
Priority to US09/909,051 priority patent/US6476500B2/en
Priority to TW090118113A priority patent/TW503556B/zh
Priority to KR10-2001-0044445A priority patent/KR100390966B1/ko
Publication of JP2002043503A publication Critical patent/JP2002043503A/ja
Abandoned legal-status Critical Current

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Classifications

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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01—ELECTRIC ELEMENTS
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Abstract

(57)【要約】 【課題】スタック構造でＣＳＰ型の半導体装置におい
て、より小型化が図れ安価にする。 【解決手段】第２の半導体チップ２に搭載すべく第１の
半導体チップ１を中心よりいずれかの方向に片寄せて搭
載することによって、寄せられた側の第２の半導体チッ
プ１の片側に中継端子１０が不要となり、中継端子１０
が占める面積を減じた第２の半導体チップ２で済み、小
型化が図れる。

Description

【発明の詳細な説明】
【０００１】
【発明の属する技術分野】本発明は半導体装置に関し、
特に複数の半導体チップを積み重ねたスタック型の半導
体装置にに関する。
【０００２】
【従来の技術】近年、携帯電話などの実装用ケ−スが小
型化し、半導体装置も小型化が要求されるようになっ
た。この小さなケ−スに収納できるように、半導体チッ
プのサイズとほぼ同程度の大きさのパッケ−ジに開発さ
れる至った。また、この種の半導体装置は、ＣＳＰ（Ｃ
ｈｉｐ Ｓｉｚｅ Ｐａｃｋａｇｅ）と呼ばれていた。
さらに、記憶容量や多数の電子回路機能をもたせるため
に複数の半導体チップを積み重ねたスタックドパッケ−
ジ構造の半導体装置が提案されている。
【０００３】図３は従来の半導体装置の一例を示す図で
ある。このような小型で多機能である半導体装置は、例
えば、図３に示すように、周辺部の表面に複数個の電極
パッド２４が並べて配置された第１の半導体チップ２１
と両側の周辺部に複数個を並べ配置された電極パッド２
７および中継端子２５をもつ第２の半導体チップ２２と
を接着剤で固定保持した構造である。
【０００４】また、第１の半導体チップ２１を搭載した
第２の半導体チップ２２は絶縁性配線基板２３に接着剤
を介して搭載されている。そして、導電パッド２６と電
極パッド２４と直接接続する場合、金属細線であるワイ
ヤが長くなる。ワイヤが長くなると、半導体チップや他
のワイヤに接触したりする問題を起こす。
【０００５】そこで、第２の半導体チップ２２上に通常
の電極パッド２７の他に中継端子２５を設け、導電パッ
ド２６からの電極パッド２４への接続を、導電パッド２
６からのワイヤ２９を中継端子２５に接続し、中継端子
２５からのワイヤ２８を電極パッド２４に接続してい
る。
【０００６】なお、実装用ケ−ス内の配線基板の導電パ
ッドと接続する実装用外部端子３１は、絶縁性配線基板
２３の配線層３０と接続し絶縁性配線基板２３の裏面よ
り突出している。また、外部からの水分の浸入や機械的
外力の保護のために、ワイヤ２８，２９および第１の半
導体チップ２１と第２の半導体チップ２２を含む金型の
空間部に樹脂を充填し樹脂体３２を成形している。この
ように、半導体装置の大きさが、第２の半導体チップ２
２より稍大きい絶縁性配線基板２３程度内に収まるよう
にし、半導体装置を小型にしていることを特徴としてい
る。
【０００７】
【発明が解決しようとする課題】しかしながら、上述し
た半導体装置においては、第２の半導体チップ２２の両
側に細長い中継端子２５があるため、第２の半導体チッ
プ２２が小さくならない。言い換えれば、第２の半導体
チップ２２が小さくならないとすると、当然、絶縁性配
線基板２３も小さくすことができず、半導体装置をさら
に小型化することが困難である。
【０００８】例えば、第２の半導体チップ２２が記憶素
子であると仮定すると、中継端子２５を設けるために、
必要以上の記憶容量をもつ一ランク上の大きさの半導体
チップを使うことになり、半導体装置自体が高価になる
という問題もある。
【０００９】従って、本発明の目的は、より小型化が図
れ安価な半導体装置を提供することにある。
【００１０】
【課題を解決するための手段】本発明の特徴は、一主面
の両辺に一方向に並べ配置される複数の第１の電極パッ
ドを有する第１の半導体チップと、この第１の半導体チ
ップを中心よりいずれかの方向に片寄せられて搭載する
とともに両辺に並べ配置された複数の第２の電極パッド
とを有する第２の半導体チップと、前記第１の半導体チ
ップが片寄せられて配置される側と反対側の前記第２の
半導体チップに配置される複数の中継用端子と、前記第
２の半導体チップを搭載するとともに前記第１の電極パ
ッドと前記第２の電極パッドに対応して配置される複数
の導電パッドを有する配線基板と、前記第１の半導体チ
ップの第１の電極パッドと前記配線基板の導電パッドと
を接続する第１の金属細線と、前記第２の半導体チップ
の第２の電極パッドと前記配線基板の導電パッドと接続
する第２の金属細線と、前記配線基板の裏面から突出す
るとともに前記導電パッドに接続される配線と接続され
る実装用外部端子とを有する半導体装置である。
【００１１】また、前記第１の半導体チップの第１の電
極パッドと前記配線基板の導電パッドとを前記中継端子
を介して接続する第３の金属細線を有することが望まし
い。さらに、前記中継端子は前記第２の電極パッドと並
べて形成されていることが望ましい。好ましくは、前記
中継端子は、短冊状であることである。
【００１２】一方、前記第１の金属細線および前記第２
の金属細線ならびに前記第３の金属細線は、金線である
ことが望ましい。また、前記実装用外部端子は、球形状
に成形されれた半田材であることことが望ましい。
【００１３】
【発明の実施の形態】次に、本発明について図面を参照
して説明する。
【００１４】図１（ａ）および（ｂ）は本発明の一実施
の形態における半導体装置を示す平面図および断面図で
ある。この半導体装置は、図１に示すように、一主面の
両側の辺に一方向に並べ配置される複数の電極パッド４
を有する第１の半導体チップ１と、この第１の半導体チ
ップ１を中心よりいずれかの方向に片寄せられて搭載す
るとともに両側の辺に並べ配置された複数の電極パッド
５とを有する第２の半導体チップ２と、第１の半導体チ
ップ１が片寄せられて配置される側と反対側の第２の半
導体チップ２上に配置される複数の中継用端子１０と、
第２の半導体チップ２を搭載するとともに電極パッド４
と電極パッド５に対応して配置される複数の導電パッド
１２を有する絶縁性配線基板３と、第１の半導体チップ
１の電極パッド４と絶縁性配線基板３の導電パッド１２
とを接続する金属細線であるワイヤ８と、第２の半導体
チップ２の電極パッド５と絶縁性配線基板３の導電パッ
ド１２と接続するワイヤ７と、絶縁性配線基板３の裏面
から突出するとともに導電パッド１２に接続される配線
層１３と接続される実装用外部端子１４とを有してい
る。
【００１５】また、第１の半導体チップ１が接着剤を介
して寄せられて搭載される側と反対側の第２の半導体チ
ップ２の上には、電極パッド５との間に中継端子１０が
形成されている。そして、電極パッド４と導電パッド１
２との接続は、導電パッド１２からのワイヤを中継端子
１０に接続し、中継端子１０からのワイヤ６により電極
パッド４に接続することが望ましい。
【００１６】一方、第１の半導体チップ１が寄せられて
搭載された側におけるワイヤリングは、導電パッド１２
と電極パッド４および電極パッドが近いので、ワイヤ９
とワイヤ８との接触や半導体チップへの接触など起こら
ずにできる。そこで、導電パッド１２と電極パッド４と
の接続はワイヤ８で行い、導電パッド１２と電極パッド
５との接続をワイヤ９で行った。すなわち、中継端子を
必要とせず直接接続することができる。このことは、後
述するが第２の半導体チップ２を小さくできる。
【００１７】なお、この中継端子１０は、第２の半導体
チップ２の電極パッド５と同時に形成すので、細長い矩
形である短冊状の形状が望ましい。このことは、電極パ
ッド５および中継端子１０を形成するときの露光装置の
レチクルパタ−ン形状を単純にするためである。また、
この中継端子１０は一端は電極パッド５の端部に揃え、
他端は第１の半導体チップ１に近づけて配置することが
望ましい。さらに、望ましくは、この中継端子１０の他
端と電極パッド４との距離は、導電パッド１２と電極パ
ッド５との距離に等しくなるように中継端子１０の他端
を伸ばすことが望ましい。
【００１８】一方、絶縁性配線基板３は、セラミクやガ
ラスエポキシの基板に印刷配線したもので良く、ここで
は、安価なガラスエポキシ基板を使用した。そして、第
２の半導体チップ２との接着には、エポキシ樹脂接着剤
を使用した。また、ワイヤ６，７，８，９である金属細
線は、信号電位が低いことから低抵抗である金線を用い
ることが望ましい。
【００１９】また、ワイヤ６，７，８，９を包み込む樹
脂体１５は、底部は絶縁性配線基板３の外形と同一にな
るように成形し、上部に行くほどやや小さくなるように
勾配をもたせ角部はア−ルにすることが望ましい。そし
て、実装用外部端子１４は、背の低いバンプでなく、予
め球状に成形した背の高い半田ボ−ルを準備し、半田ボ
−ル搭載治具を用いて絶縁性配線基板３に取り付けるこ
とが望ましい。
【００２０】図２（ａ）および（ｂ）は従来の第２の半
導体チップと図１の第２の半導体チップを示す平面図で
ある。前述したように、第１の半導体チップ１を第２の
半導体チップ２のいずれかの側に寄せて搭載することに
よって、図２（ａ）に示すように、第２の半導体チップ
の中継端子が必要であったものが、図２（ｂ）に示すよ
うに、不要となり、短冊状の中継端子１０の占める不要
な領域の面積だけ第２の半導体チップを小さくできる。
【００２１】
【発明の効果】以上説明したように本発明は、第２の半
導体チップに搭載すべく第１の半導体チップを中心より
いずれかの方向に片寄せて搭載することによって、寄せ
られた側の第２の半導体チップの片側に中継端子が不要
となり、中継端子が占める面積を減じた第２の半導体チ
ップで済み、小型化が図れるという効果がある。
【００２２】また、第２の半導体チップに不必要に記憶
容量の大きな半導体チップを用いることなく、より安価
で容量の適した半導体チップを使用することによって、
より安価な半導体装置が得られるという効果もある。
【図面の簡単な説明】
【図１】本発明の一実施の形態における半導体装置を示
す平面図および断面図である。
【図２】従来の第２の半導体チップと図１の第２の半導
体チップを示す平面図である。
【図３】従来の半導体装置の一例を示す図である。
【符号の説明】
１ 第１の半導体チップ ２ 第２の半導体チップ ３ 絶縁性配線基板 ４，５ 電極パッド ６，７，８，９ ワイヤ １０ 中継端子 １２ 導電パッド １３ 配線層 １４ 実装用外部端子 １５ 樹脂体

Claims (6)

    【特許請求の範囲】
  1. 【請求項１】 一主面の両辺に一方向に並べ配置される
    複数の第１の電極パッドを有する第１の半導体チップ
    と、この第１の半導体チップを中心よりいずれかの方向
    に片寄せられて搭載するとともに両辺に並べ配置された
    複数の第２の電極パッドとを有する第２の半導体チップ
    と、前記第１の半導体チップが片寄せられて配置される
    側と反対側の前記第２の半導体チップ面に配置される複
    数の中継用端子と、前記第２の半導体チップを搭載する
    とともに前記第１の電極パッドと前記第２の電極パッド
    に対応して配置される複数の導電パッドを有する配線基
    板と、前記第１の半導体チップの第１の電極パッドと前
    記配線基板の導電パッドとを接続する第１の金属細線
    と、前記第２の半導体チップの第２の電極パッドと前記
    配線基板の導電パッドと接続する第２の金属細線と、前
    記配線基板の裏面から突出するとともに前記導電パッド
    に接続される配線と接続される実装用外部端子とを有す
    ることを特徴とする半導体装置。
  2. 【請求項２】 前記第１の半導体チップの第１の電極パ
    ッドと前記配線基板の導電パッドとを前記中継端子を介
    して接続する第３の金属細線を有することを特徴とする
    請求項１記載の半導体装置。
  3. 【請求項３】 前記中継端子は前記第２の電極パッドと
    並べて形成されていることを特徴とする請求項１または
    請求項２記載の半導体装置。
  4. 【請求項４】 前記中継端子は、短冊状であることを特
    徴とする請求項３記載の半導体装置。
  5. 【請求項５】 前記第１の金属細線および前記第２の金
    属細線ならびに前記第３の金属細線は、金線であること
    を特徴とする請求項１、請求項２、請求項３または請求
    項４記載の半導体装置。
  6. 【請求項６】 前記実装用外部端子は、球形状に成形さ
    れれた半田材であることを特徴とする請求項１、請求項
    ２、請求項３、請求項４または請求項５記載の半導体装
    置。
JP2000224437A 2000-07-25 2000-07-25 半導体装置 Abandoned JP2002043503A (ja)

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US09/909,051 US6476500B2 (en) 2000-07-25 2001-07-19 Semiconductor device
TW090118113A TW503556B (en) 2000-07-25 2001-07-24 Semiconductor device
KR10-2001-0044445A KR100390966B1 (ko) 2000-07-25 2001-07-24 반도체 장치

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US6476500B2 (en) 2002-11-05
KR100390966B1 (ko) 2003-07-16
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US20020011654A1 (en) 2002-01-31
TW503556B (en) 2002-09-21

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