JP5150243B2 - 半導体記憶装置 - Google Patents
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Description
Claims (6)
- 外部接続端子を備える第1の主面と、素子搭載部と接続パッドとを備え、前記第1の主面とは反対側の第2の主面とを有する配線基板と、
外形の一辺に沿って配列された電極パッドを有する複数の第1のメモリ素子を備え、前記複数の第1のメモリ素子は前記配線基板の前記素子搭載部上に、パッド形成面を同方向に向けると共に、パッド配列辺を同方向に向け、かつ前記電極パッドが露出するように順に階段状に積層されている第1のメモリ素子群と、
外形の一辺に沿って配列された電極パッドを有する複数の第2のメモリ素子を備え、前記複数の第2のメモリ素子は前記第1の素子群上に、パッド形成面を前記第1のメモリ素子群と同方向に向けると共に、パッド配列辺を前記第1のメモリ素子群と逆方向に向け、かつ前記電極パッドが露出するように前記第1のメモリ素子群の階段方向とは逆方向に向けて順に階段状に積層されている第2のメモリ素子群と、
前記第2のメモリ素子群上に積層され、少なくとも外形の一辺に沿って配列された電極パッドを有するコントローラ素子と、
前記第1のメモリ素子群を構成する前記複数の第1のメモリ素子の前記電極パッドと前記配線基板の前記接続パッドとを電気的に接続する第1の金属ワイヤと、
前記第2のメモリ素子群を構成する前記複数の第2のメモリ素子の前記電極パッドと前記配線基板の前記接続パッドとを電気的に接続する第2の金属ワイヤと、
前記コントローラ素子の前記電極パッドと前記配線基板の前記接続パッドとを電気的に接続する第3の金属ワイヤと、
前記第1および第2のメモリ素子群と前記コントローラ素子を前記第1、第2および第3の金属ワイヤと共に封止するように、前記配線基板の前記第2の主面上に形成された封止樹脂層とを具備し、
前記第1のメモリ素子と前記第2のメモリ素子とは同一の外形形状を有し、
前記第2のメモリ素子群における最下段の第2のメモリ素子は、前記第1のメモリ素子群における最上段の第1のメモリ素子と外形辺が重なるように配置され、かつ前記最上段の第1のメモリ素子の直上にスペーサ層として機能する絶縁性接着層を介して積層されており、かつ前記最上段の第1のメモリ素子に接続された前記第1の金属ワイヤの素子側端部は、前記絶縁性接着層内に埋め込まれており、
前記第1のメモリ素子群における最下段の第1のメモリ素子の厚さをT1、他の第1のメモリ素子の厚さをT2、前記第2のメモリ素子群における前記最下段の第2のメモリ素子の厚さをT3、他の第2のメモリ素子の厚さをT4としたとき、前記第1のメモリ素子群はT1>T2を満足し、かつ前記第2のメモリ素子群はT3>T4を満足することを特徴とする半導体記憶装置。 - 請求項1記載の半導体記憶装置において、
前記最下段の第1のメモリ素子の厚さT1は40〜50μmの範囲、前記他の第1のメモリ素子の厚さT2は10〜40μmの範囲、前記最下段の第2のメモリ素子の厚さT3は25〜40μmの範囲、前記他の第2のメモリ素子の厚さT4は10〜25μmの範囲であることを特徴とする半導体記憶装置。 - 請求項1または請求項2記載の半導体記憶装置において、
前記第1のメモリ素子群は、第1の素子集団と、前記第1の素子集団に対して前記電極パッドの配列方向にずらした状態で配置された第2の素子集団とに分けられており、
前記第2のメモリ素子群は、第3の素子集団と、前記第3の素子集団に対して前記電極パッドの配列方向にずらした状態で配置された第4の素子集団とに分けられており、
前記第1の金属ワイヤは、前記第1および第2の素子集団を構成する複数の前記第1のメモリ素子の前記電極パッドと前記配線基板の前記接続パッドとを順に接続する第1のデータ信号用金属ワイヤと、前記第1の素子集団を構成する複数の前記第1のメモリ素子の前記電極パッドと前記配線基板の前記接続パッドとを順に接続する第1の制御信号用金属ワイヤと、前記第2の素子集団を構成する複数の前記第1のメモリ素子の前記電極パッドと前記配線基板の前記接続パッドとを順に接続する第2の制御信号用金属ワイヤとを備え、前記第2の制御信号用金属ワイヤは前記第1の素子集団を構成する前記複数の第1のメモリ素子の前記電極パッド間にワイヤリングされており、
前記第2の金属ワイヤは、前記第3および第4の素子集団を構成する複数の前記第2のメモリ素子の前記電極パッドと前記配線基板の前記接続パッドとを順に接続する第2のデータ信号用金属ワイヤと、前記第3の素子集団を構成する複数の前記第2のメモリ素子の前記電極パッドと前記配線基板の前記接続パッドとを順に接続する第3の制御信号用金属ワイヤと、前記第4の素子集団を構成する複数の前記第2のメモリ素子の前記電極パッドと前記配線基板の前記接続パッドとを順に接続する第4の制御信号用金属ワイヤとを備え、前記第4の制御信号用金属ワイヤは前記第3の素子集団を構成する前記複数の第2のメモリ素子の前記電極パッド間にワイヤリングされていることを特徴とする半導体記憶装置。 - 請求項1ないし請求項3のいずれか1項記載の半導体記憶装置において、
さらに、前記第2のメモリ素子群上に前記コントローラ素子と隣接して配置され、第1の外形辺に沿って配列された第1の中継パッド、前記第1の外形辺と直交する第2の外形辺に沿って配列された第2の中継パッド、および前記第1の中継パッドと前記第2の中継パッドとを電気的に繋ぐ配線層を有する中継素子を具備し、
前記コントローラ素子の前記電極パッドは、第1の外形辺に沿って配列された第1の電極パッドと、第2の外形辺に沿って配列された第2の電極パッドと、第3の外形辺に沿って配列された第3の電極パッドとを有し、
前記コントローラ素子の前記第1および第2の電極パッドは、前記配線基板の前記接続パッドと前記第3の金属ワイヤを介して電気的に接続されており、
前記コントローラ素子の前記第3の電極パッドは、前記中継素子の前記第1の中継パッドと第1の中継用金属ワイヤを介して電気的に接続されており、
前記中継素子の前記第2の中継パッドは、前記配線基板の前記接続パッドと第2の中継用金属ワイヤを介して電気的に接続されていることを特徴とする半導体記憶装置。 - 請求項4記載の半導体記憶装置において、
前記配線基板は略矩形状の外形を有し、前記外形は直線形状の第1の長辺、切り欠き部を有する第2の長辺、第1の短辺および第2の短辺を有し、
前記配線基板の前記第2の主面は、前記第1の短辺に沿って設けられた第1のパッド領域と、前記第2の短辺に沿って設けられた第2のパッド領域と、前記第1の長辺に沿って設けられた第3のパッド領域とを有し、
前記第1のメモリ素子群を構成する前記複数の第1のメモリ素子の前記電極パッドは、前記第1のパッド領域に配置された前記接続パッドと前記第1の金属ワイヤを介して電気的に接続されており、
前記第2のメモリ素子群を構成する前記複数の第2のメモリ素子の前記電極パッドは、前記第2のパッド領域に配置された前記接続パッドと前記第2の金属ワイヤを介して電気的に接続されており、
前記コントローラ素子の前記第1の電極パッドは、前記第3のパッド領域に配置された前記接続パッドと前記第3の金属ワイヤを介して電気的に接続されており、
前記コントローラ素子の前記第2の電極パッドは、前記第1のパッド領域に配置された前記接続パッドと前記第3の金属ワイヤを介して電気的に接続されており、
前記中継素子の前記第2の中継パッドは、前記第1のパッド領域に配置された前記接続パッドと前記第2の中継用金属ワイヤを介して電気的に接続されていることを特徴とする半導体記憶装置。 - 請求項1ないし請求項5のいずれか1項記載の半導体記憶装置において、
前記半導体記憶装置は半導体メモリカードであることを特徴とする半導体記憶装置。
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