CN103681571B - 半导体存储卡及其制造方法 - Google Patents

半导体存储卡及其制造方法 Download PDF

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Publication number
CN103681571B
CN103681571B CN201310056269.7A CN201310056269A CN103681571B CN 103681571 B CN103681571 B CN 103681571B CN 201310056269 A CN201310056269 A CN 201310056269A CN 103681571 B CN103681571 B CN 103681571B
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chip
external connection
connection terminals
lead
resin layer
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CN103681571A (zh
Inventor
土井英
土井一英
本间庄
本间庄一
渡边胜好
西山拓
生田武史
奥村尚久
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Japanese Businessman Panjaya Co ltd
Kioxia Corp
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Toshiba Corp
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Abstract

本发明提供在使用引线框谋求低成本化的基础上使外部连接端子的露出性提高的半导体存储卡及其制造方法。实施方式的半导体存储卡（1）具备：引线框（2），其具备外部连接端子（3）、引线部（4）、芯片部件搭载部（5）和半导体芯片搭载部（6）；搭载于芯片部件搭载部（5）的芯片部件（7）；以及搭载于半导体芯片搭载部（6）的控制器芯片（8）及存储器芯片（9）。引线框（2）被树脂封装。封装树脂层（10）具有使外部连接端子（3）的表面及侧面的一部分露出并以包围外部连接端子（3）的周围的方式设置于第1面（10a）的凹部（15）。

Description

半导体存储卡及其制造方法
相关申请
本申请享有以日本专利申请2012—200159号（申请日：2012年9月12日）为基础申请的优先权。本申请通过参照该基础申请而包含基础申请的全部内容。
技术领域
本发明的实施方式涉及半导体存储卡及其制造方法。
背景技术
在内置NAND型闪速存储器等存储卡（半导体存储卡）中，小型化和高容量化得到发展。此外，在实现存储卡的高容量化的基础上，存储器芯片本身的高密度化和基于此的高容量化得到发展。存储卡一般通过在具有外部连接端子的布线基板上搭载存储器芯片和／或控制器芯片等半导体芯片并且在布线基板上形成封装树脂层而对半导体芯片进行封装来构成。进而，为了谋求存储卡的低成本化等，将存储器芯片和／或控制器芯片等半导体芯片和电容器和／或熔丝等芯片部件搭载于具有外部连接端子的引线框上的方案也得到探讨。
在使用了引线框的存储卡中，在将半导体芯片和／或芯片部件搭载于引线框上之后，形成与半导体芯片和／或芯片部件一起将引线框封装的封装树脂层。在形成封装树脂层时，需要使外部连接端子的表面露出。封装树脂层例如使用使外部连接端子的表面露出的成型模并应用传递成型等而形成。但是，因为存储卡的外部连接端子配置于封装树脂层的一表面内，所以例如难以在封装树脂层的形成时完全地抑制树脂毛边的产生。因此，外部连接端子的表面的一部分会由树脂覆盖，由外部连接端子实现的与外部设备的连接性容易降低。
发明内容
本发明要解决的课题在于提供在使用引线框谋求低成本化的基础上使外部连接端子的露出性提高的半导体存储卡及其制造方法。
实施方式的半导体存储卡具备：引线框，其具备多个外部连接端子、具有至少一部分连接于所述外部连接端子的多条引线的引线部、设置于所述引线部的芯片部件搭载部、和半导体芯片搭载部；芯片部件，其搭载于所述芯片部件搭载部，且与所述引线电连接；搭载于所述半导体芯片搭载部且与所述引线电连接的控制器芯片及与所述控制器芯片电连接的存储器芯片；封装树脂层，其将所述引线框与所述芯片部件、所述控制器芯片及所述存储器芯片一起进行封装。所述封装树脂层具有作为所述外部连接端子的露出面的第1面、和凹部，所述凹部使所述外部连接端子的表面及侧面的一部分露出并以包围所述外部连接端子的周围的方式设置于所述第1面。
附图说明
图1是表示第1实施方式涉及的半导体存储卡的上表面透视图。
图2是图1所示的半导体存储卡的仰视图。
图3是图1所示的半导体存储卡的剖视图。
图4是表示图1所示的半导体存储卡的下表面的其他例子的图。
图5是放大地表示图1所示的半导体存储卡中的外部连接端子及设置于树脂密封层的凹部的剖视图。
图6是图5所示的外部连接端子及凹部的俯视图。
图7是表示图5所示的外部连接端子及凹部的其他例子的剖视图。
图8是表示图5所示的凹部的形成工序的剖视图。
图9是表示图1所示的半导体存储卡中的存储器芯片的再布线层的第1构成例的剖视图。
图10是表示图1所示的半导体存储卡中的存储器芯片的再布线层的第2构成例的剖视图。
图11是放大地表示第2实施方式涉及的半导体存储卡的外部连接端子的剖视图。
图12是表示第2实施方式的半导体存储卡的第1构成例及其制造工序的剖视图。
图13是表示图12所示的半导体存储卡的最终构成的剖视图。
图14是表示第2实施方式的半导体存储卡的第2构成例及其制造工序的剖视图。
图15是表示第2实施方式的半导体存储卡的第3构成例及其制造工序的剖视图。
图16是表示图15所示的半导体存储卡的最终构成的剖视图。
图17是表示第2实施方式的半导体存储卡的第4构成例及其制造工序的剖视图。
图18是表示图17所示的半导体存储卡的最终构成的剖视图。
符号说明：
1、31存储卡，2、2引线框，3外部连接端子，4引线部，41、42引线，5芯片部件搭载部，6半导体芯片搭载部，7芯片部件，8控制器芯片，9存储器芯片，10封装树脂层，15凹部，16加工部，19、22电极焊盘，20、26、27金属线，24再布线层，32金属镀层，33镀覆用连接端子，35、37绝缘树脂层。
具体实施方式
以下，关于实施方式的半导体存储卡，参照附图进行说明。
（第1实施方式）
图1~图3是表示第1实施方式涉及的半导体存储卡的图。图1是第1实施方式涉及的半导体存储卡的上表面图，是透射地表示半导体存储卡的构成的图（上表面透视图），图2是第1实施方式涉及的半导体存储卡的仰视图，图3是对第1实施方式涉及的半导体存储卡在长边方向（插入于卡槽的方向）剖切的剖视图。这些图所示的半导体存储卡1用作各种规格的存储卡。
存储卡1具备引线框2作为兼作端子部件、布线部件和元件搭载部件的引线电路部件。引线框2具备多个外部连接端子3、具有至少一部分连接于外部连接端子3的多条引线的引线部4、设置于引线部4的芯片部件搭载部5、和半导体芯片搭载部6。在芯片部件搭载部5，搭载有芯片部件（从动部件）7。在半导体芯片搭载部6，搭载有控制器芯片8和NAND型闪速存储器那样的存储器芯片9。控制器芯片8是进行向存储器芯片9的数据的写入和／或存储于存储器芯片9的数据的读出等的半导体芯片。
引线框2由封装树脂层10封装。封装树脂层10以使外部连接端子3的表面露出并且将引线框2与芯片部件7、控制器芯片8、存储器芯片9等一起进行封装的方式，通过传递成型而形成例如环氧树脂等封装树脂。封装树脂层10具有基本矩形状的外形，构成存储卡1的整体形状。封装树脂层10的露出外部连接端子3的第1面10a（图2）相当于存储卡1的背面。封装树脂层10的与第1面10a相反侧的第2面10b（图1）相当于存储卡1的表面。
封装树脂层10的外形边11之中接近外部连接端子3的第1短边11A相当于存储卡1的前端部。在封装树脂层10的前端，设置有表示存储卡1的前方的倾斜部10c。封装树脂层10的第2短边11B相当于存储卡1的后方部。在封装树脂层10的后方，设置有使其一部分向第2面10b侧凸起的把持部10d。在封装树脂层10的第1长边11C，形成有切口部12和／或收缩部13，表示存储卡1的前后和／或表背的朝向。封装树脂层10的第2长边11D为直线形状。
多个外部连接端子3的前端配置于封装树脂层10内。在第1实施方式中，在外部连接端子3的前端不设置悬置引线。由此，防止在封装树脂层10的前端残留悬置引线。多个外部连接端子3从未图示的框架分离，所以在其上粘接有固定带14A。多个外部连接端子3通过固定带14A保持。多个外部连接端子3的表面分别在封装树脂层10的第1面10a露出。在使外部连接端子3的表面在封装树脂层10的第1面10a露出时，对引线框2的外部连接端子3与引线部4的连接部分进行弯曲加工，并且在封装树脂层10的第1面10a设置包围外部连接端子3的周围的凹部15。
即，外部连接端子3在封装树脂层10的第1面10a露出，相对于此，连接于外部连接端子3的引线部4和／或半导体芯片搭载部6等埋设于封装树脂层10内。因此，引线框2具有对外部连接端子3和引线部4的连接部分进行弯曲加工而成的加工部16。加工部16使外部连接端子3露出于外部，并使引线部4和／或半导体芯片搭载部6等配置于封装树脂层10内，具有使外部连接端子3与引线部4的连接部分暂时向上方弯曲之后返弯向水平方向的形状。通过将这样的加工部16设置于引线框2，能够使外部连接端子3露出于外部，并提高除了外部连接端子3之外的引线框2的构成部（引线部4、芯片部件搭载部5、半导体芯片搭载部6等）和／或芯片部件7、控制器芯片8、存储器芯片9等的树脂封装性。
在第1实施方式的存储卡1中，为了提高外部连接端子3的向外部的露出性，除了在引线框2设置加工部16之外，还在封装树脂层10的第1面10a设置使外部连接端子3的表面及侧面的一部分露出的凹部15。凹部15设置得包围外部连接端子3的周围。凹部15既可以如图2所示设置得分别包围多个外部连接端子3，也可以如图4所示设置得一并包围多个外部连接端子3。凹部15如图5和／或图6放大所示，具有除了外部连接端子3的表面3a之外还使侧面3b的一部分露出的形状。通过在封装树脂层10的第1面10a设置这样的凹部15，外部连接端子3的表面3a的露出性提高。进而，通过以包围外部连接端子3的周围的方式设置凹部15，外部连接端子3的外周形状变得稳定。由此，可以使外部连接端子3的功能充分地发挥。
凹部15设置为，从封装树脂层10的第1面10a起凹陷。优选：凹部15的距第1面10a的深度D1为10~300μm的范围。在凹部15的深度D1不足10μm的情况下，有可能无法使外部连接端子3的表面3a完全地露出。若凹部15的深度D1超过300μm，则当从外部设备的插座拔出存储卡1时，凹部15有可能卡住插座侧的端子等而难以取出存储卡1。凹部15的外形形状只要是可以包围外部连接端子3的全周并使外部连接端子3的侧面3b的一部分露出的形状即可，凹部15的宽度（从外部连接端子3的侧面3b到封装树脂层10的壁面15a的距离）并无特别限定。
虽然图5示出使外部连接端子3的表面3a与封装树脂层10的第1面10a为基本相同的高度的结构，但是外部连接端子3的配置结构并不限于此。外部连接端子3也可以如图7所示配置为，使表面3a从封装树脂层10的第1面10a凹陷。但是，因为若外部连接端子3的表面3a距封装树脂层10的第1面10a的深度D2过深，则存储卡1的插拔性有可能反而降低，所以优选：深度D2为100μm以下。通过使外部连接端子3的表面3a凹陷，能够抑制外部连接端子3的损伤和／或摩耗等的产生。另外，如在第2实施方式中详述地，当在外部连接端子3的表面3a形成金属镀层时，能够防止端子表面从第1面10a突出。
封装树脂层10的凹部15例如通过对封装树脂层10照射激光、紫外线、等离子等并除去相当于封装树脂层10的凹部15的形成位置的部分而形成。关于凹部15的形成工序，参照图8进行说明。首先，在引线框2上搭载芯片部件7、控制器芯片8、存储器芯片9，并进而形成与这些部件一起对引线框2进行封装的封装树脂层10。封装树脂层10例如通过传递成型而形成。因此，外部连接端子3的表面3b如图8（a）所示，成为由封装树脂曾10覆盖的状态。
在将外部连接端子3的表面3a设定为与封装树脂层10的第1面10a同一面的情况下，因为外部连接端子3的表面3a被成型模覆盖，所以在表面3a上并不形成封装树脂层10。但是，在通常的传递成型中，难以完全地抑制向外部连接端子3的表面3a产生树脂毛边。因此，在形成了封装树脂层10的阶段，不可避免外部连接端子3的表面3a的至少一部分成为由构成封装树脂层10的树脂覆盖的状态。因此，如图8（b）所示，包括外部连接端子3的表面3a之上，对封装树脂层10的凹部15的形成区域照射激光L。也可以代替激光L而照射紫外线和／或等离子。
通过对封装树脂层10照射激光L，除去存在于外部连接端子3的表面3a上的树脂，同时以包围外部连接端子3的全周的方式形成使外部连接端子3的侧面3b的一部分露出的凹部15。凹部15既可以如图2和／或图6所示形成得分别包围各个外部连接端子3的外周，也可以如图4所示一并包围多个外部连接端子3的外周。通过在封装树脂层10的第1面10a形成这样的凹部15，能够切实地使外部连接端子3的表面3a露出，并使外部连接端子3的外周形状稳定。从而，可以使外部连接端子3的功能充分地发挥。
引线部4具有直接连接于外部连接端子3的引线41和与外部连接端子3电独立的引线42。这些引线41、42之中，第1、第2及第3引线41A、41B、41C的一方端部直接连接于外部连接端子3。第1引线41A的另一方端部配置于控制器芯片8的附近区域。在第2引线41B和与其电独立的第4引线42A，设置有第1芯片部件搭载部5A。在第1芯片部件搭载部5A，与第2引线41B及第4引线42A电连接而搭载有熔丝等第1芯片部件7A。第4引线42A进一步引绕至控制器芯片8的附近区域。
第3引线41C在控制器芯片8的附近区域引绕，之后分支。在第3引线41C的一方分支部41C1和与其电独立的第5引线42B，设置有第2芯片部件搭载部5B。在第2芯片部件搭载部5B，与第3引线41C的分支部41C1及第5引线42B电连接而搭载有电容器等第2芯片部件7B。在第3引线41C的另一方分支部41C2和与其电独立的第6引线42C，设置有第3芯片部件搭载部5C。在第3芯片部件搭载部5C，与第3引线41C的分支部41C2及第6引线42C电连接而搭载有电容器等第3及第4芯片部件7C、7D。第5及第6引线42B、42C进一步引绕至存储器芯片9的附近。
半导体芯片搭载部6具有朝向封装树脂层10的短边11B扩展的扩展部6a，在该扩展部6a设置有与未图示的框架连接的悬置引线17。进而，引线框2具有沿着封装树脂层10的两条长边11C、11D设置的固定部18。在固定部18，设置有悬置引线17。半导体芯片搭载部6与固定部18电独立。半导体芯片搭载部6和／或引线部4的一部分通过粘接于设置有悬置引线17的固定部18的固定带14B保持。固定带14B从固定部18粘接到半导体芯片搭载部6、进而到引线部4的一部分，将半导体芯片搭载部6和／或引线部4的一部分固定于被悬置引线17支持的固定部18。
这样，半导体芯片搭载部6在封装树脂层10的两个侧面（具有长边11C、11D的面）间电独立。即，半导体芯片搭载部6不与设置于封装树脂层10的两个侧面的悬置引线17导通，两个侧面的悬置引线17间电独立。通过应用这样的半导体芯片搭载部6，即使在封装树脂层10的两个侧面与外部的导通部件接触等情况下，半导体芯片搭载部6也不会发生短路。从而，即使在封装树脂层10的两个侧面间发生了短路的情况下，也能够抑制控制器芯片8和／或存储器芯片9产生不良状况等，可以提高存储卡1的可靠性。
配置于半导体芯片搭载部6上的控制器芯片8及存储器芯片9分别具有矩形状的外形。控制器芯片8配置于外部连接端子3与存储器芯片9之间。即，控制器芯片8配置于比存储器芯片9更接近外部连接端子3的一侧。控制器芯片8具有沿着接近外部连接端子3的一侧的长边排列的电极焊盘19A和沿着接近存储器芯片9的一侧的长边排列的电极焊盘19B。控制器芯片8的接近外部连接端子3的一侧的电极焊盘19A与第1、第3、第4引线41A、41C、42A介由金属线20电连接。
存储器芯片9例如如图9所示具有：具有省略了图示的半导体元件部等的芯片主体21；形成于芯片主体21的电极焊盘22；以使电极焊盘22露出并覆盖芯片主体21的表面的方式形成的绝缘树脂膜23；和形成于绝缘树脂膜23上的再布线层24。根据控制器芯片8和存储器芯片9的电极焊盘19、22的排列和／或种类等，需要对存储器芯片9的电极焊盘22进行再配置。设置于包括聚酰亚胺树脂等的绝缘树脂膜（保护膜）23上的再布线层24将电极焊盘22再配置于存储器芯片9上的预期的位置，例如一方端部与电极焊盘22电连接，在另一方端部形成有作为金属线的接合部的连接焊盘25。
考虑金属线对于再布线层24的接合性，优选：再布线层24的至少最表面层由Al和／或Al-0.5质量%Cu合金等Al合金、或者Au和／或Pd等贵金属材料等形成。进而，若考虑再布线层24向绝缘树脂膜23上的形成性和／或紧密附着性等，则优选：再布线层23的最下层由Ti和／或Cr等形成。作为再布线层24的具体的构成，可举出Al／Ti、Al-Cu／Ti、Au／Ni／Ti、Au／Ni／Cu／Ti等的层叠膜。在由Al层（包括Al合金层）和／或贵金属层形成再布线层24的最表面层的情况下，优选：最表面层的厚度在确保接合性的基础上为2μm以上。因为即便使最表面层过厚也得不到更高的效果，所以优选：其厚度为5μm以下。
构成再布线层24的再布线之中的至少一部分再布线24A的一方端部与电极焊盘22电连接，并且在另一方端部形成有连接焊盘25。在形成于再布线24A的端部的连接焊盘25，接合着金属线26的一方端部。金属线26的另一方端部接合于控制器芯片8的电极焊盘19B和／或引线41C、42B、42C。即，再布线24A介由金属线26与控制器芯片8的电极焊盘19B和／或引线41C、42B、42C电连接。
再布线24A与电极焊盘22的电连接结构既可以如图9所示为直接连接的结构，也可以如图10所示为介由金属线27而连接的结构。当在连接再布线24A的电极焊盘22的附近存在其他的电极焊盘（例如不同电位的电极焊盘22a）的情况下，如图10所示，通过以跨过不同电位的电极焊盘22a的方式配置金属线27，能够将再布线24A连接于电极焊盘22。基于金属线27形成的跳线结构对于跨过不同电位的再布线和／或引线的结构也是有效的。第4引线42A介由以跨过不同电位的第1引线41A的方式配置的金属线27，与同电位的第6引线42C电连接。通过应用基于这样的金属线27形成的跳线结构，可以提高基于单层结构的再布线层24形成的电路的形成性。
在第1实施方式的存储卡1中，因为在封装树脂层10的第1面10a设置使外部连接端子3的表面3a及侧面3b的一部分露出并包围外部连接端子3的周围的凹部15，所以能够在使用引线框2谋求存储卡1的低成本化的基础上，使外部连接端子3的露出性提高。进而，外部连接端子3的外周形状也变得稳定。从而，可以提高存储卡1的基于外部连接端子3实现的与外部设备的连接可靠性即存储卡1的工作可靠性。
（第2实施方式）
接下来，关于第2实施方式涉及的存储卡，参照图11~图18进行说明。对于与第1实施方式相同的部分附加相同符号，并省略其说明的一部分。第2实施方式涉及的存储卡31如图11所示，具备设置于从封装树脂层10露出的外部连接端子3的表面3a及侧面3b上的金属镀层32。在第2实施方式涉及的存储卡31中，基本的结构除了在外部连接端子3上设置有金属镀层32之外，与第1实施方式的存储卡1相同。在封装树脂层10的第1面10a，设置有使外部连接端子3的表面3a及侧面3b的一部分露出并包围外部连接端子3的周围的凹部15。凹部15的具体的结构等也与第1实施方式相同。
引线框2一般通过Fe-Ni类合金（例如Fe-42%Ni合金）和／或Cu合金等形成。因此，在露出于外部的外部连接端子3的表面3a及侧面3b，在使用时有可能形成表面氧化膜、或产生腐蚀和／或锈等。为了抑制这样的表面氧化膜、腐蚀、锈等的产生，在外部连接端子3的露出的表面3a和／或侧面3b形成金属镀层32。作为金属镀层32的代表性的构成材料，可举出Au和／或Pd等贵金属。金属镀层32并不限于Au和／或Pd的单层膜，也可以为Au／Cu、Pd／Cu、Au／Ni、Pd／Ni、Au／Ni／Cu、Pd／Ni／Cu、Au／Pd／Ni、Au／Pd／Ni／Cu等的层叠膜。另外，根据存储卡31的使用用途等，也能够不在外部连接端子3上形成金属镀层32来使用存储卡31。
为了在外部连接端子3的露出的表面3a和／或侧面3b上以电镀法形成金属镀层32，需要在外部连接端子3上连接电镀用接触引脚。在金属镀层32的形成前的阶段，外部连接端子3的表面3a露出。从而，通过使电镀用接触引脚接触于外部连接端子3的露出的表面3a，能够在外部连接端子3的露出的表面3a及侧面3b进行电镀。但是，若使接触引脚接触于外部连接端子3的表面3a而进行电镀，则镀覆金属会不附着于表面3a的接触着接触引脚的部分，成为使表面氧化膜、腐蚀、锈等产生的原因。
在第2实施方式的存储卡31中，引线框2在外部连接端子3之外，具有从封装树脂层10露出的镀覆用连接端子。关于涂敷用连接端子的具体的构成进行描述。图12表示镀覆用连接端子33的第1构成例。图12所示的引线框2具有以使得连接于外部连接端子3的引线41的一部分在封装树脂层10的第1面10a露出的方式通过对引线41进行弯曲加工而形成的镀覆用连接端子33A。引线41在暂时朝向封装树脂层10的第1面10a弯曲而将引线41的一部分配置为与第1面10a相同的高度之后，弯曲返回至半导体芯片搭载部6的高度。
如图12所示，通过使电镀用接触引脚34接触于从封装树脂层10露出的镀覆用连接端子33A而进行电镀，在外部连接端子3的露出的表面3a及侧面3b形成金属镀层32。通过这样进行电镀，能够在外部连接端子3的露出的表面3a及侧面3b的整体良好地形成金属镀层32。在形成了金属镀层32之后，如图13所示，以覆盖镀覆用连接端子33A的方式在封装树脂层10的第1面10a形成绝缘树脂层35。绝缘树脂层35通过粘贴绝缘膜或者涂敷绝缘树脂膏而形成。
上述的引线41的弯曲加工不仅对于镀覆用连接端子33A的形成实施，而且也可以对于芯片部件搭载部5实施。即，芯片部件7的高度一般比控制器芯片8和／或存储器芯片9的高度要高。因此，若使芯片部件搭载部5的高度（离开封装树脂层10的第1面10a的高度）与半导体芯片搭载部6的高度相同，则芯片部件7上的树脂厚度变薄，由封装树脂层10实现的芯片部件7的覆盖性有可能降低。对于这一点，下述方法是有效的：如图14所示，将半导体芯片搭载部6的高度设定为，从半导体芯片搭载部6到第1面10a的树脂厚度T1与从控制器芯片8和／或存储器芯片9的上表面到第2面10b的树脂厚度T2基本相等，在此基础上将芯片部件搭载部5配置于比半导体芯片搭载部6靠近封装树脂层10的第1面10a的位置。
这样，通过将半导体芯片搭载部6配置于使得树脂厚度T1与树脂厚度T2基本相等的位置，并将芯片部件搭载部5配置于可使芯片部件7由封装树脂层10充分地覆盖的位置，可以在防止芯片部件7的覆盖性的降低和／或伴随于此的芯片部件7向外部的露出等的基础上，抑制树脂封装工序中的半导体芯片搭载部6的位置偏离和／或封装树脂层10的翘曲等的产生。即，能够提高使用了引线框2的存储卡31的制造性和／或可靠性等。
图14所示的芯片部件搭载部5A、5B以配置于比半导体芯片搭载部6靠近封装树脂层10的第1面10a的位置的方式设置于弯曲加工过的引线41、42。这些部件之中，芯片部件搭载部5A以使得引线41的一部分在封装树脂层10的第1面10a露出的方式设置于弯曲加工过的引线41，并兼作镀覆用连接端子33B。通过使电镀用接触引脚34接触于这样的镀覆用连接端子33B，也可以进行电镀。图14所示的镀覆用连接端子33B与图13所示的镀覆用连接端子33A同样地，也在形成了金属镀层32之后由绝缘树脂层35覆盖。
图15表示镀覆用连接端子33的第2构成例。图15所示的存储卡31具有以使外部连接端子3的背面露出的方式从封装树脂层10的第2面10b设置的开口部36。外部连接端子3的背面的一部分在开口部36内露出，该部分作为镀覆用连接端子33C而起作用。通过使电镀用接触引脚34接触于在开口部36内露出的外部连接端子3的背面（镀覆用连接端子33C）而进行电镀，也能够在露出于封装树脂层10的第1面10a侧的外部连接端子3的表面3a及侧面3b的整体良好地形成金属镀层32。在形成了金属镀层32之后，如图16所示，在开口部36内填充绝缘树脂37。或者，也可以与第1构成例同样地，在封装树脂层10的第2面10b形成绝缘树脂层35而堵塞开口部36。
图17表示镀覆用连接端子33的第3构成例。在图17所示的引线框2中，在外部连接端子3的前端设置悬置引线17，使从该封装树脂层10的前端面10e突出的悬置引线17作为镀覆用连接端子33D而起作用。通过使电镀用接触引脚38接触于从封装树脂层10的前端面突出的镀覆用连接端子33D而进行电镀，也能够在露出于封装树脂层10的第1面10a的外部连接端子3的表面3a及侧面3b的整体良好地形成金属镀层32。在形成了金属镀层32之后，如图18所示，将悬置引线17的从封装树脂层10的前端面10e突出的部分切断，之后在前端面10e形成绝缘树脂层35。绝缘树脂层35与第1构成例同样地，通过绝缘膜的粘贴和／或绝缘树脂膏的涂敷等形成。
另外，虽然对本发明的几种实施方式进行了说明，但是这些实施方式是作为例子而呈现的，并非要对发明的范围进行限定。这些新的实施方式能够以其他的各种方式实施，在不脱离发明的主旨的范围，能够进行各种省略、替换、变更。这些实施方式和／或其变形包括于发明的范围和／或主旨，并包括于权利要求的范围所记载的发明及其等同的范围。

Claims (5)

1.一种半导体存储卡，其特征在于，具备：
引线框，其具备多个外部连接端子、具有至少一部分连接于所述外部连接端子的多条引线的引线部、设置于所述引线部的芯片部件搭载部、和半导体芯片搭载部；
芯片部件，其搭载于所述芯片部件搭载部，且与所述引线电连接；
搭载于所述半导体芯片搭载部且与所述引线电连接的控制器芯片及与所述控制器芯片电连接的存储器芯片；
封装树脂层，其将所述引线框与所述芯片部件、所述控制器芯片及所述存储器芯片一起进行封装，具有作为所述外部连接端子的露出面的第1面、和凹部，所述凹部使所述外部连接端子的表面露出，并且使所述外部连接端子的侧面的一部分露出并以包围所述外部连接端子的周围的方式设置于所述第1面且距所述第1面的深度处于10～300μm的范围；以及
金属镀层，其设置于所述外部连接端子的露出的所述表面及所述侧面；
其中，所述引线框在所述外部连接端子之外具有从所述封装树脂层露出的镀覆用连接端子；
所述引线框具有设置于所述封装树脂层的一方侧面的第1悬置引线和设置于所述封装树脂层的另一方侧面的第2悬置引线；
所述半导体芯片搭载部在所述第1悬置引线与所述第2悬置引线之间电独立；
所述凹部的底面位于所述外部连接端子的表面与背面之间。
2.一种半导体存储卡，其特征在于，具备：
引线框，其具备多个外部连接端子、具有至少一部分连接于所述外部连接端子的多条引线的引线部、设置于所述引线部的芯片部件搭载部、和半导体芯片搭载部；
芯片部件，其搭载于所述芯片部件搭载部，且与所述引线电连接；
搭载于所述半导体芯片搭载部且与所述引线电连接的控制器芯片及与所述控制器芯片电连接的存储器芯片；以及
封装树脂层，其将所述引线框与所述芯片部件、所述控制器芯片及所述存储器芯片一起进行封装，具有作为所述外部连接端子的露出面的第1面、和凹部，所述凹部使所述外部连接端子的表面露出，并且使所述外部连接端子的侧面的一部分露出并以包围所述外部连接端子的周围的方式设置于所述第1面，
所述凹部的底面位于所述外部连接端子的表面与背面之间。
3.根据权利要求2所述的半导体存储卡，其特征在于：
还具备设置于所述外部连接端子的露出的所述表面及所述侧面的金属镀层；
所述引线框在所述外部连接端子之外具有从所述封装树脂层露出的镀覆用连接端子。
4.根据权利要求2或3所述的半导体存储卡，其特征在于：
所述引线框具有设置于所述封装树脂层的一方侧面的第1悬置引线和设置于所述封装树脂层的另一方侧面的第2悬置引线；
所述半导体芯片搭载部在所述第1悬置引线与所述第2悬置引线之间电独立。
5.一种半导体存储卡的制造方法，其特征在于，包括：
准备引线框的工序，所述引线框具备多个外部连接端子、具有至少一部分连接于所述外部连接端子的多条引线的引线部、设置于所述引线部的芯片部件搭载部、和半导体芯片搭载部；
在所述芯片部件搭载部搭载芯片部件的工序；
在所述半导体芯片搭载部搭载控制器芯片和存储器芯片的工序；
将所述控制器芯片与所述引线电连接的工序；
将所述存储器芯片与所述控制器芯片电连接的工序；
形成将所述引线框与所述芯片部件、所述控制器芯片及所述存储器芯片一起进行封装的封装树脂层的工序；以及
在所述封装树脂层的作为所述外部连接端子的露出面的第1面形成凹部的工序，所述凹部使所述外部连接端子的表面露出，并且使所述外部连接端子的侧面的一部分露出并包围所述外部连接端子的周围，
所述凹部的底面位于所述外部连接端子的表面与背面之间。
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