CN104752413A - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN104752413A
CN104752413A CN201410453249.8A CN201410453249A CN104752413A CN 104752413 A CN104752413 A CN 104752413A CN 201410453249 A CN201410453249 A CN 201410453249A CN 104752413 A CN104752413 A CN 104752413A
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lead
wire
semiconductor chip
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semiconductor device
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石井齐
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Kioxia Corp
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Toshiba Corp
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
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    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
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    • H01—ELECTRIC ELEMENTS
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/48147—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked with an intermediate bond, e.g. continuous wire daisy chain
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Abstract

本发明提供一种小型化、高密度化推进的半导体装置，其可以将内引线间连接。本发明的实施方式的半导体装置包含：多根引线，包括内引线及外引线；半导体芯片，设置在多根引线上；间隔片，介于半导体芯片与多根引线之间，在半导体芯片的背面与多根引线之间形成间隙；导线，设置在间隙，且在半导体芯片的背面下将内引线间电性连接；以及第1绝缘层，设置在所述半导体芯片与所述导线之间。

Description

半导体装置
[相关申请案] 
本申请案享受将日本专利申请案2013-269434号(申请日：2013年12月26日)作为基础申请案的优先权。本申请案是通过参照该基础申请案而包含基础申请案的全部内容。 
技术领域
本发明涉及一种半导体装置。 
背景技术
随着半导体装置的高速化，变得容易受到电源(Vcc)或接地(Vss)的电位变动的影响。尤其是，数据的I/O(Input/Output，输入输出)信号受到电源、接地、或这两者的电位变动的影响，而造成在I/O信号上升/下降部分的偏差变大。因此，为了使电源或接地的电位稳定化(强化)或使电源-接地间的电感降低，进行利用金属导线将电源用引线间或接地(ground)用引线间电连接的操作。另外，为了提高半导体装置的通用性，进行变更控制信号或I/O信号等内引线的排列顺序与外引线的排列顺序的操作。该情况下，在封装体内，利用中继用金属导线将引线彼此连接，由此改变电极垫的排列顺序与外引线的排列顺序，所述中继用金属导线是以跨越位于引线彼此之间的引线的方式设置。 
另外，近年来，半导体装置的小型化、高密度化不断推进。例如有在封装体内积层半导体芯片而得到的半导体装置或使半导体芯片大型化而得到的半导体装置。然而，在这种半导体装置中，半导体芯片所占据的区域变大(变宽)，所以难以确保在封装体内设置金属导线的空间。另外，如果想要确保在封装体内设置金属导线的空间，那么封装体会变大。 
如上所述，寻求一种小型化、高密度化推进的半导体装置，其可以将内引线间连接。 
发明内容
本发明提供一种小型化、高密度化推进的半导体装置，其可以将内引线间连接。 
实施方式的半导体装置包含：多根引线，包括内引线及外引线；半导体芯片，设置在多根引线上；间隔件，介于半导体芯片与多根引线之间，在半导体芯片的背面与多根引线之间形成间隙；导线，设置在间隙，且在半导体芯片的背面下将内引线间电连接；以及第1绝缘层，设置在所述半导体芯片与所述导线之间。 
附图说明
图1是表示第1实施方式的半导体装置的俯视图。 
图2是表示第1实施方式的半导体装置的放大剖视图。 
图3是实施方式的半导体装置的局部俯视图。 
图4是线段X-X处的剖视图。 
图5是表示实施方式的半导体装置的制造方法的流程图。 
具体实施方式
(第1实施方式) 
图1是实施方式的半导体装置100的俯视图。图2是实施方式的半导体装置100的局部放大剖视图。在该实施方式中，半导体装置100是TSOP(Thin Small Outline Packeage，薄型小尺寸封装)型的半导体装置。 
如图1、图2所示，半导体装置100包括引线基板110、半导体芯片121～124、间隔件130、导线140、密封树脂150及绝缘层F1～F4。此外，于图1中，以实线而非点划线记载利用密封树脂150进行密封的半导体芯片121～124、间隔件130及导线140。 
引线基板110具有多根引线111。对于各引线111，使用导电性优异的金属材料、例如铜(Cu)或铁(Fe)、镍(Ni)。各引线111具有：内引线111A，被密封在密封树脂150内；以及外引线111B，从密封树脂150露出。内引线111A主要作为与半导体芯片121～124的电极垫的连接部发挥功能。外引线111B作为外部连接端子发挥功能。此外，多根引线111是利用绝缘性的固定胶带(例如聚酰亚胺(Polyimide))加以固定，以使位置不偏移。 
各引线111包括多根引线，该多根引线包含电源用(Vcc)引线、接地用(Vss)引线、控制信号用引线、以及输入输出(I/O)用引线。此处，在控制信号用引线中，包含芯片使能(CE)、写入使能(WE)、引线使能(RE)、指令锁定使能(CLE)、地址锁存使能(ALE)、写入保护(WP)、就绪/忙碌(R/B)、数据选通信号(DQS)等引线。 
此外，各引线的排列顺序是根据供搭载半导体装置100的封装板的规格等而有所不同。 
半导体芯片121～124例如为NAND(NOT-AND，与非)型闪速存储器等存储元件及它的控制器元件。在半导体芯片121～124的一边侧，以沿其一边排列的方式分别形成着多个电极垫121P～124P。各半导体芯片121～124是以沿一边侧形成的电极垫121P～124P露出的方式呈阶梯状积层在引线基板110上。 
在各半导体芯片121～124的背面121R～124R，配置着绝缘层F1～F4。绝缘层F1～F4兼作为粘着层，绝缘层F1～F4例如为晶粒附着膜(Die Attach Film)(接着剂膜)。作为绝缘层F1～F4的具体材料，例如使用以聚酰亚胺树脂、环氧树脂、丙烯酸系树脂等为主要成分的热硬化性或光硬化性的材料。各半导体芯片122～124是利用绝缘层F1～F3而接着于各半导体芯片121～123上。 
绝缘层F1(第1绝缘层)配置在半导体芯片121的背面121R，且覆盖半导体芯片121的背面121R整体。也就是说，绝缘层F1位于半导体芯片121的背面121R与导线140之间，所以半导体芯片121与间隔件130及导线140绝缘。由此，可以防止在动作时半导体芯片121与导线140接触而造成电性短路。 
此外，在图2中，积层4片半导体芯片。然而，所积层的半导体芯片的片数并不限定于4片。半导体芯片的片数只要1片以上即可。通过积层为阶梯状而露出的半导体芯片121～124的电极垫121P～124P是利用Au导线或Cu导线等金属导线W而与引线111的内引线111A电连接。 
间隔件130介于引线基板110与最下层的半导体芯片121的背面121R之间。间隔件130是在引线基板110与最下层的半导体芯片121的背面121R之间形成间隙S。间隙S的高度D1优选为70μm以上。此外，如果间隙S的高度D1过高，那么半导体装置100变厚。因此，间隙S的高度D1优选为小于等于100μm。 
间隔件130包括粘着层131及绝缘层(第2绝缘层)132。对于粘着层131，例如使用以聚酰亚胺树脂、环氧树脂、丙烯酸系树脂等为主要成分的热硬化性或光硬化性的材料。另外，对于绝缘层132，使用绝缘性的材料、例如聚酰亚胺树脂。 
此外，在图1中，在半导体芯片121的背面121R与引线基板110之间存在6个间隔件130。然而，间隔件130只要可以确保设置下述导线140的空间即可。因此，设置间隔件130的位置并不限定于图1所示的位置。例如也可以将间隔件130配置在半导体芯片121的背面121R的四角。 
导线140例如为使用了导电性优异的金(Au)、铜(Cu)、铝(A1)或这些金属的合金的 金属导线。导线140将内引线111A间电连接。在该实施方式中，导线140是在最下层的半导体芯片121的背面121R下，将电源用(Vcc)引线的内引线111A间、接地用(Vss)引线的内引线111A间及控制信号用引线的内引线111A间的至少一个以上的内引线111A间电连接。 
密封树脂150将引线基板110、半导体芯片121～124、间隔件130、导线140及绝缘层F1～F4密封。此外，各引线111的外引线111B是在露出的状态下被密封树脂150密封。 
接下来，对利用半导体装置100的导线140而完成的内引线111A间的连接更详细地进行说明。图3是半导体装置100的局部俯视图。图4是图3的线段X-X处的剖视图。在图3、图4中，表示利用导线140将电源用(Vcc)引线的内引线111A间及接地用(Vss)引线的内引线111A间电连接的例子。此外，在图3中，省略半导体芯片121～124、密封树脂150及绝缘层F1～F4的图示。另外，将金属导线W以点划线表示到中途为止。在图4中，省略间隔件130及密封树脂150的图示。 
如图3所示，导线140是以跨越其他内引线111A的状态，将电源用(Vcc)引线的内引线111A间及接地用(Vss)引线的内引线111A间电连接。此外，在图3所示的例中，导线140跨越输入输出(I/O)用引线。在输入输出(I/O)用引线的附近，容易受到电源(Vcc)或接地(Vss)的电位的影响。因此，优选为如图3所示，将配置在输入输出(I/O)用引线的周围的电源用(Vcc)引线及接地用(Vss)引线的内引线111A间电连接。然而，导线140也可以跨越其他引线、例如控制信号用引线。 
另外，如图3所示，在被夹于利用导线140而电连接的电源用(Vcc)引线及接地用(Vss)引线的内引线111A间的输入输出(I/O)用引线的内引线111A，形成着凹部111C。此外，如图3所示，在该半导体装置100中，在导线140所跨越的区域形成凹部111C。 
因此，如图4所示，连接着导线140的电源用(Vcc)引线及接地用(Vss)引线的内引线111A的上表面S1、S2与半导体芯片121的背面121R的距离D2短于被连接着导线140的电源用(Vcc)引线及接地用(Vss)引线的内引线111A所夹的输入输出(I/O)用引线的内引线111A的上表面S3与半导体芯片121的背面121R的距离D3。此外，距离D2为与距离D1相同的距离。 
也就是说，通过形成凹部111C，而使被利用导线140而连接的内引线111A所夹的内引线111A的上表面的位置低于利用导线140而连接的内引线111A的上表面。因此，可以减少导线140与除作为连接对象的内引线111A以外的内引线111A接触的担忧。另外，通过形成凹部111C，内引线111A的上表面与半导体芯片121的背面121R的距离 变长。因此，可以减少半导体芯片121与形成着凹部111C的内引线111A的寄生电容。 
此外，内引线111A的凹部111C可以通过干式蚀刻或湿式蚀刻而形成。另外，也可以对内引线111A施加压力，而在上下方向将它压扁。通过压扁，内引线111A的厚度变薄，从而可以形成凹部111C(压印加工)。另外，也可以通过压下加工使内引线111A向下方弯折而形成凹部111C。压印加工或压下加工可以抑制内引线111A的截面积的减少。因此，可以抑制形成着凹部111C的内引线111A的电阻增加。 
此外，在图3、图4所示的例子中，为了使电源(Vcc)或接地(Vss)的电位稳定化(强化)或使电源-接地间的电感降低，利用导线140将电源用(Vcc)引线的内引线111A间及接地用(Vss)引线的内引线111A间电连接。然而，为了变更内引线111A的排列顺序与外引线111B的排列顺序，也可以利用导线140将控制信号用引线及/或输入输出(I/O)用引线的内引线111A间电连接。 
(半导体装置100的制造) 
图5是表示半导体装置100的制造方法的流程图。以下，参照图1～图5，对半导体装置100的制造方法进行说明。 
在引线基板110的特定位置安装间隔件130(步骤S101)。间隔件130的安装也可以在引线基板110的制造步骤的中途且压下加工或压印加工、对引线的前端的切断加工之前进行。 
接下来，利用导线140将引线基板110的引线111中的所期望的引线111的内引线111A间电连接(步骤S102)。对于导线140的连接，使用既有的导线接合装置。 
接下来，在半导体芯片121～124的背面121R～124R配置绝缘层F1～F4(步骤S103)。对于绝缘层F1～F4，使用晶粒附着膜等接着剂膜。 
接下来，在间隔件130上呈阶梯状积层半导体芯片121～124及绝缘层F1～F4(步骤S104)。 
接下来，利用金属导线W将所积层的半导体芯片121～124的电极垫121P～124P及引线基板110的内引线111A电连接(步骤S105)。此外，对于金属导线W的连接，使用既有的导线接合装置。 
接下来，利用密封树脂150将引线基板110、半导体芯片121～124、间隔件130、导线140及金属导线W等密封(步骤S106)。 
接下来，对从密封树脂150露出的外引线111B进行弯曲加工或切断加工等(步骤S107)。此外，也可以在将间隔件130贴附在半导体芯片121的背面之后，对引线基板110上安装半导体芯片121。 
如上所述，半导体装置100包括在半导体芯片121的背面121R与多根引线111之间形成间隙S的间隔件130。而且，在该间隙S中，通过导线140将内引线111A间电连接。 
因此，当在封装半导体芯片121～124的区域的外侧无用于设置导线140的空间时，也可以利用导线140将内引线111A间电连接。 
另外，使被利用导线140而连接的内引线111A所夹的内引线111A的上表面的位置低于利用导线140而连接的内引线111A的上表面。因此，可以减少导线140与除作为连接对象的内引线111A以外的内引线111A接触的担忧。进而，通过形成凹部111C，而使内引线111A的上表面与半导体芯片121的背面121R的距离变长，从而在半导体芯片121的背面121R与内引线111A间设置绝缘层F1。因此，可以减少半导体芯片121与形成着凹部111C的内引线111A的寄生电容。 
进而，当通过压印加工或压下加工形成内引线111A的凹部111C时，可以抑制内引线111A的截面积的减少。因此，可以抑制形成着凹部111C的内引线111A的电阻增加。 
对本发明的若干实施方式进行了说明，但这些实施方式是作为示例而提出的，并非意图限定发明的范围。这些新颖的实施方式能够以其他各种形态实施，可以在不脱离发明的主旨的范围内进行各种省略、替换、变更。这些实施方式及其变化包含在发明的范围或主旨中，并且包含在权利要求中所记载的发明及其均等范围内。 
[符号的说明] 
100         半导体装置 
110         引线基板 
111         引线 
111A        内引线 
111B        外引线 
121～124    半导体芯片 
121P～124P  电极垫 
121R～124R  背面 
130         间隔件 
131         粘着层 
132         绝缘层(第2绝缘层) 
134         导体层 
140         导线 
150         密封树脂 
E           导电体 
F1          绝缘层(第1绝缘层) 
F2          绝缘层 
F3          绝缘层 
F4          绝缘层 
S           间隙 
S1、S2、S3  上表面 
W           金属导线。 

Claims (6)

1.一种半导体装置，其特征在于包含：多根引线，包括内引线及外引线；
半导体芯片，设置在所述多根引线上；
间隔件，介于所述半导体芯片的背面的一部分与所述多根引线之间，在所述半导体芯片的背面与所述多根引线之间形成间隙；
导线，设置在所述间隙，且在所述半导体芯片的背面下，将所述多根引线中与I/O信号用引线相邻的电源用引线的内引线间、接地用引线的内引线间、及控制信号用引线的内引线间的至少一个以上的内引线间以跨越其他内引线的方式电连接；以及
第1绝缘层，设置在所述半导体芯片的背面与所述导线之间；且
连接着所述导线的内引线的上表面与所述半导体芯片的背面的距离短于被连接着所述导线的内引线所夹的内引线的上表面与所述半导体芯片的背面的距离。
2.一种半导体装置，其特征在于包含：多根引线，包括内引线及外引线；
半导体芯片，设置在所述多根引线上；
间隔件，介于所述半导体芯片与所述多根引线之间，在所述半导体芯片的背面与所述多根引线之间形成间隙；
导线，设置在所述间隙，且在所述半导体芯片的背面下将所述内引线间电性连接；以及
第1绝缘层，设置在所述半导体芯片与所述导线之间。
3.根据权利要求2所述的半导体装置，其特征在于：所述导线是将所述多根引线中的电源用引线的内引线间、接地用引线的内引线间、及控制信号用引线的内引线间的至少一个以上的内引线间电连接。
4.根据权利要求2或3所述的半导体装置，其特征在于：所述导线跨越其他内引线而将所述内引线间电连接。
5.根据权利要求2或3所述的半导体装置，其特征在于：连接着所述导线的内引线的上表面与所述半导体芯片的背面的距离短于被连接着所述导线的内引线所夹的内引线的上表面与所述半导体芯片的背面的距离。
6.根据权利要求2或3所述的半导体装置，其特征在于：所述间隔件包括第2绝缘层，且
设置在所述半导体芯片的背面的一部分。
CN201410453249.8A 2013-12-26 2014-09-05 半导体装置 Pending CN104752413A (zh)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030038374A1 (en) * 2001-08-27 2003-02-27 Shim Jong Bo Multi-chip package (MCP) with spacer
US20110210432A1 (en) * 2010-03-01 2011-09-01 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
CN102891136A (zh) * 2011-07-18 2013-01-23 三星电子株式会社 半导体封装及其形成方法
US20130200514A1 (en) * 2012-02-08 2013-08-08 Samsung Electronics Co., Ltd. Semiconductor packages and methods of manufacturing the same
CN104051418A (zh) * 2013-03-15 2014-09-17 株式会社东芝 半导体装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030038374A1 (en) * 2001-08-27 2003-02-27 Shim Jong Bo Multi-chip package (MCP) with spacer
US20110210432A1 (en) * 2010-03-01 2011-09-01 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
CN102891136A (zh) * 2011-07-18 2013-01-23 三星电子株式会社 半导体封装及其形成方法
US20130200514A1 (en) * 2012-02-08 2013-08-08 Samsung Electronics Co., Ltd. Semiconductor packages and methods of manufacturing the same
CN104051418A (zh) * 2013-03-15 2014-09-17 株式会社东芝 半导体装置

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