TWI543317B - Semiconductor device - Google Patents

Semiconductor device Download PDF

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TWI543317B
TWI543317B TW103122856A TW103122856A TWI543317B TW I543317 B TWI543317 B TW I543317B TW 103122856 A TW103122856 A TW 103122856A TW 103122856 A TW103122856 A TW 103122856A TW I543317 B TWI543317 B TW I543317B
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lead
leads
semiconductor wafer
semiconductor device
semiconductor
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TW201526185A (zh
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Hitoshi Ishii
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Toshiba Kk
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/48147—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked with an intermediate bond, e.g. continuous wire daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Description

半導體裝置
[相關申請案]
本申請案係享受將日本專利申請案2013-269434號(申請日：2013年12月26日)作為基礎申請案之優先權。本申請案係藉由參照該基礎申請案而包含基礎申請案之全部內容。
本發明係關於一種半導體裝置。
隨著半導體裝置之高速化，變得容易受到電源(Vcc)或接地(Vss)之電位變動之影響。尤其是，資料之I/O(Input/Output，輸入輸出)信號受到電源、接地、或該兩者之電位變動之影響，而造成於I/O信號上升/下降部分之偏差變大。因此，為了使電源或接地之電位穩定化(強化)或使電源-接地間之電感降低，進行藉由金屬導線將電源用引線間或接地(ground)用引線間電性連接之操作。又，為了提高半導體裝置之通用性，進行變更控制信號或I/O信號等內引線之排列順序與外引線之排列順序之操作。此情形時，於封裝體內，利用中繼用之金屬導線將引線彼此連接，藉此改變電極墊之排列順序與外引線之排列順序，上述中繼用之金屬導線係以跨越位於引線彼此之間之引線之方式設置。
又，近年來，半導體裝置之小型化、高密度化不斷發展。例如有於封裝體內積層半導體晶片而得之半導體裝置或使半導體晶片大型化而得之半導體裝置。然而，於此種半導體裝置中，半導體晶片所佔 據之區域變大(變寬)，故而難以確保於封裝體內設置金屬導線之空間。又，若欲確保於封裝體內設置金屬導線之空間，則封裝體會變大。
如上所述，尋求一種小型化、高密度化發展之半導體裝置，其可將內引線間連接。
本發明係提供一種小型化、高密度化發展之半導體裝置，其可將內引線間連接。
實施形態之半導體裝置包含：複數根引線，其等包括內引線及外引線；半導體晶片，其設置於複數根引線上；間隔件，其介於半導體晶片與複數根引線之間，於半導體晶片之背面與複數根引線之間形成間隙；導線，其設置於間隙，且於半導體晶片之背面下將內引線間電性連接；及第1絕緣層，其設置於上述半導體晶片與上述導線之間。
100‧‧‧半導體裝置
110‧‧‧引線基板
111‧‧‧引線
111A‧‧‧內引線
111B‧‧‧外引線
111C‧‧‧凹部
121~124‧‧‧半導體晶片
121P~124P‧‧‧電極墊
121R~124R‧‧‧背面
130‧‧‧間隔件
131‧‧‧黏著層
132‧‧‧絕緣層(第2絕緣層)
134‧‧‧導體層
140‧‧‧導線
150‧‧‧密封樹脂
D1‧‧‧高度
D2、D3‧‧‧距離
E‧‧‧導電體
F1‧‧‧絕緣層(第1絕緣層)
F2、F3、F4‧‧‧絕緣層
S‧‧‧間隙
S1、S2、S3‧‧‧上表面
S101~S107‧‧‧步驟
W‧‧‧金屬導線
圖1係表示第1實施形態之半導體裝置之俯視圖。
圖2係表示第1實施形態之半導體裝置之放大剖面圖。
圖3係實施形態之半導體裝置之局部俯視圖。
圖4係線段X-X處之剖面圖。
圖5係表示實施形態之半導體裝置之製造方法之流程圖。
(第1實施形態)
圖1係實施形態之半導體裝置100之俯視圖。圖2係實施形態之半導體裝置100之局部放大剖面圖。於本實施形態中，半導體裝置100係TSOP(Thin Small Outline Packeage，薄型小尺寸封裝)型之半導體裝置。
如圖1、圖2所示，半導體裝置100包括引線基板110、半導體晶片121~124、間隔件130、導線140、密封樹脂150及絕緣層F1~F4。再者，於圖1中，以實線而非鏈線記載利用密封樹脂150進行密封之半導體晶片121~124、間隔件130及導線140。
引線基板110具有複數根引線111。對於各引線111，使用導電性優異之金屬材料、例如銅(Cu)或鐵(Fe)、鎳(Ni)。各引線111具有：內引線111A，其被密封於密封樹脂150內；及外引線111B，其自密封樹脂150露出。內引線111A主要作為與半導體晶片121~124之電極墊之連接部發揮功能。外引線111B作為外部連接端子發揮功能。再者，複數根引線111係利用絕緣性之固定膠帶(例如聚醯亞胺(Polyimide))加以固定，以使得位置不偏移。
各引線111包括包含電源用(Vcc)引線、接地用(Vss)引線、控制信號用引線、及輸入輸出(I/O)用引線之複數根引線。此處，於控制信號用引線中，包含晶片賦能(CE)、寫入賦能(WE)、引線賦能(RE)、指令鎖定賦能(CLE)、位址閂賦能(ALE)、寫入保護(WP)、就緒/忙碌(R/B)、資料選通信號(DQS)等之引線。
再者，各引線之排列順序係根據供搭載半導體裝置100之封裝板之規格等而有所不同。
半導體晶片121~124例如為NAND(NOT-AND，反及)型快閃記憶體等記憶元件及其控制器元件。於半導體晶片121~124之一邊側，以沿其一邊排列之方式分別形成有複數個電極墊121P~124P。各半導體晶片121~124係以沿一邊側形成之電極墊121P~124P露出之方式呈階梯狀積層於引線基板110上。
於各半導體晶片121~124之背面121R~124R，配置有絕緣層F1~F4。絕緣層F1~F4兼作為黏著層，絕緣層F1~F4例如為晶粒黏著膜(Die Attach Film)(接著劑膜)。作為絕緣層F1~F4之具體之材料，例 如使用以聚醯亞胺樹脂、環氧樹脂、丙烯酸系樹脂等為主成分之熱硬化性或光硬化性之材料。各半導體晶片122~124係藉由絕緣層F1~F3而接著於各半導體晶片121~123上。
絕緣層F1(第1絕緣層)係配置於半導體晶片121之背面121R，且覆蓋半導體晶片121之背面121R整體。意即，絕緣層F1位於半導體晶片121之背面121R與導線140之間，故半導體晶片121與間隔件130及導線140絕緣。藉此，可防止動作時半導體晶片121與導線140接觸而造成電性短路。
再者，於圖2中，積層有4片半導體晶片。然而，積層之半導體晶片之片數並不限定於4片。半導體晶片之片數只要1片以上即可。藉由呈階梯狀積層而露出之半導體晶片121~124之電極墊121P~124P，係藉由Au導線或Cu導線等金屬導線W而與引線111之內引線111A電性連接。
間隔件130係介於引線基板110與最下層之半導體晶片121之背面121R之間。間隔件130係於引線基板110與最下層之半導體晶片121之背面121R之間形成間隙S。間隙S之高度D1較佳為70μm以上。再者，若間隙S之高度D1過高，則半導體裝置100會變厚。因此，間隙S之高度D1較佳為100μm以下。
間隔件130包括黏著層131及絕緣層(第2絕緣層)132。黏著層131例如使用以聚醯亞胺樹脂、環氧樹脂、丙烯酸系樹脂等為主成分之熱硬化性或光硬化性之材料。又，絕緣層132使用絕緣性之材料、例如聚醯亞胺樹脂。
再者，於圖1中，於半導體晶片121之背面121R與引線基板110之間，存在6個間隔件130。然而，間隔件130只要可確保設置下述導線140之空間即可。因此，設置間隔件130之位置並不限定於圖1所示之位置。例如亦可將間隔件130配置於半導體晶片121之背面121R之四 角。
導線140例如為使用導電性優異之金(Au)、銅(Cu)、鋁(Al)或該等之合金之金屬導線。導線140將內引線111A間電性連接。於本實施形態中，導線140係於最下層之半導體晶片121之背面121R下，將電源用(Vcc)引線之內引線111A間、接地用(Vss)引線之內引線111A間及控制信號用引線之內引線111A間之至少1個以上之內引線111A間電性連接。
密封樹脂150係將引線基板110、半導體晶片121~124、間隔件130、導線140及絕緣層F1~F4密封。再者，各引線111之外引線111B係於露出之狀態下以密封樹脂150密封。
接下來，就利用半導體裝置100之導線140之內引線111A間之連接，更詳細地進行說明。圖3係半導體裝置100之局部俯視圖。圖4係圖3之線段X-X處之剖面圖。於圖3、圖4中，表示利用導線140將電源用(Vcc)引線之內引線111A間及接地用(Vss)引線之內引線111A間電性連接之例。再者，於圖3中，省略半導體晶片121~124、密封樹脂150及絕緣層F1~F4之圖示。又，將金屬導線W以鏈線表示至中途為止。於圖4中，省略間隔件130及密封樹脂150之圖示。
如圖3所示，導線140係以跨越其他內引線111A之狀態，將電源用(Vcc)引線之內引線111A間及接地用(Vss)引線之內引線111A間電性連接。再者，於圖3所示之例中，導線140跨越輸入輸出(I/O)用引線。於輸入輸出(I/O)用引線之附近，容易受到電源(Vcc)或接地(Vss)之電位之影響。因此，較佳為如圖3所示，將配置於輸入輸出(I/O)用之引線之周圍之電源用(Vcc)引線及接地用(Vss)引線之內引線111A間電性連接。然而，導線140亦可跨越其他引線、例如控制信號用引線。
又，如圖3所示，於夾於藉由導線140而電性連接之電源用(Vcc)引線及接地用(Vss)引線之內引線111A間之輸入輸出(I/O)用引線之內 引線111A，形成有凹部111C。再者，如圖3所示，於該半導體裝置100中，於導線140所跨越之區域形成凹部111C。
因此，如圖4所示，連接有導線140之電源用(Vcc)引線及接地用(Vss)引線之內引線111A之上表面S1、S2與半導體晶片121之背面121R之距離D2，短於由連接有導線140之電源用(Vcc)引線及接地用(Vss)引線之內引線111A所夾之輸入輸出(I/O)用引線之內引線111A之上表面S3與半導體晶片121之背面121R之距離D3。再者，距離D2係與距離D1相同之距離。
意即，藉由形成凹部111C，而使由利用導線140而連接之內引線111A所夾之內引線111A之上表面之位置，低於利用導線140而連接之內引線111A之上表面。因此，可減少導線140與作為連接對象之內引線111A以外之內引線111A接觸之虞。又，藉由形成凹部111C，內引線111A之上表面與半導體晶片121之背面121R之距離變長。因此，可減少半導體晶片121與形成有凹部111C之內引線111A之寄生電容。
再者，內引線111A之凹部111C可藉由乾式蝕刻或濕式蝕刻而形成。又，亦可對內引線111A施加壓力，而於上下方向將其壓扁。藉由壓扁，內引線111A之厚度變薄而可形成凹部111C(壓印加工)。又，亦可藉由壓下加工使內引線111A向下方彎折而形成凹部111C。壓印加工或壓下加工可抑制內引線111A之截面積之減少。因此，可抑制形成有凹部111C之內引線111A之電阻增加。
再者，於圖3、圖4所示之例中，為使電源(Vcc)及接地(Vss)之電位穩定化(強化)或為使電源-接地間之電感降低，利用導線140將電源用(Vcc)引線之內引線111A間及接地用(Vss)引線之內引線111A間電性連接。然而，於為了變更內引線111A之排列順序與外引線111B之排列順序之目的下，亦可利用導線140將控制信號用引線及/或輸入輸出(I/O)用引線之內引線111A間電性連接。
(半導體裝置100之製造)
圖5係表示半導體裝置100之製造方法之流程圖。以下，參照圖1~圖5，就半導體裝置100之製造方法進行說明。
於引線基板110之特定位置安裝間隔件130(步驟S101)。間隔件130之安裝亦可於引線基板110之製造步驟之中途，於壓下加工或壓印加工、引線之前端之切斷加工之前進行。
接下來，利用導線140將引線基板110之引線111中之所期望之引線111之內引線111A間電性連接(步驟S102)。對於導線140之連接，使用既有之打線裝置。
接下來，於半導體晶片121~124之背面121R~124R配置絕緣層F1~F4(步驟S103)。對於絕緣層F1~F4，使用晶粒黏著膜等接著劑膜。
接下來，於間隔件130上呈階梯狀積層半導體晶片121~124及絕緣層F1~F4(步驟S104)。
接下來，利用金屬導線W將所積層之半導體晶片121~124之電極墊121P~124P及引線基板110之內引線111A電性連接(步驟S105)。又，對於金屬導線W之連接，使用既有之打線裝置。
接下來，利用密封樹脂150將引線基板110、半導體晶片121~124、間隔件130、導線140及金屬導線W等密封(步驟S106)。
接下來，進行自密封樹脂150露出之外引線111B之彎曲加工及切斷加工等(步驟S107)。又，亦可於將間隔件130貼附於半導體晶片121之背面之後，將半導體晶片121安裝在引線基板110上。
如上所述，半導體裝置100包括於半導體晶片121之背面121R與複數根引線111之間形成間隙S之間隔件130。而且，於該間隙S中，藉由導線140將內引線111A間電性連接。
因此，於在封裝半導體晶片121~124之區域之外側無用於設置 導線140之空間之情形時，亦可藉由導線140將內引線111A間電性連接。
又，使由利用導線140而連接之內引線111A所夾之內引線111A之上表面之位置，低於利用導線140而連接之內引線111A之上表面。因此，可減少導線140與作為連接對象之內引線111A以外之內引線111A接觸之虞。進而，藉由形成凹部111C，而使內引線111A之上表面與半導體晶片121之背面121R之距離變長，從而於半導體晶片121之背面121R與內引線111A間設置絕緣層F1。因此，可減少半導體晶片121與形成有凹部111C之內引線111A之寄生電容。
進而，於藉由壓印加工或壓下加工形成內引線111A之凹部111C之情形時，可抑制內引線111A之截面積之減少。因此，可抑制形成有凹部111C之內引線111A之電阻增加。
就本發明之若干實施形態進行了說明，但該等實施形態係作為示例而提出者，並非意欲限定發明之範圍。該等新穎之實施形態能夠以其他各種形態實施，可於不脫離發明之主旨之範圍內進行各種省略、替換、變更。該等實施形態及其變化包含於發明之範圍或主旨中，並且包含於申請專利範圍中所記載之發明及其均等範圍內。
100‧‧‧半導體裝置
110‧‧‧引線基板
111A‧‧‧內引線
111B‧‧‧外引線
121~124‧‧‧半導體晶片
121P‧‧‧電極墊
130‧‧‧間隔件
140‧‧‧導線
150‧‧‧密封樹脂
W‧‧‧金屬導線

Claims (6)

  1. 一種半導體裝置，其包含：複數根引線，其等包括內引線及外引線；半導體晶片，其設置於上述複數根引線上；間隔件，其介於上述半導體晶片之背面之一部分與上述複數根引線之間，於上述半導體晶片之背面與上述複數根引線之間形成間隙；導線，其設置於上述間隙，且於上述半導體晶片之背面下，將上述複數根引線中之相鄰於I/O信號用引線之電源用引線之內引線間、接地用引線之內引線間及控制信號用引線之內引線間之至少1個以上之內引線間以跨越其他內引線之方式電性連接；及第1絕緣層，其設置於上述半導體晶片之背面與上述導線之間；且連接有上述導線之內引線之上表面與上述半導體晶片之背面之距離係短於由連接有上述導線之內引線所夾之內引線之上表面與上述半導體晶片之背面之距離。
  2. 一種半導體裝置，其包含：複數根引線，其等包括內引線及外引線；半導體晶片，其設置於上述複數根引線上；間隔件，其介於上述半導體晶片與上述複數根引線之間，於上述半導體晶片之背面與上述複數根引線之間形成間隙；導線，其設置於上述間隙，且於上述半導體晶片之背面下將上述內引線間電性連接；及第1絕緣層，其設置於上述半導體晶片與上述導線之間。
  3. 如請求項2之半導體裝置，其中上述導線係將上述複數根引線中之電源用引線之內引線間、接地用引線之內引線間及控制信號用引線之內引線間之至少1個以上之內引線間電性連接。
  4. 如請求項2或3之半導體裝置，其中上述導線係跨越其他內引線而將上述內引線間電性連接。
  5. 如請求項2或3之半導體裝置，其中連接有上述導線之內引線之上表面與上述半導體晶片之背面之距離係短於由連接有上述導線之內引線所夾之內引線之上表面與上述半導體晶片之背面之距離。
  6. 如請求項2或3之半導體裝置，其中上述間隔件包括第2絕緣層，且設置於上述半導體晶片之背面之一部分。
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