JP2005252295A - 半導体装置およびその製造方法 - Google Patents
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/32257—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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Abstract
【解決手段】極薄厚の半導体素子10と、その周囲に配置された外部電極11と、それらの間を接続した金属細線12と、外囲を絶縁性樹脂で外形が直方体を構成するように封止した封止樹脂13とより構成され、半導体素子10と外部電極11の底面と上面が封止樹脂13の底面と上面で露出され、半導体素子10の上面と外部電極11の上面の位置が略同一位置である半導体装置であり、底面側からの電極部材、半導体素子を研削し上面側から封止樹脂を研削することによって極薄厚を実現した半導体装置である。
【選択図】図13
Description
成体どうしを分離させて底面に凹部を有した外部電極を構成するとともに、前記構成した外部電極の底面および前記半導体素子の底面を樹脂より露出させる工程とよりなる半導体装置の製造方法である。
工やプレス加工により行う。
れた封止樹脂13の底面で露出するとともに、外部電極11の突起19の上面が封止樹脂13の上面から露出している半導体装置であり、半導体素子10の上面と外部電極11の突起段差部20の上面の位置が略同一位置にある半導体装置である。
封止樹脂13の底面で露出し、外部電極11の突起19の上面が封止樹脂13の上面から露出している半導体装置である。また本実施形態の半導体装置では、半導体素子10の上面と外部電極11の突起段差部20の上面の位置が略同一位置である。さらに本実施形態の半導体装置は、外部電極11の底面には凹部21が設けられ、別の半導体装置の上面突起が嵌合してスタック構造可能な構造を有している。
れた封止樹脂13の底面で露出するとともに、外部電極11の突起19の上面が封止樹脂13の上面から突出している半導体装置であり、半導体素子10の上面と外部電極11の突起段差部20の上面の位置が略同一位置にある半導体装置である。
2 ダイパッド部
3 吊りリード部
4 インナーリード部
5 アウターリード部
6 タイバー部
7 半導体素子
8 金属細線
9 封止樹脂
10 半導体素子
11 外部電極
12 金属細線
13 封止樹脂
13a くぼみ
14 フレーム本体
15 電極構成体
16 素子収納部
17 接着剤
18 研削部材
19 突起
20 突起段差部
21 凹部
Claims (5)
- 半導体素子と、
前記半導体素子の周囲に配置され、上方に突起段差部を有した突起を備えた外部電極と、
前記外部電極の前記突起段差部の表面と前記半導体素子の電極とを電気的に接続した細線と、
前記半導体素子、外部電極、細線の外囲を外形が直方体を構成するように封止した封止樹脂とより構成され、
前記半導体素子および外部電極の底面が前記封止樹脂の底面から露出し、前記半導体素子の上面と前記外部電極の突起段差部の上面の位置が略同一位置であり、
前記外部電極の突起が封止樹脂の上面に露出していることを特徴とする半導体装置。 - 導電性の板材よりなるフレーム本体と、前記フレーム本体面内に突出して設けられ、その上部に突起段差部を構成して突出した突起を有した複数の電極構成体と、前記電極構成体に包囲されるように設けられた素子収納部とより構成されたフレーム部材を用意する工程と、
前記用意したフレーム部材の前記素子収納部に対して、半導体素子を固定する工程と、
固定した半導体素子の電極と前記電極構成体の突起段差部の上面とを細線により電気的に接続する工程と、
前記半導体素子が固定され、前記細線で結線されたフレーム部材の上面側を樹脂により封止する工程と、
樹脂封止後のフレーム部材に対して、その底面のフレーム本体を研削部材により研削し、底面のフレーム本体を除去し、前記電極構成体どうしを分離させて外部電極を構成するとともに、前記構成した外部電極の底面および前記半導体素子の底面を樹脂より露出させる工程と、
底面を研削したフレーム部材に対して、その上面側を研削部材により研削して封止樹脂を切削し、前記突起の上面を封止樹脂の上面から露出させる工程とよりなることを特徴とする半導体装置の製造方法。 - 半導体素子と、
前記半導体素子の周囲に配置され、上方に突起段差部を有した突起を備え、底面に凹部を有した外部電極と、
前記外部電極の前記突起段差部の表面と前記半導体素子の電極とを電気的に接続した細線と、
前記半導体素子、外部電極、細線の外囲を外形が直方体を構成するように封止した封止樹脂とより構成され、
前記半導体素子および外部電極の底面が前記封止樹脂の底面から露出し、前記半導体素子の上面と前記外部電極の突起段差部の上面の位置が略同一位置であり、
前記外部電極の突起が封止樹脂の上面に突出していることを特徴とする半導体装置。 - 導電性の板材よりなるフレーム本体と、前記フレーム本体面内に突出して設けられ、その上部に突起段差部を構成して突出した突起と底面に凹部とを有した複数の電極構成体と、前記電極構成体に包囲されるように設けられた素子収納部とより構成されたフレーム部材を用意する工程と、
前記用意したフレーム部材の前記素子収納部に対して、半導体素子を固定する工程と、
固定した半導体素子の電極と前記電極構成体の突起段差部の上面とを細線により電気的に接続する工程と、
前記半導体素子が固定され、前記細線で結線されたフレーム部材の上面側を前記電極構成体の突起の上部を突出させて樹脂により封止する工程と、
樹脂封止後のフレーム部材に対して、その底面のフレーム本体を研削部材により研削し、底面のフレーム本体を除去し、前記電極構成体どうしを分離させて底面に凹部を有した外部電極を構成するとともに、前記構成した外部電極の底面および前記半導体素子の底面を樹脂より露出させる工程とよりなることを特徴とする半導体装置の製造方法。 - 樹脂封止後のフレーム部材に対して、その底面のフレーム本体を研削部材により研削し、底面のフレーム本体を除去し、電極構成体どうしを分離させて底面に凹部を有した外部電極を構成するとともに、構成した外部電極の底面および半導体素子の底面を樹脂より露出させる工程の後、前記外部電極の前記凹部に対して、各々対応するように別の半導体装置の突出した外部電極の突起を嵌合してスタック構造を形成する工程と、前記スタック形成後に個々に分割することにより、積層型の半導体装置を得る工程とをさらに備えたことを特徴とする請求項4に記載の半導体装置の製造方法。
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2009105335A (ja) * | 2007-10-25 | 2009-05-14 | Spansion Llc | 半導体装置及びその製造方法 |
JP2016225430A (ja) * | 2015-05-29 | 2016-12-28 | 日立マクセル株式会社 | 半導体装置用基板及びその製造方法、半導体装置及びその製造方法 |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2009105335A (ja) * | 2007-10-25 | 2009-05-14 | Spansion Llc | 半導体装置及びその製造方法 |
JP2016225430A (ja) * | 2015-05-29 | 2016-12-28 | 日立マクセル株式会社 | 半導体装置用基板及びその製造方法、半導体装置及びその製造方法 |
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