JP5149694B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP5149694B2 JP5149694B2 JP2008128361A JP2008128361A JP5149694B2 JP 5149694 B2 JP5149694 B2 JP 5149694B2 JP 2008128361 A JP2008128361 A JP 2008128361A JP 2008128361 A JP2008128361 A JP 2008128361A JP 5149694 B2 JP5149694 B2 JP 5149694B2
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- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
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- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
樹脂部 4、24
リードフレーム 6、26、34、38
第1半導体チップ 10
外部接続端子 16
第2半導体チップ 18
第3半導体チップ 20
半田 30
第4半導体チップ 36
半導体装置 100、300、500、600、800
上部半導体装置 200、400、700
Claims (6)
- 絶縁性基板と、
前記絶縁性基板の上面に実装された第1半導体チップと、
前記第1半導体チップと電気的に接続されたリードフレームと、
前記絶縁性基板の下面に設けられ、前記第1半導体チップと電気的に接続された外部接続端子と、
前記絶縁性基板の下面と前記リードフレームの上面とが露出するように、前記絶縁性基板と前記半導体チップと前記リードフレームとを封止する樹脂部と、
第2半導体チップ、及び、前記第2半導体チップと電気的に接続され且つ下面が露出した端子を有する上部半導体装置と、
を具備し、
前記上部半導体装置は、前記リードフレームの上面と前記端子の下面とが接続されるように、積層されており、
前記樹脂部の上面が前記リードフレームの上面と実質的に同一レベルとなるように形成された、
ことを特徴とする半導体装置。 - 前記リードフレームの上面と前記端子の下面とは、半田を介して接続されていることを特徴とする請求項1記載の半導体装置。
- 前記リードフレームの側面は前記樹脂部から露出していることを特徴とする請求項1又は2記載の半導体装置の製造方法。
- 絶縁性基板の上面に第1半導体チップを実装する工程と、
前記第1半導体チップとリードフレームとを電気的に接続する工程と、
前記絶縁性基板の下面と前記リードフレームの上面とが露出するように、前記前記絶縁性基板と前記第1半導体チップと前記リードフレームとを樹脂部により封止する工程と、
前記絶縁性基板の下面に、前記第1半導体チップと電気的に接続されるように、外部接続端子を設ける工程と、
第2半導体チップ、及び、前記第2半導体チップと電気的に接続され且つ下面が露出した端子を有する上部半導体装置を、前記リードフレームの上面と前記端子の下面とが接続されるように、積層する工程と、
を有し、
樹脂部により封止する工程においては、前記樹脂部の上面が前記リードフレームの上面と実質的に同一レベルとなるように形成する、
ことを特徴とする半導体装置の製造方法。 - 前記上部半導体装置を積層する工程は、前記リードフレームの上面と前記端子の下面とが半田を介して接続されるように、積層する工程であることを特徴とする請求項4記載の半導体装置の製造方法。
- 前記樹脂部により封止する工程は、前記リードフレームの側面が露出するように封止する工程であることを特徴とする請求項4又は5記載の半導体装置の製造方法。
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Application Number | Priority Date | Filing Date | Title |
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JP2008128361A JP5149694B2 (ja) | 2008-05-15 | 2008-05-15 | 半導体装置及びその製造方法 |
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JP2009277923A JP2009277923A (ja) | 2009-11-26 |
JP5149694B2 true JP5149694B2 (ja) | 2013-02-20 |
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JP2008128361A Expired - Fee Related JP5149694B2 (ja) | 2008-05-15 | 2008-05-15 | 半導体装置及びその製造方法 |
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Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2924847B2 (ja) * | 1997-04-11 | 1999-07-26 | 日本電気株式会社 | 半導体パッケージ |
KR100302593B1 (ko) * | 1998-10-24 | 2001-09-22 | 김영환 | 반도체패키지및그제조방법 |
JP3600138B2 (ja) * | 2000-09-05 | 2004-12-08 | シャープ株式会社 | 半導体装置 |
JP3941877B2 (ja) * | 2005-11-16 | 2007-07-04 | 国立大学法人九州工業大学 | 両面電極パッケージ及びその製造方法 |
JP5217291B2 (ja) * | 2006-08-04 | 2013-06-19 | 大日本印刷株式会社 | 樹脂封止型半導体装置とその製造方法、半導体装置用基材、および積層型樹脂封止型半導体装置 |
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