JP2013219183A - 積層型半導体装置、プリント回路板及び積層型半導体装置の製造方法 - Google Patents
積層型半導体装置、プリント回路板及び積層型半導体装置の製造方法 Download PDFInfo
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Abstract
【解決手段】第1の半導体パッケージ101の第1の配線基板105には、外部接続端子190を介してメイン基板180のパッド181にそれぞれ接続される複数のパッド106が形成されている。第2の半導体パッケージ102の第2の半導体チップ111は第1の封止樹脂115で封止されている。第1の配線基板105と第2の配線基板113とは、金属ワイヤ121により電気的に接続されている。第1の半導体チップ103、金属ワイヤ121及び第2の半導体パッケージ102は、第2の封止樹脂122で封止されている。第1の半導体パッケージ101と第2の半導体パッケージ102との間には、封止樹脂115,122よりも線膨張係数が大きい板部材123が設けられている。
【選択図】図2
Description
図1は、本発明の第1実施形態に係るプリント回路板の積層型半導体装置の概略構成を示す説明図であり、図1(a)は積層型半導体装置の平面図、図1(b)は積層型半導体装置の底面図である。図2は、図1(a)のA−A線に沿う断面図である。
次に、本発明の第2実施形態に係るプリント回路板の積層型半導体装置について説明する。図6は、本発明の第2実施形態に係るプリント回路板の積層型半導体装置の概略構成を示す説明図であり、図6(a)は積層型半導体装置の平面図、図6(b)は積層型半導体装置の底面図である。なお、図6に示す本第2実施形態の積層型半導体装置おいて上記第1実施形態の積層型半導体装置と同様の構成については、同一符号を付して説明を省略する。
次に、本発明の第3実施形態に係るプリント回路板の積層型半導体装置について説明する。図7は、本発明の第3実施形態に係るプリント回路板の積層型半導体装置の概略構成を示す説明図であり、図7(a)は積層型半導体装置の平面図、図7(b)は積層型半導体装置の底面図である。なお、図7に示す本第3実施形態の積層型半導体装置おいて上記第1実施形態の積層型半導体装置と同様の構成については、同一符号を付して説明を省略する。
次に、本発明の第4実施形態に係るプリント回路板の積層半導体装置の製造方法について説明する。図8及び図9は、本発明の第4実施形態にかかるプリント回路板400の積層型半導体装置450の製造工程の一例を示す説明図である。図8(a)は、積層型半導体装置450の製造工程における第1の固着工程を示す説明図である。図8(b)は、積層型半導体装置450の製造工程における第2の固着工程を示す説明図である。図8(c)は、積層型半導体装置450の製造工程におけるワイヤボンディング工程を示す説明図である。図8(d)は、積層型半導体装置450の製造工程における封止工程を示す説明図である。図9(a)は、積層型半導体装置450の製造工程における外部接続端子取付工程を示す説明図である。図9(b)は、積層型半導体装置450の製造工程における個片化工程を示す説明図である。図9(c)は、製造された積層型半導体装置450をメイン基板180に搭載する搭載工程を示す説明図である。上記第1実施形態では、第1の半導体パッケージが複数連結されたシート状の半導体装置を用いて積層型半導体装置を製造したが、本第5実施形態では、板部材が複数連結された状態のシート状板材を用い、第1の半導体パッケージは個片化されたものを用いている。
次に、本発明の第5実施形態に係るプリント回路板の積層型半導体装置について説明する。図10は、本発明の第5実施形態に係るプリント回路板の積層型半導体装置の概略構成を示す説明図であり、図10(a)は積層型半導体装置の平面図、図10(b)は図10(a)のB−B線に沿う断面図である。なお、図10に示す本第5実施形態の積層型半導体装置おいて上記第1実施形態の積層型半導体装置と同様の構成については、同一符号を付して説明を省略する。
Claims (9)
- 第1の半導体素子、及び一方の平面に前記第1の半導体素子が実装され、他方の平面にプリント配線板に電気的に接続される導体からなるパッドが複数形成された第1の配線基板を有する第1の半導体パッケージと、
第2の半導体素子、一方の平面に前記第2の半導体素子が実装された第2の配線基板、及び前記第2の半導体素子を封止する第1の封止樹脂を有する第2の半導体パッケージと、
前記第1の配線基板と前記第2の配線基板とを電気的に接続する金属ワイヤと、
前記第1の半導体素子、前記金属ワイヤ及び前記第2の半導体パッケージを封止する第2の封止樹脂と、
前記第1の半導体パッケージと前記第2の半導体パッケージとの間に介在され、前記第1及び第2の封止樹脂よりも線膨張係数が大きい板部材と、を備えたことを特徴とする積層型半導体装置。 - 前記板部材は、前記第1の配線基板の平面に垂直な方向から見て、前記第1の配線基板の面積よりも小面積であり、且つ前記第1の配線基板の領域内に配置された板本体と、前記板本体から、前記複数のパッドのうち前記第1の配線基板の隅部に配置された隅部パッドの位置まで突出する突出片と、を有することを特徴とする請求項1に記載の積層型半導体装置。
- 前記第2の配線基板は、前記第1の配線基板の平面に垂直な方向から見て、前記第1の配線基板よりも小面積であり、且つ前記第1の配線基板の領域内に配置され、
前記板本体は、前記第1の配線基板の平面に垂直な方向から見て、前記第2の配線基板の面積以下の面積であり、且つ前記第2の配線基板の領域内に配置されていることを特徴とする請求項2に記載の積層型半導体装置。 - 前記突出片は、前記第1の配線基板の平面に垂直な方向から見て、前記隅部パッドの外形を覆う大きさに形成された先端部と、前記板本体と前記先端部とを連結し、前記先端部よりも幅狭に形成された連結部とを有することを特徴とする請求項2又は3に記載の積層型半導体装置。
- 前記突出片は、前記板本体よりも厚く形成されていることを特徴とする請求項2乃至4のいずれか1項に記載の積層型半導体装置。
- 請求項1乃至5のいずれか1項に記載の積層型半導体装置と、
前記積層型半導体装置が実装されたプリント配線板と、を備えたことを特徴とするプリント回路板。 - 第1の半導体素子、及び一方の平面に前記第1の半導体素子が実装され、他方の平面にプリント配線板に電気的に接続される導体からなるパッドが複数形成された第1の配線基板を有する第1の半導体パッケージと、第2の半導体素子、一方の平面に前記第2の半導体素子が実装された第2の配線基板、及び前記第2の半導体素子を封止する第1の封止樹脂を有する第2の半導体パッケージと、を備えた積層型半導体装置の製造方法において、
前記第1の封止樹脂よりも線膨張係数の大きい板部材を、複数並べて配置した前記第1の半導体パッケージ上に各々供給して、前記各板部材を前記各第1の半導体パッケージにそれぞれ固着する第1の固着工程と、
前記各板部材上に、それぞれ前記第2の半導体パッケージを供給し、前記各第2の半導体パッケージを前記各板部材にそれぞれ固着する第2の固着工程と、
前記各第1の配線基板と前記各第2の配線基板とをそれぞれ金属ワイヤで電気的に接続するワイヤボンディング工程と、
前記各第1の半導体素子、前記各金属ワイヤ及び前記各第2の半導体パッケージを、前記板部材よりも線膨張係数が小さい第2の封止樹脂で一括封止する封止工程と、
前記第2の封止樹脂を切断して個々の積層型半導体装置に個片化する個片化工程と、
を備えたことを特徴とする積層型半導体装置の製造方法。 - 前記各板部材が、前記第1の配線基板の平面に垂直な方向から見て、前記第1の配線基板よりも小面積であり、且つ前記第1の配線基板の領域内に配置される板本体と、前記板本体から、前記複数のパッドのうち前記第1の配線基板の隅部に配置された隅部パッドの位置まで突出する突出片と、を有しており、
前記第1の固着工程では、前記各板部材の板本体を前記各第1の半導体パッケージにそれぞれ固着し、
前記第2の固着工程では、前記各第2の半導体パッケージを前記各板部材の板本体にそれぞれ固着することを特徴とする請求項7に記載の積層型半導体装置の製造方法。 - 前記第1の固着工程では、検査済みの前記複数の第1の半導体パッケージ上に、前記複数の板部材が連結された状態のシート状板材を供給し、
前記個片化工程では、前記第2の封止樹脂と共に前記シート状板材を切断することを特徴とする請求項8に記載の積層型半導体装置の製造方法。
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US13/798,558 US8836102B2 (en) | 2012-04-09 | 2013-03-13 | Multilayered semiconductor device, printed circuit board, and method of manufacturing multilayered semiconductor device |
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Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006502596A (ja) * | 2002-10-08 | 2006-01-19 | チップパック,インク. | 裏返しにされた第二のパッケージを有する積み重ねられた半導体マルチパッケージモジュール |
JP2007281201A (ja) * | 2006-04-06 | 2007-10-25 | Toshiba Corp | 半導体装置 |
JP2008166803A (ja) * | 2006-12-28 | 2008-07-17 | Stats Chippac Ltd | 装着可能な集積回路パッケージインパッケージシステム |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI255536B (en) * | 2005-02-02 | 2006-05-21 | Siliconware Precision Industries Co Ltd | Chip-stacked semiconductor package and fabrication method thereof |
JP4594777B2 (ja) | 2005-03-28 | 2010-12-08 | 株式会社東芝 | 積層型電子部品の製造方法 |
US7728417B2 (en) * | 2005-05-27 | 2010-06-01 | Stats Chippac Ltd. | Integrated circuit package system including shield |
JP2007208159A (ja) * | 2006-02-06 | 2007-08-16 | Hitachi Ltd | 半導体装置 |
US8120156B2 (en) * | 2006-02-17 | 2012-02-21 | Stats Chippac Ltd. | Integrated circuit package system with die on base package |
US7829986B2 (en) * | 2006-04-01 | 2010-11-09 | Stats Chippac Ltd. | Integrated circuit package system with net spacer |
US7989269B2 (en) * | 2008-03-13 | 2011-08-02 | Stats Chippac, Ltd. | Semiconductor package with penetrable encapsulant joining semiconductor die and method thereof |
CN102024710B (zh) * | 2009-09-18 | 2012-08-29 | 展晶科技(深圳)有限公司 | 光电元件的制造方法、封装结构及其封装装置 |
JP2011096865A (ja) * | 2009-10-30 | 2011-05-12 | Sharp Corp | 基板部材、モジュール、電気機器、およびモジュールの製造方法 |
-
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Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006502596A (ja) * | 2002-10-08 | 2006-01-19 | チップパック,インク. | 裏返しにされた第二のパッケージを有する積み重ねられた半導体マルチパッケージモジュール |
JP2007281201A (ja) * | 2006-04-06 | 2007-10-25 | Toshiba Corp | 半導体装置 |
JP2008166803A (ja) * | 2006-12-28 | 2008-07-17 | Stats Chippac Ltd | 装着可能な集積回路パッケージインパッケージシステム |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015012170A (ja) * | 2013-06-28 | 2015-01-19 | キヤノン株式会社 | 積層型半導体装置、プリント回路板及び積層型半導体装置の製造方法 |
JP2019046825A (ja) * | 2017-08-29 | 2019-03-22 | 東芝メモリ株式会社 | 半導体装置 |
JP6991014B2 (ja) | 2017-08-29 | 2022-01-12 | キオクシア株式会社 | 半導体装置 |
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