JP2019046825A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2019046825A JP2019046825A JP2017164556A JP2017164556A JP2019046825A JP 2019046825 A JP2019046825 A JP 2019046825A JP 2017164556 A JP2017164556 A JP 2017164556A JP 2017164556 A JP2017164556 A JP 2017164556A JP 2019046825 A JP2019046825 A JP 2019046825A
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Abstract
Description
CTE1<CTE2<CTE3<CTE4 式1
半導体チップの弾性率をEM1、第1〜第3樹脂層の弾性率をEM2、第1〜第4配線層の弾性率をEM3、および接着剤の弾性率をEM4とすると、式2を満たす。
EM1>EM3>EM2>EM4 式2
CTE1<CTE2<CTE3<CTE4 式1
EM1>EM3>EM2>EM4 式2
従って、パッケージ基板10の熱膨張係数CTE2、CTE3および実装基板60の熱膨張係数CTE4は、半導体チップ20の熱膨張係数CTE1よりも大きい。また、パッケージ基板10の弾性率EM2、EM3および実装基板60の弾性率EM4は、半導体チップ20の弾性率EM1よりも小さい。即ち、パッケージ基板10および実装基板60は、半導体チップ20よりも撓みやすく、歪み応力を吸収し易い。
サンプルP1に対応する半導体装置は、2層配線構造のパッケージ基板10と20μmの厚みを有する接着剤40とを有する。サンプルP1は、P2〜P5の基準となっており、従って、サンプルP1におけるはんだバンプ50の寿命を1としている。後述するように、サンプルP1に対応するパッケージ基板10のソルダレジストの構造は、他のサンプルP2〜P5に対応するパッケージ基板10のソルダレジストの構造と異なる。従って、図3においては、サンプルP1を基準として示しているが、以下、ソルダレジストについて同一構成を有するサンプルP2〜P5について比較する。
TCT試験において、樹脂層および配線層からなる実装基板60は、比較的大きく伸縮するが、シリコン基板からなる半導体チップ20は、あまり伸縮しない。従って、もし、パッケージ基板10や接着剤40の厚みが薄く、あるいは、パッケージ基板10の構造が伸縮し難い構造(例えば、シリコン基板)である場合、実装基板60の伸縮と半導体チップ20の伸縮との差が、比較的大きな歪み応力としてはんだバンプ50に印加される。これは、はんだバンプ50とパッケージ基板10または実装基板60との間の接続部におけるクラックの原因となる。
例えば、樹脂等で構成される実装基板60が温度差によって比較的大きく伸縮する一方で、パッケージ基板10のシリコン基板は温度によって伸縮し難い。このため、実装基板60とパッケージ基板10との間のバンプに歪み応力がかかり、バンプとそれに接続する半導体パッケージの金属電極との間にクラックが生じるおそれがある。この場合、TCTに対する充分な耐性を得ることができず、半導体装置の信頼性を損ねるという問題がある。
これに対し、本実施形態によれば、はんだバンプ50は、配線部分15の表面F15_1だけでなく、側面F15_2にも接触する。これにより、はんだバンプ50と配線部分15との間の物理的な接合強度が上昇し、はんだバンプ50と配線部分15との間のクラックは抑制され得る。
尚、本実施形態による半導体装置を上から見た場合、その寸法は、JEDEC(Joint Electron Device Engineering Council)のMO−276K規格に準拠し得る。例えば、本実施形態の半導体装置を上から見た場合、半導体装置の寸法は、MO−276K規格で規定された、11.5mm×13mm、12mm×16mm、14mm×18mmのいずれかでよい。ただし、これらに限られる必要は無く、半導体装置の寸法は、6mm×7mm、3mm×7.5mm、3mm×8mm、6mm×8mm、7mm×9mm、11mm×11.5mm、6mm×12mm、9mm×12mm、12mm×15mm、12mm×18mm、16mm×20mm、17mm×22mmのいずれでもよい。
本実施形態の半導体装置はその他の規格に準拠するものでもよく、本実施形態に係る半導体装置は種々の大きさの構成に適宜適用可能である。
Claims (8)
- 第1面と前記第1面に対して反対側にある第2面とを有するパッケージ基板と、
前記パッケージ基板の前記第1面上に設けられ、半導体素子を有する半導体チップと、
前記半導体チップと前記パッケージ基板との間に設けられた接着剤と、
前記第2面上に設けられた金属バンプとを備え、
前記パッケージ基板は、第1〜第4配線層と、前記第1配線層と前記第2配線層との間に設けられた第1樹脂層と、前記第2配線層と前記第3配線層との間に設けられた第2樹脂層と、前記第3配線層と前記第4配線層との間に設けられた第3樹脂層と、を備えた積層基板であり、
前記半導体チップの熱膨張係数をCTE1、前記第1〜第3樹脂層の熱膨張係数をCTE2、前記第1〜第4配線層の熱膨張係数をCTE3、および前記接着剤の熱膨張係数をCTE4とすると、式1を満たし、
CTE1<CTE2<CTE3<CTE4 式1
前記半導体チップの弾性率をEM1、前記第1〜第3樹脂層の弾性率をEM2、前記第1〜第4配線層の弾性率をEM3、および前記接着剤の弾性率をEM4とすると、式2を満たす、
EM1>EM3>EM2>EM4 式2
半導体装置。 - 前記金属バンプを介して前記パッケージ基板に電気的に接続される実装基板をさらに備え、
前記実装基板は、複数の配線層と前記複数の樹脂層とを積層した積層基板である、請求項1に記載の半導体装置。 - 前記第1〜第4配線層には、銅、金、銀のいずれかの導電材料が用いられ、
前記第1〜第3樹脂層には、ガラスエポキシ樹脂、フェノール樹脂、ポリテトラフルオロエチレン、ポリイミドのいずれかの絶縁材料が用いられ得、
前記半導体チップは、シリコン基板を有し、
前記実装基板の前記複数の配線層には、銅、金、銀のいずれかの導電材料が用いられ、
前記実装基板の前記樹脂層には、ガラスエポキシ樹脂、フェノール樹脂、ポリテトラフルオロエチレン、ポリイミドのいずれかの絶縁材料が用いられる、請求項1または請求項2に記載の半導体装置。 - 前記パッケージ基板の前記第2面上において、前記バンプの位置に開口を有するように該バンプの周辺に設けられたソルダレジストをさらに備え、
前記ソルダレジストの前記開口の径は、前記第4配線層のうち前記バンプが接続する接続部分の径よりも大きい、請求項1から請求項3のいずれか一項に記載の半導体装置。 - 前記バンプは、前記配線部分の表面および側面に接触している、請求項4に記載の半導体装置。
- 前記ソルダレジストは、前記接続部分に接触しておらず、
前記バンプは、前記ソルダレジストの設けられていない領域に設けられている、請求項4または請求項5に記載の半導体装置。 - 前記接着剤の厚みは、100〜135μmである、請求項1に記載の半導体装置。
- 当該半導体装置を上から見たときの寸法は、JEDEC(Joint Electron Device Engineering Council)のMO−276K規格に準拠する、請求項1から請求項5のいずれか一項に記載の半導体装置。
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