JP4108643B2 - 配線基板及びそれを用いた半導体パッケージ - Google Patents
配線基板及びそれを用いた半導体パッケージ Download PDFInfo
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- JP4108643B2 JP4108643B2 JP2004142133A JP2004142133A JP4108643B2 JP 4108643 B2 JP4108643 B2 JP 4108643B2 JP 2004142133 A JP2004142133 A JP 2004142133A JP 2004142133 A JP2004142133 A JP 2004142133A JP 4108643 B2 JP4108643 B2 JP 4108643B2
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- wiring
- insulating film
- wiring board
- base insulating
- via hole
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H01L2924/097—Glass-ceramics, e.g. devitrified glass
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- H01L2924/1025—Semiconducting materials
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- H01L2924/10253—Silicon [Si]
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- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H01L2924/151—Die mounting substrate
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- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
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- H05K2201/0364—Conductor shape
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- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
- H05K2203/0703—Plating
- H05K2203/0733—Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
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- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
- H05K3/205—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/423—Plated through-holes or plated via connections characterised by electroplating method
Description
(1)厚み方向の熱膨張率が90ppm/K以下
温度がT℃のときの弾性率をDT、温度がT℃のときの破断強度をHTとしたとき
(2)D23≧5GPa
(3)D150≧2.5GPa
(4)(D−65/D150)≦3.0
(5)H23≧140MPa
(6)(H−65/H150)≦2.3
D23≧5GPa:これより小さいものでは、20μm厚配線基板の半導体パッケージ組立時における搬送性などに劣り、実用に供せない。
D150≧2.5GPa:これより小さいものでは、ワイヤーボンディング性が不十分なため、実用に供せない。なお、これを満たすためには、少なくともガラス転移温度150℃以上の耐熱性樹脂を補強繊維に含浸する必要がある。
(D−65/D150)≦3.0:この値が大きいということは、低温と高温における弾性率の変化量が大きいことを意味する。これより大きいものでは、半導体パッケージ組立時における加熱、冷却工程の繰り返しにより、配線基板に歪み応力が加わり、半導体パッケージ自体が沿ってしまうトラブルが発生し、実用に供せない。
H23≧140MPa:これより小さいものでは、20μm厚配線基板の半導体パッケージ組立時における取り扱い性に劣り、実用に供せない。
(H−65/H150)≦2.3:この値が大きいということは、低温と高温における破断強度の変化量が大きいことを意味する。これより大きいものでは、特に高温時における機械的強度に劣ることになり、ワイヤーボンディングなどの半導体パッケージ組立工程で基体絶縁膜に微少ながらもクラックが発生してしまい、実用に供せない。
であり、これらのうちいずれかの要素がかけても信頼性の高い配線基板がえられないことを見出した。
(1)厚み方向の熱膨張率が90ppm/K以下
温度がT℃のときの弾性率をDT、温度がT℃のときの破断強度をHTとしたとき
(2)D23≧5GPa
(3)D150≧2.5GPa
(4)(D−65/D150)≦3.0
(5)H23≧140MPa
(6)(H−65/H150)≦2.3
基体絶縁膜の膜厚が20μm未満であると、耐熱性樹脂にガラス又はアラミドからなる補強繊維を効果的に含有することができなかった。一方、基体絶縁膜の膜厚が100μmを超えると、レーザ加工によるヴィアホールの加工性が著しく低下し、微細なヴィアホールを形成できなくなる。従って、基体絶縁膜の膜厚は20乃至100μmとする。
基体絶縁膜の厚み方向の熱膨張率が90ppm/Kを超えると、半導体デバイスを搭載した電極パッドの真下にヴィアホールを形成し、さらにこのヴィアホールの真下にボード搭載用の半田ボールを設置した場合、半導体デバイスの作動により熱負荷が繰返し印加されることを想定したヒートサイクル試験を行うと、図2のヴィアホール10aの接続部でオープン不良が発生した。従って、基体絶縁膜の厚み方向の熱膨張率は90ppm/K以下とする。
単一の材料からなる基体絶縁膜では、150℃における弾性率が1.0GPa以上あれば良好なワイヤーボンディング性が得られることが多い。しかしながら、ガラス又はアラミド補強繊維を樹脂に含有した基体絶縁膜の場合、補強繊維のみの150℃における弾性率は10GPa以上と高いため、この基体絶縁膜の150℃における弾性率が1.0GPaであったとしても、樹脂のみの150℃における弾性率は0.1GPa以下になっている。このため、ワイヤーボンディングを行うと、配線本体6が沈み込んでしまい、良好な強度を有するワイヤー接続を行うことができない。そこで、基体絶縁膜の150℃における弾性率とワイヤーボンディング強度との関係を実験で確認した結果、150℃における弾性率が2.5GPa以上であれば、良好なワイヤーボンディング性が得られることがわかった。従って、基体絶縁膜の150℃における弾性率は2.5GPa以上とする。なお、150℃における弾性率が2.5GPa以上を満たすためには、補強繊維に含浸する耐熱性樹脂は、ガラス転移温度150℃以上でなければならないことがわかった。なお、ガラス転移温度は、JIS6481に準拠し、DMA(Dynamic Mechanical analysis)法で測定した。
(D−65/D150)値が大きいということは、低温と高温における弾性率の変化量が大きいことを意味する。特願2003−382418には、この値が大きくなると配線基板に取り付けられた半田ボールが破損してしまうので、(D−65/D150)値は4.7以下にしなければならないと記載されている。しかしながら、(D−65/D150)値が3.0より大きくなると、半導体パッケージ組立時における加熱、冷却工程の繰り返しにより、配線基板に歪み応力が加わり、半導体パッケージ自体が反ってしまうトラブルが発生することがわかった。従って、(D−65/D150)値は3.0以下とする。
基体絶縁膜の23℃における破断強度が140MPaより小さいと、基体絶縁膜の膜厚が20μmである配線基板の場合、半導体パッケージ組立時における搬送時に、基体絶縁膜に亀裂が入ってしまう。従って、基体絶縁膜の23℃における破断強度は140MPa以上とする。
(H−65/H150)値が大きいということは、低温と高温における破断強度の変化量が大きいことを意味する。特願2003−382418には、この値が大きくなると基体絶縁膜にクラックが発生してしまうので、(H−65/H150)値は4.5以下にしなければならないと記載されている。しかしながら、(H−65/H150)値が2.3より大きいものでは、高温時における機械的強度が極端に低下するので、ワイヤーボンディングなどの高温時における半導体パッケージ組立工程で基体絶縁膜に微少ながらもクラックが発生してしまうことがわかった。従って、(H−65/H150)値は2.3以下とする。
下層配線の下面と基体絶縁膜の下面との間の距離が0.5μm未満であると、バンプの位置ずれを防止する効果が十分に得られない。一方、前記距離が10μmを超えると、配線基板に半導体デバイスを搭載する際に、基体絶縁膜と半導体デバイスとの間のギャップが小さくなる。このため、半導体デバイスを搭載した後にこのギャップにアンダーフィル樹脂を充填してアンダーフィルを設ける場合には、このギャップにアンダーフィル樹脂を流し込むことが困難になる。従って、前記距離は0.5乃至10μmであることが好ましい。
2;レジスト
3;導体配線層
4;エッチング容易層
5;エッチングバリア層
6;配線本体
7;基体絶縁膜
7a;凹部
8;絶縁層
10;ヴィアホール
11;上層配線
12;ソルダーレジスト
13;配線基板
14、14a;バンプ
15、15a、15b;半導体デバイス
16;アンダーフィル
17;モールディング
18;半田ボール
19;半導体パッケージ
21;配線基板
22;中間配線
23;中間絶縁膜
24;ヴィアホール
25;半導体パッケージ
26;マウント材
27;ワイヤー
41;保護膜
42;エッチング部
43;配線基板
71;貫通スルーホール
72;導体配線
73;ベースコア基板
74;ヴィアホール
75;層間絶縁膜
76;導体配線
81;導体配線
82;プリプレグ
83;スルーホール
84;導体ペースト
85;プリント基板
86;ランドパターン
91;支持板
92;導体配線
93;層間絶縁膜
94;ヴィアホール
95;導体配線
96;支持体
97;配線基板
Claims (11)
- ヴィアホールが形成され膜厚が20乃至100μmの基体絶縁膜と、この基体絶縁膜の下面に形成され前記ヴィアホールに接続された下層配線と、前記基体絶縁膜上に形成され前記ヴィアホールを介して前記下層配線に接続された上層配線と、を有し、前記基体絶縁膜の下面には凹部が形成されていて、前記下層配線は前記凹部に埋め込まれており、前記下層配線の少なくとも一部は半導体デバイス搭載用の接続電極であり、前記基体絶縁膜はガラス又はアラミドからなる補強繊維をガラス転移温度150℃以上の耐熱性樹脂に含有させたものであり、さらに下記(1)〜(6)の物性を有するものであることを特徴とする配線基板。
(1)厚み方向の熱膨張率が90ppm/K以下
温度がT℃のときの弾性率をDT、温度がT℃のときの破断強度をHTとしたとき
(2)D23≧5GPa
(3)D150≧2.5GPa
(4)(D−65/D150)≦3.0
(5)H23≧140MPa
(6)(H−65/H150)≦2.3 - 前記補強繊維の直径が10μm以下であることを特徴とする請求項1に記載の配線基板。
- 前記基体絶縁膜と前記上層配線との間に配置され、前記ヴィアホールを介して前記下層配線に接続された中間配線と、この中間配線を覆うように形成されこの中間配線と前記上層配線とを相互に接続する他のヴィアホールが形成された中間絶縁膜とよりなる配線構造層を1又は複数層有することを特徴とする請求項1又は2に記載の配線基板。
- 前記下層配線の下面は、前記基体絶縁膜の下面よりも0.5乃至10μm上方に位置していることを特徴とする請求項1に記載の配線基板。
- 前記基体絶縁膜の下面と前記下層配線の下面とが、同一平面をなしていることを特徴とする請求項1乃至3のいずれか1項に記載の配線基板。
- 前記基体絶縁膜の下方に形成され、前記下層配線の一部を覆うと共に残部を露出させる保護膜を有することを特徴とする請求項5に記載の配線基板。
- 前記上層配線の一部を覆い、残部を露出させるソルダーレジスト層を有することを特徴とする請求項1乃至6のいずれか1項に記載の配線基板。
- 請求項1乃至7のいずれか1項に記載の配線基板と、この配線基板に搭載された半導体デバイスと、を有することを特徴とする半導体パッケージ。
- 前記半導体デバイスは、前記下層配線に接続されていることを特徴とする請求項8に記載の半導体パッケージ。
- 第2の半導体デバイスが、前記上層配線に接続されていることを特徴とする請求項9に記載の半導体パッケージ。
- 前記上層配線又は前記下層配線に接続された、外部素子との接続用端子をさらに有することを特徴とする請求項8乃至10のいずれか1項に記載の半導体パッケージ。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004142133A JP4108643B2 (ja) | 2004-05-12 | 2004-05-12 | 配線基板及びそれを用いた半導体パッケージ |
TW094113919A TWI259045B (en) | 2004-05-12 | 2005-04-29 | Wiring board and semiconductor package using the same |
CNB200510070096XA CN100380637C (zh) | 2004-05-12 | 2005-05-10 | 布线板及使用该板的半导体封装 |
US11/125,158 US7397000B2 (en) | 2004-05-12 | 2005-05-10 | Wiring board and semiconductor package using the same |
US12/140,041 US7566834B2 (en) | 2004-05-12 | 2008-06-16 | Wiring board and semiconductor package using the same |
Applications Claiming Priority (1)
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JP2004142133A JP4108643B2 (ja) | 2004-05-12 | 2004-05-12 | 配線基板及びそれを用いた半導体パッケージ |
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JP2005327780A JP2005327780A (ja) | 2005-11-24 |
JP4108643B2 true JP4108643B2 (ja) | 2008-06-25 |
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Country Status (4)
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US (2) | US7397000B2 (ja) |
JP (1) | JP4108643B2 (ja) |
CN (1) | CN100380637C (ja) |
TW (1) | TWI259045B (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9232642B2 (en) | 2012-07-20 | 2016-01-05 | Shinko Electric Industries Co., Ltd. | Wiring substrate, method for manufacturing the wiring substrate, and semiconductor package |
Families Citing this family (85)
Publication number | Priority date | Publication date | Assignee | Title |
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WO2004064467A1 (ja) * | 2003-01-16 | 2004-07-29 | Fujitsu Limited | 多層配線基板、その製造方法、および、ファイバ強化樹脂基板の製造方法 |
US7656677B2 (en) * | 2004-01-27 | 2010-02-02 | Murata Manufacturing Co., Ltd. | Multilayer electronic component and structure for mounting multilayer electronic component |
TWI280084B (en) * | 2005-02-04 | 2007-04-21 | Phoenix Prec Technology Corp | Thin circuit board |
JP4768994B2 (ja) | 2005-02-07 | 2011-09-07 | ルネサスエレクトロニクス株式会社 | 配線基板および半導体装置 |
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US7566834B2 (en) | 2009-07-28 |
US20080258283A1 (en) | 2008-10-23 |
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TWI259045B (en) | 2006-07-21 |
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