JP5114130B2 - 配線基板及びその製造方法、及び半導体装置 - Google Patents
配線基板及びその製造方法、及び半導体装置 Download PDFInfo
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- JP5114130B2 JP5114130B2 JP2007218146A JP2007218146A JP5114130B2 JP 5114130 B2 JP5114130 B2 JP 5114130B2 JP 2007218146 A JP2007218146 A JP 2007218146A JP 2007218146 A JP2007218146 A JP 2007218146A JP 5114130 B2 JP5114130 B2 JP 5114130B2
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
- H05K1/113—Via provided in pad; Pad over filled via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/09472—Recessed pad for surface mounting; Recessed electrode of component
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/13—Moulding and encapsulation; Deposition techniques; Protective layers
- H05K2203/1305—Moulding and encapsulation
- H05K2203/1327—Moulding over PCB locally or completely
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
- H05K3/205—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/941—Dispositions of bond pads
- H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49158—Manufacturing circuit on or in base with molding of insulated base
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structure Of Printed Boards (AREA)
Description
図2は、本発明の第1の実施の形態に係る半導体装置の断面図である。
図14は、本発明の第2の実施の形態に係る半導体装置の断面図である。図14において、第1の実施の形態の半導体装置10と同一構成部分には同一符号を付す。
図15は、本発明の第3の実施の形態に係る半導体装置の断面図である。図15において、第1の実施の形態の半導体装置10と同一構成部分には同一符号を付す。
図16は、本発明の第4の実施の形態に係る半導体装置の断面図である。図16において、第2の実施の形態の半導体装置80と同一構成部分には同一符号を付す。
11,91,101 配線基板
12,13,92,105 電子部品
14,81 外部接続端子
16 バンプ
17 アンダーフィル樹脂
18,82,106 はんだ
21,27,31 樹脂層
21A,21B,27B,31B,33A,37A,51A 面
22,23 パッド
25,26,28,29 配線パターン
32,36,54,56,61,63 ビア
33,37 外部接続用パッド
41 ソルダーレジスト
41A,41B,66,67,94A,95A,95B 開口部
42 モールド樹脂
51 Au層
52 Ni層
55,57,62,64 配線
71 金属板
73 下部金型
74 上部金型
75,76 突出部
84 支持体
85 ピン本体
A 空間
B,C 突出量
D 切断位置
H1,H2 高さ
M1〜M3 厚さ
Claims (13)
- 積層されると共に、最下層又は最上層に配置された第1の樹脂層を有する複数の樹脂層と、前記複数の樹脂層に形成された配線パターンと、前記第1の樹脂層に設けられ、外部接続端子が配設される外部接続用パッドと、を備えた配線基板であって、
前記外部接続用パッドが設けられた側の前記第1の樹脂層の面に、前記外部接続用パッドを露出する開口部を有するようにモールド樹脂を設けると共に、
前記モールド樹脂の厚さを、前記外部接続用パッドに配設された前記外部接続端子よりも突出しない厚さにしたことを特徴とする配線基板。 - 積層された前記複数の樹脂層は、前記第1の樹脂層の反対側に配置された第2の樹脂層を有しており、
前記第2の樹脂層に、前記配線パターンを介して、前記外部接続用パッドと電気的に接続されると共に、電子部品が搭載される電子部品搭載用パッドを設けたことを特徴とする請求項1記載の配線基板。 - 前記外部接続端子が、はんだボール、または、ネイルヘッドとピン本体とを有するピン形状の端子であることを特徴とする請求項1または2記載の配線基板。
- 前記モールド樹脂の厚さが0.2mm〜0.3mmであることを特徴とする請求項1乃至3いずれか一項に記載の配線基板。
- 前記モールド樹脂内に電子部品が内蔵されていることを特徴とする請求項1乃至4いずれか一項に記載の配線基板。
- 前記配線基板がコアレス基板であることを特徴とする請求項1乃至5いずれか一項に記載の配線基板。
- 請求項1乃至6のうち、いずれか一項記載の配線基板と、
前記配線パターンと電気的に接続される電子部品と、を備えたことを特徴とする半導体装置。 - 積層されると共に、最下層又は最上層に配置された第1の樹脂層を有する複数の樹脂層と、前記複数の樹脂層に形成された配線パターンと、前記第1の樹脂層に設けられ、外部接続端子が配設される外部接続用パッドと、を備えた配線基板の製造方法であって、
前記最下層又は前記最上層に配置された前記第1の樹脂層の前記外部接続用パッドが設けられた側の面に、前記外部接続用パッドを露出するようにモールド樹脂を形成するモールド樹脂形成工程を、含み、
前記モールド樹脂形成工程では、前記モールド樹脂が前記外部接続用パッドに配設される前記外部接続端子よりも突出しない厚さに前記モールド樹脂を形成することを特徴とする配線基板の製造方法。 - 前記モールド樹脂は、トランスファーモールド法により形成することを特徴とする請求項8記載の配線基板の製造方法。
- 前記外部接続端子が、はんだボール、または、ネイルヘッドとピン本体とを有するピン形状の端子であることを特徴とする請求項8または9記載の配線基板の製造方法。
- 前記モールド樹脂の厚さが0.2mm〜0.3mmであることを特徴とする請求項8乃至10いずれか一項に記載の配線基板の製造方法。
- 前記モールド樹脂内に電子部品が内蔵されていることを特徴とする請求項8乃至11いずれか一項に記載の配線基板の製造方法。
- 前記配線基板がコアレス基板であることを特徴とする請求項8乃至12いずれか一項に記載の配線基板の製造方法。
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007218146A JP5114130B2 (ja) | 2007-08-24 | 2007-08-24 | 配線基板及びその製造方法、及び半導体装置 |
| KR1020080080333A KR101412720B1 (ko) | 2007-08-24 | 2008-08-18 | 배선 기판, 그 제조 방법, 및 배선 기판을 가지는 반도체 장치 |
| TW097132053A TWI479971B (zh) | 2007-08-24 | 2008-08-22 | 佈線板,其製造方法及具有佈線板之半導體裝置 |
| US12/196,432 US8379401B2 (en) | 2007-08-24 | 2008-08-22 | Wiring board, method of manufacturing the same, and semiconductor device having wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007218146A JP5114130B2 (ja) | 2007-08-24 | 2007-08-24 | 配線基板及びその製造方法、及び半導体装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2009054686A JP2009054686A (ja) | 2009-03-12 |
| JP5114130B2 true JP5114130B2 (ja) | 2013-01-09 |
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| Application Number | Title | Priority Date | Filing Date |
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| JP2007218146A Active JP5114130B2 (ja) | 2007-08-24 | 2007-08-24 | 配線基板及びその製造方法、及び半導体装置 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US8379401B2 (ja) |
| JP (1) | JP5114130B2 (ja) |
| KR (1) | KR101412720B1 (ja) |
| TW (1) | TWI479971B (ja) |
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| JP4473141B2 (ja) * | 2005-01-04 | 2010-06-02 | 日立オートモティブシステムズ株式会社 | 電子制御装置 |
| JP4072176B2 (ja) * | 2005-08-29 | 2008-04-09 | 新光電気工業株式会社 | 多層配線基板の製造方法 |
| JP4452222B2 (ja) * | 2005-09-07 | 2010-04-21 | 新光電気工業株式会社 | 多層配線基板及びその製造方法 |
| JP2007123524A (ja) * | 2005-10-27 | 2007-05-17 | Shinko Electric Ind Co Ltd | 電子部品内蔵基板 |
| CN102654409A (zh) * | 2006-04-28 | 2012-09-05 | 松下电器产业株式会社 | 电容式传感器 |
| JP4961848B2 (ja) * | 2006-06-12 | 2012-06-27 | 日本電気株式会社 | 金属ポストを有する配線基板、半導体装置及び半導体装置モジュールの製造方法 |
| DE102007034402B4 (de) * | 2006-12-14 | 2014-06-18 | Advanpack Solutions Pte. Ltd. | Halbleiterpackung und Herstellungsverfahren dafür |
| KR100827667B1 (ko) * | 2007-01-16 | 2008-05-07 | 삼성전자주식회사 | 기판 내에 반도체 칩을 갖는 반도체 패키지 및 이를제조하는 방법 |
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| Publication number | Publication date |
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| JP2009054686A (ja) | 2009-03-12 |
| US20090052150A1 (en) | 2009-02-26 |
| TWI479971B (zh) | 2015-04-01 |
| KR20090021076A (ko) | 2009-02-27 |
| TW200913844A (en) | 2009-03-16 |
| US8379401B2 (en) | 2013-02-19 |
| KR101412720B1 (ko) | 2014-06-26 |
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