TWI408785B - 半導體封裝結構 - Google Patents

半導體封裝結構 Download PDF

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TWI408785B
TWI408785B TW098146112A TW98146112A TWI408785B TW I408785 B TWI408785 B TW I408785B TW 098146112 A TW098146112 A TW 098146112A TW 98146112 A TW98146112 A TW 98146112A TW I408785 B TWI408785 B TW I408785B
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pads
substrate
solder
semiconductor package
package structure
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TW098146112A
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TW201123384A (en
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Chi Chih Chu
Cheng Yi Weng
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Advanced Semiconductor Eng
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Priority to TW098146112A priority Critical patent/TWI408785B/zh
Priority to US12/818,422 priority patent/US8405212B2/en
Publication of TW201123384A publication Critical patent/TW201123384A/zh
Priority to US13/773,896 priority patent/US20130161816A1/en
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Publication of TWI408785B publication Critical patent/TWI408785B/zh

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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Computer Hardware Design (AREA)
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  • Lead Frames For Integrated Circuits (AREA)
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Description

半導體封裝結構
本發明係關於一種半導體封裝結構，詳言之，係關於一種可防止銲料橋接之半導體封裝結構。
參考圖1至圖4，顯示習知半導體封裝結構之製造方法之示意圖。參考圖1，提供一基板11，該基板11具有一第一表面111、一第二表面112、複數個第一銲墊113、複數個第二銲墊114、一鎳金鍍層115及一防銲層116。該等第一銲墊113係顯露於該第一表面111，該等第二銲墊114係顯露於該第二表面112，該鎳金鍍層115係形成於該第一銲墊113整個上表面上。該防銲層116係直接接觸該鎳金鍍層115，且具有至少一開口以顯露部分該等鎳金鍍層115。接著，附著一晶片12至該基板11，且形成複數個導電元件(例如複數條導線13)以電性連接該晶片12及該基板11之第一表面111。之後，形成複數個第一導體(例如複數個第一銲球14)於該該鎳金鍍層115上。
參考圖2，形成一封膠材料15於該基板11之第一表面111上，以包覆該晶片12、該等導線13及該等第一銲球14。參考圖3，形成複數個第二銲球16於該等第二銲墊114上，並迴銲該等第二銲球16。參考圖4，去除該封膠材料15之一外圍區域之一部分，使得該封膠材料15具有至少二高度，且暴露出該等第一銲球14之一端，而製成該習知半導體封裝結構1。
該習知半導體封裝結構1之缺點如下。首先，該防銲層116係直接接觸該鎳金鍍層115，然而該防銲層116與該鎳金鍍層115間之結合力不佳，故該防銲層116及該鎳金鍍層115之間容易產生脫層的問題。此外，位於該鎳金鍍層115上之該等第一銲球14被該封膠材料15所包覆，而在迴銲該等第二銲球16時，該等第一銲球14也同時受高溫影響而膨脹。此時，該等第一銲球14向鄰近元件擠壓，而擴散至結合力不佳之該防銲層116及該鎳金鍍層115間之介面，最後，導致該等第一銲球14產生橋接，如圖3至圖5之區域A所示，而降低良率。
因此，有必要提供一種半導體封裝結構，以解決上述問題。
本發明提供一種半導體封裝結構。該半導體封裝結構包括一基板、至少一晶片、複數個導電元件、複數個第一導體及一封膠材料。該基板具有一第一表面、一第二表面、複數個第一銲墊及一防銲層。該等第一銲墊係顯露於該第一表面，且其材質係為銅。該防銲層係直接接觸該等第一銲墊，且具有至少一開口以顯露部分該等第一銲墊。該晶片係附著至該基板。該等導電元件係電性連接該晶片及該基板。該等第一導體係位於該等第一銲墊上。該封膠材料係位於該基板之第一表面上，且包覆該晶片、該等導電元件及該等第一導體。該封膠材料具有一第一頂面及一第二頂面，該第一頂面及該第二頂面具有不同高度，且暴露出該等第一導體之一端，其中該暴露出之該等第一導體之頂面與該封膠材料之第二頂面係位於同一平面。
本發明更提供一種半導體封裝結構。該半導體封裝結構包括一基板、至少一晶片、複數個導電元件、複數個第一導體及一封膠材料。該基板具有一第一表面、一第二表面、複數個第一銲墊及一防銲層。該等第一銲墊係顯露於該第一表面，且其材質係為銅。該防銲層係直接接觸該等第一銲墊，且具有至少一開口以顯露部分該等第一銲墊。該晶片係附著至該基板。該等導電元件係電性連接該晶片及該基板。該等第一導體係位於該等第一銲墊上。該封膠材料係位於該基板之第一表面上，且包覆該晶片、該等導電元件及部分該等第一導體。該封膠材料具有一第一表面及複數個盲孔，該等盲孔係開口於該封膠材料之第一表面，且暴露部分該等第一導體。
藉此，該防銲層與該等第一銲墊直接接觸，而具有較佳的結合力，可避免該等第一導體滲入該防銲層及該等第一銲墊之介面，進而導致該等第一導體橋接的問題。
參考圖6，顯示本發明半導體封裝結構之第一實施例之剖面示意圖。該半導體封裝結構2包括一基板21、至少一晶片22、複數個導電元件(例如複數條導線23)、複數個第一導體(例如複數個第一銲球24)、一封膠材料25及複數個第二銲球26。該基板21具有一第一表面211、一第二表面212、複數個第一銲墊213、複數個第二銲墊214、一防銲層216及一抗氧化層217。
該等第一銲墊213係顯露於該第一表面211，且其材質係為銅。該等第二銲墊214係顯露於該第二表面212。該防銲層216係直接接觸該等第一銲墊213，且具有至少一開口以顯露部分該等第一銲墊213。該抗氧化層217係位於該防銲層216之開口所顯露之第一銲墊213上。亦即，該抗氧化層217並未完全覆蓋該第一銲墊213之整個上表面。在本實施例中，該抗氧化層217係為一鎳金鍍層(Ni/Au Plating Layer)。然而，在其他應用中，該抗氧化層217係可為有機保焊劑(Organic Solderability Preservative,OSP)，則該抗氧化層217不存在於最終結構。藉此，可避免該等第一銲墊213接觸空氣後氧化，而降低其良率。
該晶片22係附著至該基板21。在本實施例中，該晶片22係黏附於該防銲層216上。在本發明中，該晶片22係不限於任何形式之晶片。該等導線23係電性連接該晶片22及該基板21。該等第一銲球24係位於該等第一銲墊213上，較佳地，該等第一銲球24係為半球狀。該等第二銲球26係位於該等第二銲墊214上。
該封膠材料25係位於該基板21之第一表面211上，且包覆該晶片22、該等導線23及該等第一銲球24。該封膠材料25具有一第一頂面251及一第二頂面252，該第一頂面251及該第二頂面252具有不同高度，且暴露出該等第一銲球24之一端，其中該暴露出之該等第一銲球24之頂面與該封膠材料25之第二頂面252係位於同一平面。
該封膠材料25具有一第一高度H1 及一第二高度H2 ，該第一高度H1 係為該第一頂面251至該防銲層216之高度，該第二高度H2 係為該第二頂面252至該防銲層216之高度，且該第一高度H1 係大於該第二高度H2 。
參考圖7，顯示本發明半導體封裝結構之第二實施例之剖面示意圖。該半導體封裝結構3包括一基板31、至少一晶片32、複數個導電元件(例如複數條導線33)、複數個第一導體(例如複數個第一銲球34)、一封膠材料35及複數個第二銲球36。該基板31具有一第一表面311、一第二表面312、複數個第一銲墊313、複數個第二銲墊314、一防銲層316及一抗氧化層317。
該等第一銲墊313係顯露於該第一表面311，且其材質係為銅。該等第二銲墊314係顯露於該第二表面312。該防銲層316係直接接觸該等第一銲墊313，且具有至少一開口以顯露部分該等第一銲墊313。該抗氧化層317係位於該防銲層316之開口所顯露之第一銲墊313上，較佳地，該抗氧化層317係為有機保焊劑(Organic Solderability Preservative,OSP)或一鎳金鍍層(Ni/Au Plating Layer)。藉此，可避免該等第一銲墊313接觸空氣後氧化，而降低其良率。
該晶片32係附著至該基板31。在本實施例中，該晶片32係黏附於該防銲層316上。在本發明中，該晶片32係不限於任何形式之晶片。該等導線33係電性連接該晶片32及該基板31。該等第一銲球34係位於該等第一銲墊313上。該等第二銲球36係位於該等第二銲墊314上。
該封膠材料35係位於該基板31之第一表面311上，且包覆該晶片32、該等導線33及部分該等第一銲球34。該封膠材料35具有一第一表面351及複數個盲孔352，該等盲孔352係開口於該封膠材料之第一表面351，且暴露部分該等第一銲球34。
藉此，該防銲層216,316與該等第一銲墊213,313直接接觸，而具有較佳的結合力，可避免該等第一導體(該等第一銲球24,34)滲入該防銲層216,316及該等第一銲墊213,313之介面，進而導致該等第一導體(該等第一銲球24,34)橋接的問題。
惟上述實施例僅為說明本發明之原理及其功效，而非用以限制本發明。因此，習於此技術之人士對上述實施例進行修改及變化仍不脫本發明之精神。本發明之權利範圍應如後述之申請專利範圍所列。
1．．．習知半導體封裝結構
2．．．本發明半導體封裝結構之第一實施例
3．．．本發明半導體封裝結構之第二實施例
11．．．基板
12．．．晶片
13．．．導線
14．．．第一銲球
15．．．封膠材料
16．．．第二銲球
21．．．基板
22．．．晶片
23．．．導線
24．．．第一銲球
25．．．封膠材料
26．．．第二銲球
31．．．基板
32．．．晶片
33．．．導線
34．．．第一銲球
35．．．封膠材料
36．．．第二銲球
111．．．第一表面
112．．．第二表面
113．．．第一銲墊
114．．．第二銲墊
115．．．鎳金鍍層
116．．．防銲層
211．．．第一表面
212．．．第二表面
213．．．第一銲墊
214．．．第二銲墊
216．．．防銲層
217．．．抗氧化層
251．．．第一頂面
252．．．第二頂面
311．．．第一表面
312．．．第二表面
313．．．第一銲墊
314．．．第二銲墊
316．．．防銲層
317．．．抗氧化層
351．．．第一表面
352．．．盲孔
圖1至圖4顯示習知半導體封裝結構之製造方法之示意圖；
圖5顯示圖4之局部放大照片圖；
圖6顯示本發明半導體封裝結構之第一實施例之剖面示意圖；及
圖7顯示本發明半導體封裝結構之第二實施例之剖面示意圖。
2．．．本發明半導體封裝結構之第一實施例
21．．．基板
22．．．晶片
23．．．導線
24．．．第一銲球
25．．．封膠材料
26．．．第二銲球
211．．．第一表面
212．．．第二表面
213．．．第一銲墊
214．．．第二銲墊
216．．．防銲層
217．．．抗氧化層
251．．．第一頂面
252．．．第二頂面

Claims (11)

  1. 一種半導體封裝結構，包括：一基板，具有一第一表面、一第二表面、複數個第一銲墊及一防銲層，該等第一銲墊係位於該第一表面，且其材質係為銅，該防銲層係直接接觸該等第一銲墊，且具有至少一開口以顯露部分該等第一銲墊；至少一晶片，附著至該基板；複數個導電元件，電性連接該晶片及該基板；複數個第一銲球，位於該等第一銲墊上；及一封膠材料，位於該基板之第一表面上，且包覆該晶片、該等導電元件及該等第一銲球，該封膠材料具有一第一頂面及一第二頂面，該第一頂面及該第二頂面具有不同高度，且暴露出該等第一銲球之一端，其中該暴露出之該等第一銲球之頂面與該封膠材料之第二頂面係位於同一平面。
  2. 如請求項1之半導體封裝結構，其中該基板更包括一抗氧化層，位於該防銲層之開口所顯露之第一銲墊上，該抗氧化層係為一鎳金鍍層(Ni/Au Plating Layer)。
  3. 如請求項1之半導體封裝結構，其中該等第一銲球係為半球狀。
  4. 如請求項1之半導體封裝結構，其中該封膠材料具有一第一高度及一第二高度，該第一高度係於該晶片及該等導電元件之相對位置，該第二高度係於該等第一銲球之相對位置，且該第一高度係大於該第二高度。
  5. 如請求項4之半導體封裝結構，其中該第一頂面係相對於該第一高度，該第二頂面係相對於該第二高度。
  6. 如請求項1之半導體封裝結構，更包括複數個第二銲墊，位於該第二表面。
  7. 如請求項6之半導體封裝結構，更包括複數個第二銲球，位於該等第二銲墊上。
  8. 一種半導體封裝結構，包括：一基板，具有一第一表面、一第二表面、複數個第一銲墊及一防銲層，該等第一銲墊係位於該第一表面，且其材質係為銅，該防銲層係直接接觸該等第一銲墊，且具有至少一開口以顯露部分該等第一銲墊；至少一晶片，附著至該基板；複數個導電元件，電性連接該晶片及該基板；複數個第一銲球，位於該等第一銲墊上；及一封膠材料，位於該基板之第一表面上，且包覆該晶片、該等導電元件及部分該等第一銲球，該封膠材料具有一第一表面及複數個盲孔，該等盲孔係開口於該封膠材料之第一表面，且暴露部分該等第一銲球。
  9. 如請求項8之半導體封裝結構，其中該基板更包括一抗氧化層，位於該防銲層之開口所顯露之第一銲墊上，該抗氧化層係為一鎳金鍍層(Ni/Au Plating Layer)。
  10. 如請求項8之半導體封裝結構，更包括複數個第二銲墊，位於該第二表面。
  11. 如請求項10之半導體封裝結構，更包括複數個第二銲球，位於該等第二銲墊上。
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