JP2006186321A - 回路基板の製造方法及び電子部品実装構造体の製造方法 - Google Patents
回路基板の製造方法及び電子部品実装構造体の製造方法 Download PDFInfo
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- JP2006186321A JP2006186321A JP2005327314A JP2005327314A JP2006186321A JP 2006186321 A JP2006186321 A JP 2006186321A JP 2005327314 A JP2005327314 A JP 2005327314A JP 2005327314 A JP2005327314 A JP 2005327314A JP 2006186321 A JP2006186321 A JP 2006186321A
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- H01L2924/01078—Platinum [Pt]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15182—Fan-in arrangement of the internal vias
- H01L2924/15184—Fan-in arrangement of the internal vias in different layers of the multilayer substrate
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/03—Metal processing
- H05K2203/0376—Etching temporary metallic carrier substrate
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
- H05K2203/0703—Plating
- H05K2203/0723—Electroplating, e.g. finish plating
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
- H05K3/205—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier
Abstract
【解決手段】金属板10の上に、該金属板10に電気的に接続されるn層(nは1以上の整数)の配線層18〜18bを形成し、金属板10及び配線層18〜18bをめっき給電経路に利用する電解めっきにより、n層の配線層18〜18bにおける最上の配線層18bの接続パッド部に電解めっき層24を形成する。その後に、金属板10が除去される。
【選択図】図4
Description
図2〜図5は本発明の第1実施形態の回路基板の製造方法を順に示す断面図である。図2(a)に示すように、まず、銅(Cu)などからなる支持板として機能する金属板10を用意し、その金属板10上に開口部12xが設けられたドライフィルムレジスト(めっきレジスト)膜12を形成する。金属板10には、金属箔のようなフレキシブル金属材も含まれる。
図7〜図10は本発明の第2実施形態の回路基板の製造方法を示す断面図である。第2実施形態は、第1実施形態で説明した回路基板を上下反転させて、第1配線層の露出部に半導体チップをフリップチップ接続する形態である。第2実施形態では、第1実施形態と同じ工程についてはその詳しい説明を省略する。
図11〜図14は本発明の第3実施形態の電子部品実装構造体の製造方法を示す断面図である。第3実施形態では、本発明の回路基板の製造方法の技術思想に基づいて、回路基板上に電子部品を実装する方法について説明する。
Claims (15)
- 金属板の上に、該金属板に電気的に接続されるn層(nは1以上の整数)の配線層を形成する工程と、
前記金属板及び前記配線層をめっき給電経路に利用する電解めっきにより、前記n層の配線層における最上の配線層の接続パッド部に電解めっき層を形成する工程と、
前記金属板を除去する工程とを有することを特徴とする回路基板の製造方法。 - 前記n層の配線層の上方に半導体チップが実装され、該半導体チップと前記接続パッドの電解めっき層とがワイヤボンディング法によるワイヤによって接続されることを特徴とする請求項1に記載の回路基板の製造方法。
- 前記金属板を除去する工程において、前記n層の配線層における最下の配線層の下面が露出し、
前記最下の配線層に半導体チップがバンプを介してフリップチップ接続されることを特徴とする請求項1に記載の回路基板の製造方法。 - 前記n層の配線層の最下の配線層は、下側に金/ニッケル層を含むことを特徴とする請求項1乃至3のいずれか一項に記載の回路基板の製造方法。
- 前記n層の配線層の最下の配線層は、下側にすず層を含むことを特徴とする請求項1乃至3のいずれか一項に記載の回路基板の製造方法。
- 前記電解めっき層は、最上に金層を含むことを特徴とする請求項1乃至3のいずれか一項に記載の回路基板の製造方法。
- 前記金属板は、銅よりなることを特徴とする請求項1乃至3のいずれか一項に記載の回路基板の製造方法。
- 前記金属板は、ウェットエッチングにより除去されることを特徴とする請求項1乃至3のいずれか一項に記載の回路基板の製造方法。
- 前記n層の配線層の最下の配線層は、最下に金層を含むことを特徴とする請求項1乃至3のいずれか一項に記載の回路基板の製造方法。
- 金属板の上に、該金属板に電気的に接続されるn層(nは1以上の整数)の配線層を形成する工程と、
前記金属板及び前記配線層をめっき給電経路に利用する電解めっきにより、前記n層の配線層における最上の配線層の接続パッド部に電解めっき層を形成する工程と、
前記最上の配線層に設けられた電解めっき層に電気的に接続される電子部品を実装する工程と、
前記金属板を除去することにより、前記n層の配線層における最下の配線層の下面を露出させる工程とを有することを特徴とする電子部品実装構造体の製造方法。 - 前記n層の配線層の最下の配線層は、最下に金層を含むことを特徴とする請求項10に記載の電子部品実装構造体の製造方法。
- 前記電解めっき層は、最上に金層を含むことを特徴とする請求項10又は11に記載の電子部品実装構造体の製造方法。
- 前記金属板を除去する工程の後に、前記最下の配線層の下面に外部接続端子を設ける工程をさらに有することを特徴とする請求項10に記載の電子部品実装構造体の製造方法。
- 前記電子部品を実装する工程の後に、前記金属板を除去することを特徴とする請求項10に記載の電子部品実装構造体の製造方法。
- 前記電子部品は半導体チップであることを特徴とする請求項10乃至14のいずれか一項に記載の電子部品実装構造体の製造方法。
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JP2005327314A JP2006186321A (ja) | 2004-12-01 | 2005-11-11 | 回路基板の製造方法及び電子部品実装構造体の製造方法 |
KR1020050111126A KR20060061227A (ko) | 2004-12-01 | 2005-11-21 | 회로 기판의 제조 방법 및 전자부품 실장 구조체의 제조방법 |
TW094141877A TWI395274B (zh) | 2004-12-01 | 2005-11-29 | 製造電路基材的方法及製造電子部件封裝結構的方法 |
CN 200510129078 CN1791311B (zh) | 2004-12-01 | 2005-11-30 | 制造电路基板的方法和制造电子部件封装结构的方法 |
US11/289,785 US7435680B2 (en) | 2004-12-01 | 2005-11-30 | Method of manufacturing a circuit substrate and method of manufacturing an electronic parts packaging structure |
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- 2005-11-11 JP JP2005327314A patent/JP2006186321A/ja active Pending
- 2005-11-21 KR KR1020050111126A patent/KR20060061227A/ko not_active Application Discontinuation
- 2005-11-29 TW TW094141877A patent/TWI395274B/zh not_active IP Right Cessation
- 2005-11-30 US US11/289,785 patent/US7435680B2/en active Active
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Also Published As
Publication number | Publication date |
---|---|
TW200625485A (en) | 2006-07-16 |
TWI395274B (zh) | 2013-05-01 |
US20060121719A1 (en) | 2006-06-08 |
US7435680B2 (en) | 2008-10-14 |
KR20060061227A (ko) | 2006-06-07 |
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