JP2009105393A - 配線基板及び半導体装置、並びにこれらの製造方法 - Google Patents
配線基板及び半導体装置、並びにこれらの製造方法 Download PDFInfo
- Publication number
- JP2009105393A JP2009105393A JP2008259027A JP2008259027A JP2009105393A JP 2009105393 A JP2009105393 A JP 2009105393A JP 2008259027 A JP2008259027 A JP 2008259027A JP 2008259027 A JP2008259027 A JP 2008259027A JP 2009105393 A JP2009105393 A JP 2009105393A
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- Japan
- Prior art keywords
- support
- wiring board
- layer
- roughened
- semiconductor element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
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- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
- H05K3/205—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier
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Abstract
【解決手段】支持体20の表面に誘電体層23と配線層とを積層し、中間体を形成する工程と、該中間体から支持体を除去し、配線基板を得る工程と、から成り、前記中間体形成工程の前に、前記支持20の表面20aに粗化処理を施しておくことを特徴とする。
【選択図】図3
Description
300nm ≦ Ra ≦ 800nm、
3.5μm ≦ Rz ≦ 7μm、
であるのが好適である。
図3及び図4は本発明の第1実施形態に係る配線基板の製造方法を工程順に示すものである。図3(a)において、支持体20を準備する。支持体20としては、例えば、Cu等からなる金属板、或いは同様にCu等からなる金属箔を用いるのが一般である。Cuから成る銅箔の場合は、圧延銅箔、電解銅箔等が好適に用いられる。
この際、支持体20の粗化面20aの表面形状が、半導体素子搭載面27の絶縁層23に転写され、半導体素子搭載面27が粗化面23aとなる。
この際、支持体20の粗化面20aの表面形状が、半導体素子搭載面27のソルダレジスト層29に転写され、半導体素子搭載面27が粗化面29aとなる。
1)第1及び2実施形態では、支持体20に粗面化処理を施した後、めっき層22(接続パッド)を形成している。よって、支持体20の粗化面にめっきレジスト層21が食い込むことにより、めっきレジスト層21と支持体20との密着性が向上し、めっきレジスト層21の下部におけるめっき形成用の開口部の縁等の不要部分へのめっき液しみ込みが発生せず、良好に安定した形状のめっき層22を形成できことができる。
このように、第1〜第3実施形態では、ソルダレジスト層29と支持体20との密着性が向上するため、製造工程中に、支持体20から製造途中の中間体40が剥離・脱落することを防止できる利点がある。
この際、支持体20の粗化面20aの表面形状が、半導体素子搭載面27の絶縁層23に転写され、半導体素子搭載面27が、粗化面23aとなる。
300nm ≦ Ra ≦ 800nm、
3.5μm ≦ Rz ≦ 7μm、
となるように、支持体の表面の粗さを調整するのが好適である。
20a 支持体の粗化面
21 めっきレジスト層
21a 開口部
22 めっき層
23 絶縁層(誘電体層)
23a 絶縁層の粗化面
24 ビア孔(開口)
25 配線層(金属層)
26 ソルダレジスト層(誘電体層)
27 半導体素子搭載面
28 外部接続端子面
29 ソルダレジスト層
29a ソルダレジスト層の粗化面
30 半導体素子
40 中間体
42 配線基板(多層配線基板ないし半導体パッケージ)
Claims (23)
- 表面に粗化処理を施した支持体の該表面に誘電体層と配線層とを積層し、中間体を形成する工程と、
該中間体から支持体を除去し、配線基板を得る工程と、
から成ることを特徴とする配線基板の製造方法。 - 支持体は金属からなり、エッチングにより、該支持体の表面に粗化処理を施し、粗化面を形成することを特徴とする請求項1に記載の配線基板の製造方法。
- 支持体は金属からなり、酸化処理により酸化膜を設けることにより、該支持体の表面に粗化処理を施し、粗化面を形成することを特徴とする請求項1に記載の配線基板の製造方法。
- 支持体は金属からなり、めっきにより、該支持体の表面に粗化処理を施し、粗化面を形成することを特徴とする請求項1に記載の配線基板の製造方法。
- 誘電体層が、絶縁層又はソルダレジスト層であることを特徴とする請求項1〜4のいずれか1項に記載の配線基板の製造方法。
- 前記支持体の粗化面の表面形状が、配線基板の支持体除去面の誘電体層及び/又は配線層の表面に転写され、該誘電体層及び/又は配線層の表面が粗化面に形成されることを特徴とする請求項1〜5のいずれか1項に記載の配線基板の製造方法。
- 前記支持体の表面の粗化の程度は、
300nm ≦ Ra ≦ 800nm、
3.5μm ≦ Rz ≦ 7μm、
であることを特徴とする請求項1〜6のいずれか1項に記載の配線基板の製造方法。 - 該支持体の粗化面に配線層としての接続パッドを形成し、該支持体の粗化面の表面形状が該接続パッドの表面に転写され、該接続パッド表面が粗化面に形成されることを特徴とする請求項1〜7のいずれか1項に記載の配線基板の製造方法。
- 表面に粗化処理を施した支持体の該表面に誘電体層と配線層とを積層し、中間体を形成する工程と、
該中間体から支持体を除去し、配線基板を得る工程と、
該配線基板の支持体除去面に、半導体素子を搭載する工程と、
から成ることを特徴とする半導体装置の製造方法。 - 表面に粗化処理を施した支持体の該表面に誘電体層と配線層とを積層し、中間体を形成する工程と、
該中間体から支持体を除去し、配線基板を得る工程と、
該配線基板の支持体除去面と対向する面に、半導体素子を搭載する工程と、
から成ることを特徴とする半導体装置の製造方法。 - 表面に粗化処理を施した支持体の該表面に誘電体層と配線層とを積層し、中間体を形成する工程と、
該中間体の、前記支持体との接触面と対向する面上に、半導体素子を搭載する工程と、
該中間体から支持体を除去し、半導体装置を得る工程と、
から成ることを特徴とする半導体装置の製造方法。 - 誘電体層が、絶縁層又はソルダレジスト層であることを特徴とする請求項9〜11のいずれか1項に記載の半導体装置の製造方法。
- 支持体は金属からなり、エッチングにより、該支持体の表面に粗化処理を施し、粗化面を形成することを特徴とする請求項9〜11のいずれか1項に記載の半導体装置の製造方法。
- 支持体は金属からなり、めっきにより、該支持体の表面に粗化処理を施し、粗化面を形成することを特徴とする請求項9〜11のいずれか1項に記載の半導体装置の製造方法。
- 支持体は金属からなり、酸化処理により酸化膜を設けることにより、該支持体の表面に粗化処理を施し、粗化面を形成することを特徴とする請求項8〜10のいずれか1項に記載の半導体装置の製造方法。
- 前記支持体の粗化面の表面形状が、配線基板の支持体除去面の誘電体層及び/又は配線層の表面に転写され、該誘電体層及び/又は配線層の表面が粗化面に形成されることを特徴とする請求項8〜13のいずれか1項に記載の半導体装置の製造方法。
- 誘電体層と配線層とが積層され、一方の面が半導体素子搭載面であり、該一方の面に対向する他方の面が外部接続端子面である配線基板の、
該半導体素子搭載面の誘電体層及び/又は配線層の表面が、粗化面に形成されていることを特徴とする配線基板。 - 誘電体層と配線層とが積層され、一方の面が半導体素子搭載面であり、該一方の面に対向する他方の面が外部接続端子面である配線基板の、
該外部接続端子面の誘電体層及び/又は配線層の表面が、粗化面に形成されていることを特徴とする配線基板。 - 誘電体層が、絶縁層又はソルダレジスト層であることを特徴とする請求項15又は16に記載の配線基板。
- 前記配線層には接続パッドを含み、前記誘電体表面から露出する該接続パッドの表面が粗化面に形成されていることを特徴とする請求項15又は16に記載の配線基板。
- 誘電体層と配線層とが積層され、一方の面が半導体素子搭載面であり、該一方の面に対向する他方の面が外部接続端子面である配線基板の、
該半導体素子搭載面の誘電体層及び/又は配線層の表面が、粗化面に形成されており、
該半導体素子搭載面に、半導体素子がフリップチップ接続により搭載されており、
該半導体素子と半導体素子搭載面との間に、アンダーフィル樹脂が充填されていることを特徴とする半導体装置。 - 誘電体層と配線層とが積層され、一方の面が半導体素子搭載面であり、該一方の面に対向する他方の面が外部接続端子面である配線基板の、
該外部接続端子面の誘電体層及び/又は配線層の表面が、粗化面に形成されており、
前記半導体素子搭載面に、半導体素子が搭載されていることを特徴とする半導体装置。 - 誘電体層が、絶縁層又はソルダレジスト層であることを特徴とする請求項19又は20に記載の半導体装置。
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KR20090035449A (ko) | 2009-04-09 |
JP5456103B2 (ja) | 2014-03-26 |
US8779602B2 (en) | 2014-07-15 |
JP2012209580A (ja) | 2012-10-25 |
CN101404259A (zh) | 2009-04-08 |
KR101551898B1 (ko) | 2015-09-09 |
KR20150033625A (ko) | 2015-04-01 |
TW200919672A (en) | 2009-05-01 |
US20120155048A1 (en) | 2012-06-21 |
US20090095514A1 (en) | 2009-04-16 |
JP5398217B2 (ja) | 2014-01-29 |
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US8502398B2 (en) | 2013-08-06 |
TWI447874B (zh) | 2014-08-01 |
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