TWI473551B - 封裝基板及其製法 - Google Patents
封裝基板及其製法 Download PDFInfo
- Publication number
- TWI473551B TWI473551B TW100124360A TW100124360A TWI473551B TW I473551 B TWI473551 B TW I473551B TW 100124360 A TW100124360 A TW 100124360A TW 100124360 A TW100124360 A TW 100124360A TW I473551 B TWI473551 B TW I473551B
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- dielectric layer
- circuit
- circuit layer
- electrical contact
- Prior art date
Links
- 239000000758 substrate Substances 0.000 title claims description 76
- 238000000034 method Methods 0.000 title claims description 29
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 229910052751 metal Inorganic materials 0.000 claims description 78
- 239000002184 metal Substances 0.000 claims description 78
- 239000004065 semiconductor Substances 0.000 claims description 14
- 230000008569 process Effects 0.000 claims description 13
- 239000010410 layer Substances 0.000 description 227
- 229910000679 solder Inorganic materials 0.000 description 23
- 235000012431 wafers Nutrition 0.000 description 14
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 8
- 239000000463 material Substances 0.000 description 5
- 239000002245 particle Substances 0.000 description 5
- 238000006068 polycondensation reaction Methods 0.000 description 5
- 229910052763 palladium Inorganic materials 0.000 description 4
- 239000012792 core layer Substances 0.000 description 3
- 238000007772 electroless plating Methods 0.000 description 3
- 239000002923 metal particle Substances 0.000 description 3
- 238000012858 packaging process Methods 0.000 description 3
- 239000003973 paint Substances 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 230000004913 activation Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- QAOWNCQODCNURD-UHFFFAOYSA-L Sulfate Chemical compound [O-]S([O-])(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-L 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000013522 chelant Substances 0.000 description 1
- 238000005234 chemical deposition Methods 0.000 description 1
- 239000000084 colloidal system Substances 0.000 description 1
- 238000009833 condensation Methods 0.000 description 1
- 230000005494 condensation Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical class [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000011135 tin Substances 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- HPGGPRDJHPYFRM-UHFFFAOYSA-J tin(iv) chloride Chemical compound Cl[Sn](Cl)(Cl)Cl HPGGPRDJHPYFRM-UHFFFAOYSA-J 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/13111—Tin [Sn] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13139—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13144—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13155—Nickel [Ni] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
本發明係有關一種封裝基板及其製法,尤指一種無核心層之封裝基板及其製法。
隨著電子產業的蓬勃發展,電子產品也逐漸邁向多功能、高性能的趨勢。目前半導體封裝結構已開發出不同的封裝型態,例如:打線式或覆晶式,係於一封裝基板上設置半導體晶片,且該半導體晶片藉由導線或焊錫凸塊電性連接至該封裝基板上。為了滿足半導體封裝件高整合度(integration)及微型化(miniaturization)的封裝需求,以供更多主、被動元件及線路載接,封裝基板亦逐漸由雙層電路板演變成多層電路板(multi-layer board),俾於有限的空間下運用層間連接技術(interlayer connection)以擴大封裝基板上可供利用的線路佈局面積,並能配合高線路密度之積體電路(integrated circuit)的使用需求,且降低封裝基板的厚度,而能達到封裝結構輕薄短小及提高電性功能之目的。
習知技術中,封裝基板係由一具有內層線路之核心板及對稱形成於其兩側之線路增層結構所構成。因使用核心板將導致整體結構厚度增加,故難以滿足電子產品功能不斷提昇而體積卻不斷縮小的需求。
因此,遂發展出無核心層(coreless)之封裝基板,以縮短導線長度及降低整體結構厚度以符合高頻化、微小化的趨勢。如第1圖所示之無核心層之封裝基板1,其製法係包括:於一承載板(未圖示)上形成第一介電層120a,且於該第一介電層120a上形成第一線路層11;於該第一介電層120a與第一線路層11上形成線路增層結構12,該線路增層結構12具有第二、第三與第四介電層120b,120c,120d,且於該第二至第四介電層120b,120c,120d上形成有第二線路層121,各該第二線路層121藉由導電盲孔122相互電性連接;移除該承載板,以外露該第一介電層120a;於該第一介電層120a、及第四介電層120d與第二線路層121上分別形成如綠漆之防焊層14a,14b;於該防焊層14a與第一介電層120a中形成開孔140a,以外露該第一線路層11之部分表面,並於該防焊層14b上形成開孔140b,以外露該第二線路層121之部分表面;於該開孔140a,140b中形成金屬凸塊13a,13b,以分別結合焊球15a,15b,令上側焊球15b用以接置晶片(未圖示),而下側焊球15a用以接置電路板(未圖示),換句話說,上述製程是從封裝基板1的下側(即接觸該承載板之表面)開始製作,而後逐漸增層至用以接置晶片的金屬凸塊13b與防焊層14b為止,也就是從植球側開始製作到置晶側。
其中,每製作一層介電層時即需進行一次固化(curing)製程,使原本半固化的介電材的結構得以固化,且介電層經固化的次數越多,介電層之內部分子向中間集中聚縮的程度越完全,又每一次的固化製程都會影響整體結構中所有的介電層,故於習知封裝基板1中,該第一介電層120a係經過四次固化製程,而該第二、第三與第四介電層120b,120c,120d則分別經過三次、二次與一次固化製程。
承上述,因該第一至第四介電層120a,120b,120c,120d所經過之固化次數不同,會造成各介電層尚存的聚縮能力亦不相同,由於該第一介電層120a經過最多次固化製程,所以幾乎不再有聚縮能力,即該第一介電層120a中幾乎沒有聚縮力存在,依此類推,該第二、第三與第四介電層120b,120c,120d中的聚縮力將依序漸增,而由於各介電層的聚縮力都會對封裝基板產生一種由四周往中心拉扯的力量,故習知封裝基板1呈現該第四介電層120d之側下凹且該第一介電層120a之側凸出的翹曲現象,即置晶側朝上的整體封裝基板1呈「微笑」狀是此類製程所顯現的一個特性,而此基板彎翹之現象會造成封裝基板的製作及其後續封裝製程的困擾,進而影響良率。
惟,該第一介電層120a及第四介電層120d上分別形成有該防焊層14a,14b,且因下側防焊層14a之開孔140a大於該上側防焊層14b之開孔140b,故下側防焊層14a的實際覆蓋面積小於該上側防焊層14b的實際覆蓋面積,即該上側防焊層14b具有較下側防焊層14a多的材料,又該防焊層14a,14b同樣會有分子聚縮的能力,所以該上側防焊層14b對於封裝基板的拉扯力量大於下側防焊層14a的拉扯力量,這將造成該封裝基板1之翹曲程度更加嚴重(如第1圖中所示之虛線)。
此外,習知技術中的防焊層及其所覆蓋的外層線路層並非共平面,這也影響到整體封裝的良率與密度。
因此,如何克服上述習知技術中之翹曲過多的問題,實已成目前亟欲解決的課題。
鑑於上述習知技術之封裝基板翹曲過多的缺失,本發明揭露一種封裝基板,係包括:第一介電層,係具有相對之第一表面與第二表面;複數第一電性接觸墊,係嵌埋和外露於該第一介電層之第一表面,以供半導體晶片接置於該第一電性接觸墊係上;第一線路層,係嵌埋和外露於該第一介電層之第二表面;複數第一金屬凸塊,係設於該第一介電層中,且各該第一金屬凸塊具有相對之第一端與第二端,該第一金屬凸塊之第二端係接置於該第一電性接觸墊上,該第一金屬凸塊之第一端則嵌入至該第一線路層中,且該第一線路層與第一介電層之間、及該第一線路層與第一金屬凸塊之間設有導電層;以及增層結構,係設於該第一線路層與第一介電層上,該增層結構的最外層具有複數第二電性接觸墊,以供外部電子裝置接置於該第二電性接觸墊上。
本發明揭露一種封裝基板之製法,係包括:提供一具有相對兩表面之承載板,且各該表面上形成有複數第一電性接觸墊,以供半導體晶片接置於該第一電性接觸墊上;於該第一電性接觸墊上形成第一金屬凸塊,該第一金屬凸塊具有相對之第一端與第二端,且該第二端係接置於該第一電性接觸墊上;於該承載板的表面、第一電性接觸墊與第一金屬凸塊上覆蓋第一介電層,且該第一介電層具有複數第一開槽,以外露該第一金屬凸塊之第一端的頂表面與側表面;於該第一介電層與第一金屬凸塊之第一端上形成導電層;於該導電層上形成金屬層;移除該金屬層與導電層高於該第一介電層頂表面的部分,而於該第一開槽中構成第一線路層;於該第一線路層與第一介電層上形成增層結構,而構成一上下成對的整版面封裝基板,該增層結構的最外層具有複數第二電性接觸墊,以供外部電子裝置接置於該第二電性接觸墊上;以及移除該承載板而分離該上下成對的整版面封裝基板,以成為兩個整版面封裝基板。
由上可知,本發明的封裝基板係由用以接置晶片的一側製作到用以連接外部電子元件的一側,這樣會造成最終置晶側朝上的整體封裝基板呈「反微笑」的形狀;但是又由於第一介電層(最上層介電層)被移除的面積小於最下層介電層,所以又會產生使封裝基板呈「微笑」形狀的應力,最終此微笑與反微笑的應力將相互抵銷,使得整體封裝基板較為平整。
此外,本發明所製作的封裝基板在置晶側係電性接觸墊與介電層齊平於表面,所以能增加電性接觸墊的密度,而有利於高密度封裝製程。
而且,本發明係以介電層來取代習知如綠漆之防焊層,使得封裝基板中的各層的材質均勻且單純化,而有助於整體封裝基板更為穩定與平整,並提升良率。
再者,本發明之金屬凸塊製程不需使用傳統之雷射開孔方式,雖然雷射可以透過調整來提高整體速度,但是畢竟雷射一次只能形成一個開孔,因此本發明之同時形成複數金屬凸塊的方式能有效減少製程時間,並降低成本。又,本發明係將金屬凸塊嵌入至線路層中,故能提升其結合之可靠度。
以下藉由特定的具體實施例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知,本說明書所附圖式所繪示之結構、比例、大小等,均僅用以配合說明書所揭示之內容,以供熟悉此技藝之人士之瞭解與閱讀,並非用以限定本發明可實施之限定條件,故不具技術上之實質意義,任何結構之修飾、比例關係之改變或大小之調整,在不影響本發明所能產生之功效及所能達成之目的下,均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時,本說明書中所引用之如「上」及「一」等之用語,亦僅為便於敘述之明瞭,而非用以限定本發明可實施之範圍,其相對關係之改變或調整,在無實質變更技術內容下,當亦視為本發明可實施之範疇。
第一實施例
請參閱第2A至2O圖,係本發明之封裝基板暨其應用例及其製法的第一實施例之剖視圖。
如第2A圖所示,提供一具有相對兩表面20a之承載板20,且各該表面20a上形成有複數第一電性接觸墊22,以供半導體晶片28接置於該第一電性接觸墊22上(請參照第2O圖),以本實施例來說,該承載板20復可包括支持層201與設於該支持層201兩表面上的中介層202,以令該第一電性接觸墊22形成於該中介層202上。
如第2B圖所示,於該第一電性接觸墊22上形成第一金屬凸塊23,該第一金屬凸塊23具有相對之第一端23a與第二端23b,且該第二端23b係接置於該第一電性接觸墊22上。
於本實施例中,形成該第一金屬凸塊23之材料可為銅、鎳、錫、金、銀或銅錫合金,且以加成法、半加成法(SAP)、減成法、電鍍、無電鍍沉積(electroless plating deposit)、化學沉積或印刷之方式形成該第一金屬凸塊23。然而,有關形成金屬凸塊之方式與材料種類繁多,並不限於上述。
如第2C圖所示,於該承載板20的表面20a、第一電性接觸墊22與第一金屬凸塊23上覆蓋第一介電層24。
如第2D圖所示,於該第一介電層24中形成有複數第一開槽240,以外露該第一金屬凸塊23之第一端23a的頂表面與側表面。
如第2E圖所示,於該第一介電層24與第一金屬凸塊23之第一端23a上形成導電層25。
如第2F圖所示,於該導電層25上形成金屬層26。
如第2G圖所示,移除該金屬層26與導電層25高於該第一介電層24頂表面的部分,而於該第一開槽240中構成第一線路層261。
要補充說明的是,該第一線路層261除了以前述之電鍍方式來形成之外,亦可使用下述方式來形成:首先,於如第2C圖之結構上形成遮罩層(未圖示),再以雷射來圖案化該遮罩層並形成如第2D圖之該第一開槽240,接著,全面性地形成活化層(未圖示),形成該活化層的方法有多種,而在本實施例中,該活化層可以是經由浸鍍而形成,詳細而言,其可浸泡於含有複數金屬顆粒的化學溶液中,而該等金屬顆粒可以附著在該遮罩層、該第一開槽240表面、及外露之該第一端23a的頂表面與側表面,進而形成該活化層,其中,該金屬顆粒例如是鈀顆粒、鉑顆粒、金顆粒或銀顆粒,且該鈀顆粒可以來自於氯化物錫鈀膠體或硫酸鈀螯合物(chelator),接著,移除該遮罩層及其上的該活化層,最後,藉由化學鍍(即無電電鍍(electroless plating))方式以於該第一開槽240中的該活化層上形成如第2G圖之該第一線路層261。又本發明中之嵌埋線路均可應用前述之線路形成方式,故將不再於下文中重複說明。
如第2H至2L圖所示,重複進行第2B至2G圖的動作,依序形成第二金屬凸塊271與第二介電層272,其中形成該第二金屬凸塊271之方法可參考前述形成該第一金屬凸塊23之方法,再於該第二介電層272中形成外露該第二金屬凸塊271之第三端271a的頂表面與側表面的複數第二開槽272a,且於該第二開槽272a中形成第二線路層273,並可視需要繼續形成該第二金屬凸塊271、第二介電層272與第二線路層273,以於該第一線路層261與第一介電層24上形成增層結構27,該增層結構27係包括至少一第二介電層272、嵌埋和外露於該第二介電層272表面之第二線路層273、及複數形成於該第二介電層272中並電性連接該第一線路層261與第二線路層273或電性連接該等第二線路層273之第二金屬凸塊271,該第二金屬凸塊271具有相對之第三端271a與第四端271b,該第二金屬凸塊271之第三端271a嵌入至該第二線路層273中,且最外層之該第二線路層273具有該等第二電性接觸墊273a,如此則構成一上下成對的整版面封裝基板2,且該增層結構27的最外層復可具有複數第二電性接觸墊273a,以供外部電子裝置接置於該第二電性接觸墊273上,至此即構成一上下成對的整版面封裝基板2。
要注意的是,雖然在該增層結構27中並未圖示出導電層,但是應理解本實施例的該第二線路層273可藉由該導電層的電鍍及後續的研磨程序而形成(即類似第2E至2G圖的步驟)。
如第2M圖所示,移除該承載板20而分離該上下成對的整版面封裝基板2,以成為兩個整版面封裝基板2’。
如第2N圖所示,進行切單(singulation)製程,以得到複數個封裝基板2”。
如第2O圖所示,於該第一電性接觸墊22上封裝接置半導體晶片28,並於該第二電性接觸墊273a上形成焊球29。
要注意的是,本實施例係先切割成該等封裝基板2”後,再接置該半導體晶片28;但是當然也可先接置該半導體晶片28,最後再進行切割。
第二實施例
請參閱第3A至3E圖,係本發明之封裝基板暨其應用例及其製法的第二實施例之剖視圖。
本實施例大致上相同於第一實施例,其主要的不同點在於增層結構的結構與製法。
具體而言,本實施例之增層結構31之製程係先形成第二介電層311,再於該第二介電層311中形成盲孔311a與第二開槽311b,並於該盲孔311a與第二開槽311b中分別形成導電盲孔312與第二線路層313;也就是本實施例的增層結構31係包括至少一第二介電層311、嵌埋和外露於該第二介電層311表面之第二線路層313、及複數形成於該第二介電層311中並電性連接該第一線路層261與第二線路層313或電性連接該等第二線路層313之導電盲孔312,且最外層之該第二線路層313具有該等第二電性接觸墊313a。
第三實施例
請參閱第3A’至3D’圖,係本發明之封裝基板及其製法的第三實施例之剖視圖。
本實施例大致上相同於第二實施例,其主要的不同點在於本實施例的增層結構31’的第二線路層313’並未嵌埋於第二介電層311’中。
詳而言之,本實施例之增層結構31’之製程係先形成該第二介電層311’,再於該第二介電層311’中形成盲孔311a’,並於該盲孔311a’中與該第二介電層311’上分別形成導電盲孔312’與該第二線路層313’;也就是本實施例的增層結構31’係包括至少一第二介電層311’、形成於該第二介電層311’上之第二線路層313’、及複數形成於該第二介電層311’中並電性連接該第一線路層261與第二線路層313’或電性連接該等第二線路層313’之導電盲孔312’,且最外層之該第二線路層313’具有該等第二電性接觸墊313a’。
本發明復提供一種封裝基板,係包括:第一介電層24,係具有相對之第一表面24a與第二表面24b;複數第一電性接觸墊22,係嵌埋和外露於該第一介電層24之第一表面24a,以供半導體晶片28接置於該第一電性接觸墊22上;第一線路層261,係嵌埋和外露於該第一介電層24之第二表面24b;複數第一金屬凸塊23,係設於該第一介電層24中,且各該第一金屬凸塊23具有相對之第一端23a與第二端23b,該第一金屬凸塊23之第二端23b係接置於該第一電性接觸墊22上,該第一金屬凸塊23之第一端23a則嵌入至該第一線路層261中,且該第一線路層261與第一介電層24之間、及該第一線路層261與第一金屬凸塊23之間設有導電層25;以及增層結構27,31,31’,係設於該第一線路層261與第一介電層24上,該增層結構27,31,31’的最外層具有複數第二電性接觸墊273a,313a,313a’,以供外部電子裝置接置於該第二電性接觸墊273a,313a,313a’上。
於前述之封裝基板中,該增層結構27係包括至少一第二介電層272、嵌埋和外露於該第二介電層272表面之第二線路層273、及複數設於該第二介電層272中並電性連接該第一線路層261與第二線路層273或電性連接該等第二線路層273之第二金屬凸塊271,該第二金屬凸塊271具有相對之第三端271a與第四端271b,該第二金屬凸塊271之第三端271a嵌入至該第二線路層273中,且最外層之該第二線路層273具有該等第二電性接觸墊273a。
依上所述之封裝基板,該增層結構31係包括至少一第二介電層311、嵌埋和外露於該第二介電層311表面之第二線路層313、及複數設於該第二介電層311中並電性連接該第一線路層261與第二線路層313或電性連接該等第二線路層313之導電盲孔312,且最外層之該第二線路層313具有該等第二電性接觸墊313a。
所述之封裝基板中,該增層結構31’係包括至少一第二介電層311’、設於該第二介電層311’上之第二線路層313’、及複數設於該第二介電層311’中並電性連接該第一線路層261與第二線路層313’或電性連接該等第二線路層313’之導電盲孔312’,且最外層之該第二線路層313’具有該等第二電性接觸墊313a’。
要補充說明的是,本說明書中所述之外部電子裝置可為電路板或其他封裝結構。
綜上所述,本發明的封裝基板係由用以接置晶片的一側製作到用以連接外部電子元件的一側,這樣會造成最終置晶側朝上的整體封裝基板呈「反微笑」的形狀;但是又由於第一介電層(最上層介電層)被移除的面積小於最下層介電層,所以又會產生使封裝基板呈「微笑」形狀的應力,最終此微笑與反微笑的應力將相互抵銷,使得整體封裝基板較為平整。
此外,本發明所製作的封裝基板在置晶側係電性接觸墊與介電層齊平於表面,所以能增加電性接觸墊的密度,而有利於高密度封裝製程。
而且,本發明係以介電層來取代習知如綠漆之防焊層,使得封裝基板中的各層的材質均勻且單純化,而有助於整體封裝基板更為穩定與平整,並提升良率。
再者,本發明之金屬凸塊製程不需使用傳統之雷射開孔方式,雖然雷射可以透過調整來提高整體速度,但是畢竟雷射一次只能形成一個開孔,因此本發明之同時形成複數金屬凸塊的方式能有效減少製程時間,並降低成本。又,藉由將金屬凸塊嵌入至線路層中,可使得該線路層與該金屬凸塊之間的接觸面積增加,所以兩者之間的結合性較佳,進而能提升整體可靠度。
上述實施例係用以例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修改。因此本發明之權利保護範圍,應如後述之申請專利範圍所列。
1,2”,3”...封裝基板
10...核心板
100...內層線路
11,261...第一線路層
12...線路增層結構
120a,24...第一介電層
120b,272,311,311’...第二介電層
120c...第三介電層
120d...第四介電層
121,273,313,313’...第二線路層
122,312,312’...導電盲孔
13a,13b...金屬凸塊
14a,14b...防焊層
140a,140b...開孔
15a,15b,29...焊球
2...上下成對的整版面封裝基板
2’,3’...整版面封裝基板
20...承載板
20a...表面
201...支持層
202...中介層
22...第一電性接觸墊
23...第一金屬凸塊
23a...第一端
23b...第二端
24a...第一表面
24b...第二表面
240...第一開槽
25...導電層
26...金屬層
27,31,31’...增層結構
271...第二金屬凸塊
271a...第三端
271b...第四端
272a,311b...第二開槽
273a,313a,313a’...第二電性接觸墊
28...半導體晶片
311a,311a’...盲孔
第1圖係為習知無核心層之封裝基板的剖視示意圖;
第2A至2O圖係本發明之封裝基板暨其應用例及其製法的第一實施例之剖視圖;
第3A至3E圖係本發明之封裝基板暨其應用例及其製法的第二實施例之剖視圖;以及
第3A’至3D’圖係本發明之封裝基板及其製法的第三實施例之剖視圖。
22...第一電性接觸墊
23...第一金屬凸塊
23a...第一端
23b...第二端
24...第一介電層
24a...第一表面
24b...第二表面
25...導電層
261...第一線路層
27...增層結構
271...第二金屬凸塊
271a...第三端
271b...第四端
272...第二介電層
273...第二線路層
273a...第二電性接觸墊
2”...封裝基板
Claims (10)
- 一種封裝基板,係包括:第一介電層,係具有相對之第一表面與第二表面及複數第一開槽;複數第一電性接觸墊,係嵌埋和外露於該第一介電層之第一表面,以供半導體晶片接置於該第一電性接觸墊上;第一線路層,係嵌埋和外露於該第一介電層之第二表面;複數第一金屬凸塊,係設於該第一介電層中,且各該第一金屬凸塊具有相對之第一端與第二端,該第一金屬凸塊之第二端係接置於該第一電性接觸墊上,該第一金屬凸塊之第一端的頂表面與側表面則嵌入至該第一線路層中,且該第一線路層與第一介電層之間、及該第一線路層與第一金屬凸塊之第一端的頂表面與側表面之間設有導電層,其中,該第一介電層之第一開槽外露該第一金屬凸塊之第一端的頂表面與側表面,該第一金屬凸塊之第一端的頂表面凸出於該第一開槽之底部;以及增層結構,係設於該第一線路層與第一介電層上,該增層結構的最外層具有複數第二電性接觸墊,以供外部電子裝置接置於該第二電性接觸墊上。
- 如申請專利範圍第1項所述之封裝基板,其中,該增層結構係包括至少一第二介電層、嵌埋和外露於該第二介電層表面之第二線路層、及複數設於該第二介電層中並 電性連接該第一線路層與第二線路層或電性連接該等第二線路層之第二金屬凸塊,該第二金屬凸塊具有相對之第三端與第四端,該第二金屬凸塊之第三端嵌入至該第二線路層中,且最外層之該第二線路層具有該等第二電性接觸墊。
- 如申請專利範圍第1項所述之封裝基板,其中,該增層結構係包括至少一第二介電層、嵌埋和外露於該第二介電層表面之第二線路層、及複數設於該第二介電層中並電性連接該第一線路層與第二線路層或電性連接該等第二線路層之導電盲孔,且最外層之該第二線路層具有該等第二電性接觸墊。
- 如申請專利範圍第1項所述之封裝基板,其中,該增層結構係包括至少一第二介電層、設於該第二介電層上之第二線路層、及複數設於該第二介電層中並電性連接該第一線路層與第二線路層或電性連接該等第二線路層之導電盲孔,且最外層之該第二線路層具有該等第二電性接觸墊。
- 一種封裝基板之製法,係包括:提供一具有相對兩表面之承載板,且各該表面上形成有複數第一電性接觸墊,以供半導體晶片接置於該第一電性接觸墊上;於該第一電性接觸墊上形成第一金屬凸塊,該第一金屬凸塊具有相對之第一端與第二端,且該第二端係接置於該第一電性接觸墊上;於該承載板的表面、第一電性接觸墊與第一金屬凸塊 上覆蓋第一介電層,且該第一介電層具有複數第一開槽以外露該第一金屬凸塊之第一端的頂表面與側表面,該第一金屬凸塊之第一端的頂表面凸出於該第一開槽之底部;於該第一介電層與第一金屬凸塊之第一端的頂表面與側表面上形成導電層;於該導電層上形成金屬層;移除該金屬層與導電層高於該第一介電層頂表面的部分,而於該第一開槽中構成第一線路層,該第一金屬凸塊之第一端的頂表面與側表面嵌入至該第一線路層中;於該第一線路層與第一介電層上形成增層結構,而構成一上下成對的整版面封裝基板,該增層結構的最外層具有複數第二電性接觸墊,以供外部電子裝置接置於該第二電性接觸墊上;以及移除該承載板而分離該上下成對的整版面封裝基板,以成為兩個整版面封裝基板。
- 如申請專利範圍第5項所述之封裝基板之製法,其中,該承載板復包括支持層與設於該支持層兩表面上的中介層,以令該第一電性接觸墊與第一介電層形成於該中介層上。
- 如申請專利範圍第5項所述之封裝基板之製法,其中,該增層結構係包括至少一第二介電層、嵌埋和外露於該第二介電層表面之第二線路層、及複數形成於該第二介電層中並電性連接該第一線路層與第二線路層或電性連接該等第二線路層之第二金屬凸塊,該第二金屬凸塊具有相對之第三端與第四端,該第二金屬凸塊之第三端嵌 入至該第二線路層中,且最外層之該第二線路層具有該等第二電性接觸墊。
- 如申請專利範圍第7項所述之封裝基板之製法,其中,該增層結構之製程係先形成該第二金屬凸塊,並形成該第二介電層,再於該第二介電層中形成外露該第二金屬凸塊之第三端的頂表面與側表面的複數第二開槽,且於該第二開槽中形成該第二線路層。
- 如申請專利範圍第5項所述之封裝基板之製法,其中,該增層結構係包括至少一第二介電層、嵌埋和外露於該第二介電層表面之第二線路層、及複數形成於該第二介電層中並電性連接該第一線路層與第二線路層或電性連接該等第二線路層之導電盲孔,且最外層之該第二線路層具有該等第二電性接觸墊。
- 如申請專利範圍第5項所述之封裝基板之製法,其中,該增層結構係包括至少一第二介電層、形成於該第二介電層上之第二線路層、及複數形成於該第二介電層中並電性連接該第一線路層與第二線路層或電性連接該等第二線路層之導電盲孔,且最外層之該第二線路層具有該等第二電性接觸墊。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW100124360A TWI473551B (zh) | 2011-07-08 | 2011-07-08 | 封裝基板及其製法 |
CN201110215625.6A CN102867799B (zh) | 2011-07-08 | 2011-07-25 | 封装基板及其制造方法 |
US13/542,928 US8624382B2 (en) | 2011-07-08 | 2012-07-06 | Packaging substrate and method of fabricating the same |
US14/097,656 US9070616B2 (en) | 2011-07-08 | 2013-12-05 | Method of fabricating packaging substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW100124360A TWI473551B (zh) | 2011-07-08 | 2011-07-08 | 封裝基板及其製法 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201304641A TW201304641A (zh) | 2013-01-16 |
TWI473551B true TWI473551B (zh) | 2015-02-11 |
Family
ID=47438152
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW100124360A TWI473551B (zh) | 2011-07-08 | 2011-07-08 | 封裝基板及其製法 |
Country Status (3)
Country | Link |
---|---|
US (2) | US8624382B2 (zh) |
CN (1) | CN102867799B (zh) |
TW (1) | TWI473551B (zh) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104835749A (zh) * | 2014-02-11 | 2015-08-12 | 东琳精密股份有限公司 | 半导体封装结构及其制造方法 |
TWI581386B (zh) * | 2014-06-16 | 2017-05-01 | 恆勁科技股份有限公司 | 封裝裝置及其製作方法 |
TWI474417B (zh) * | 2014-06-16 | 2015-02-21 | Phoenix Pioneer Technology Co Ltd | 封裝方法 |
TWI534968B (zh) * | 2014-06-17 | 2016-05-21 | 恆勁科技股份有限公司 | 封裝基板、覆晶封裝電路及其製作方法 |
US9412624B1 (en) | 2014-06-26 | 2016-08-09 | STATS ChipPAC Pte. Ltd. | Integrated circuit packaging system with substrate and method of manufacture thereof |
US9502267B1 (en) | 2014-06-26 | 2016-11-22 | STATS ChipPAC Pte. Ltd. | Integrated circuit packaging system with support structure and method of manufacture thereof |
CN105448883B (zh) * | 2014-08-12 | 2017-11-24 | 碁鼎科技秦皇岛有限公司 | 芯片封装基板及、芯片封装结构及二者之制作方法 |
TWI571598B (zh) * | 2015-01-15 | 2017-02-21 | 旭德科技股份有限公司 | 照明裝置 |
KR101672641B1 (ko) * | 2015-07-01 | 2016-11-03 | 앰코 테크놀로지 코리아 주식회사 | 반도체 디바이스의 제조 방법 및 이에 따른 반도체 디바이스 |
WO2020000414A1 (en) * | 2018-06-29 | 2020-01-02 | Intel Corporation | Coupling mechanisms for substrates, semiconductor packages, and/or printed circuit boards |
CN114597193A (zh) * | 2020-12-07 | 2022-06-07 | 群创光电股份有限公司 | 电子装置的重布线层结构及其制作方法 |
CN114745862A (zh) * | 2021-01-07 | 2022-07-12 | 欣兴电子股份有限公司 | 线路板及其制作方法 |
US11621217B2 (en) * | 2021-01-15 | 2023-04-04 | Advanced Semiconductor Engineering, Inc. | Substrate structure and semiconductor package structure |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW201002166A (en) * | 2008-06-18 | 2010-01-01 | Phoenix Prec Technology Corp | Printed circuit board and fabrication method thereof |
TW201041469A (en) * | 2009-05-12 | 2010-11-16 | Phoenix Prec Technology Corp | Coreless packaging substrate, carrier thereof, and method for manufacturing the same |
Family Cites Families (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5886877A (en) * | 1995-10-13 | 1999-03-23 | Meiko Electronics Co., Ltd. | Circuit board, manufacturing method therefor, and bump-type contact head and semiconductor component packaging module using the circuit board |
EP0774888B1 (en) * | 1995-11-16 | 2003-03-19 | Matsushita Electric Industrial Co., Ltd | Printed wiring board and assembly of the same |
US6187652B1 (en) * | 1998-09-14 | 2001-02-13 | Fujitsu Limited | Method of fabrication of multiple-layer high density substrate |
TW512467B (en) * | 1999-10-12 | 2002-12-01 | North Kk | Wiring circuit substrate and manufacturing method therefor |
WO2002061827A1 (fr) * | 2001-01-31 | 2002-08-08 | Sony Corporation | DISPOSITIF à SEMI-CONDUCTEUR ET SON PROCEDE DE FABRICATION |
JP3861669B2 (ja) * | 2001-11-22 | 2006-12-20 | ソニー株式会社 | マルチチップ回路モジュールの製造方法 |
JP4044769B2 (ja) * | 2002-02-22 | 2008-02-06 | 富士通株式会社 | 半導体装置用基板及びその製造方法及び半導体パッケージ |
JP3910908B2 (ja) * | 2002-10-29 | 2007-04-25 | 新光電気工業株式会社 | 半導体装置用基板及びこの製造方法、並びに半導体装置 |
US7164197B2 (en) * | 2003-06-19 | 2007-01-16 | 3M Innovative Properties Company | Dielectric composite material |
JP3961537B2 (ja) * | 2004-07-07 | 2007-08-22 | 日本電気株式会社 | 半導体搭載用配線基板の製造方法、及び半導体パッケージの製造方法 |
JP4534062B2 (ja) * | 2005-04-19 | 2010-09-01 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP4819471B2 (ja) * | 2005-10-12 | 2011-11-24 | 日本電気株式会社 | 配線基板及び配線基板を用いた半導体装置並びにその製造方法 |
JP2007109825A (ja) * | 2005-10-12 | 2007-04-26 | Nec Corp | 多層配線基板、多層配線基板を用いた半導体装置及びそれらの製造方法 |
TWI341002B (en) * | 2007-02-09 | 2011-04-21 | Unimicron Technology Corp | Coreless flip-chip packing substrate and method for making coreless packing substrate |
KR101551898B1 (ko) * | 2007-10-05 | 2015-09-09 | 신꼬오덴기 고교 가부시키가이샤 | 배선 기판, 반도체 장치 및 이들의 제조 방법 |
EP2068361A1 (en) * | 2007-12-04 | 2009-06-10 | Phoenix Precision Technology Corporation | Packaging substrate having chip embedded therein and manufacturing method thereof |
US7964965B2 (en) * | 2008-03-31 | 2011-06-21 | Intel Corporation | Forming thick metal interconnect structures for integrated circuits |
US8044499B2 (en) * | 2008-06-10 | 2011-10-25 | Semiconductor Energy Laboratory Co., Ltd. | Wiring substrate, manufacturing method thereof, semiconductor device, and manufacturing method thereof |
KR101077380B1 (ko) * | 2009-07-31 | 2011-10-26 | 삼성전기주식회사 | 인쇄회로기판 및 그 제조방법 |
WO2011118572A1 (ja) * | 2010-03-23 | 2011-09-29 | 日本電気株式会社 | 半導体装置の製造方法 |
US8508037B2 (en) * | 2010-12-07 | 2013-08-13 | Intel Corporation | Bumpless build-up layer and laminated core hybrid structures and methods of assembling same |
JP5680401B2 (ja) * | 2010-12-22 | 2015-03-04 | 新光電気工業株式会社 | 配線基板及び半導体パッケージ |
-
2011
- 2011-07-08 TW TW100124360A patent/TWI473551B/zh active
- 2011-07-25 CN CN201110215625.6A patent/CN102867799B/zh active Active
-
2012
- 2012-07-06 US US13/542,928 patent/US8624382B2/en active Active
-
2013
- 2013-12-05 US US14/097,656 patent/US9070616B2/en active Active - Reinstated
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW201002166A (en) * | 2008-06-18 | 2010-01-01 | Phoenix Prec Technology Corp | Printed circuit board and fabrication method thereof |
TW201041469A (en) * | 2009-05-12 | 2010-11-16 | Phoenix Prec Technology Corp | Coreless packaging substrate, carrier thereof, and method for manufacturing the same |
Also Published As
Publication number | Publication date |
---|---|
US20140090794A1 (en) | 2014-04-03 |
TW201304641A (zh) | 2013-01-16 |
CN102867799A (zh) | 2013-01-09 |
US8624382B2 (en) | 2014-01-07 |
CN102867799B (zh) | 2015-12-16 |
US9070616B2 (en) | 2015-06-30 |
US20130009293A1 (en) | 2013-01-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI473551B (zh) | 封裝基板及其製法 | |
TWI463925B (zh) | 封裝基板及其製法 | |
US9484223B2 (en) | Coreless packaging substrate and method of fabricating the same | |
TWI495051B (zh) | 無核心層之封裝基板及其製法 | |
EP2654388B1 (en) | Semiconductor package, semiconductor apparatus and method for manufacturing semiconductor package | |
TWI587412B (zh) | 封裝結構及其製法 | |
TWI476888B (zh) | 嵌埋穿孔中介層之封裝基板及其製法 | |
TWI544599B (zh) | 封裝結構之製法 | |
TWI460834B (zh) | 嵌埋穿孔晶片之封裝結構及其製法 | |
TWI493671B (zh) | 具有支撐體的封裝基板及其製法、具有支撐體的封裝結構及其製法 | |
TWI594382B (zh) | 電子封裝件及其製法 | |
CN107403785B (zh) | 电子封装件及其制法 | |
TWI485815B (zh) | 半導體封裝件及其製法 | |
TWI389276B (zh) | 封裝基板結構及其製法 | |
TWI723414B (zh) | 電子封裝件及其製法 | |
TWI438880B (zh) | 嵌埋穿孔晶片之封裝結構及其製法 | |
TWI566330B (zh) | 電子封裝結構之製法 | |
KR20220150093A (ko) | 반도체 패키지 | |
TW201417225A (zh) | 封裝基板及其製法 | |
TWI612627B (zh) | 電子封裝件及其製法 | |
TWI614862B (zh) | 基板結構及其製法 | |
US20240170355A1 (en) | Electronic package and manufacturing method thereof | |
TWI805216B (zh) | 電子封裝件及其基板結構 | |
TWI720735B (zh) | 封裝結構及其製造方法 | |
TW202422841A (zh) | 電子封裝件及其製法 |