CN107403785B - 电子封装件及其制法 - Google Patents

电子封装件及其制法 Download PDF

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Publication number
CN107403785B
CN107403785B CN201610382592.7A CN201610382592A CN107403785B CN 107403785 B CN107403785 B CN 107403785B CN 201610382592 A CN201610382592 A CN 201610382592A CN 107403785 B CN107403785 B CN 107403785B
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layer
circuit
circuit structure
conductive
electronic
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CN107403785A (zh
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程吕义
李宏元
赖杰隆
彭仕良
吕长伦
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Abstract

一种电子封装件及其制法，包括：具有相对的第一表面及第二表面的线路结构、设于该第一表面上的金属层、设于该金属层上的电子元件、包覆该电子元件的封装层、设于该第二表面上的多个导电柱、以及包覆该些导电柱的绝缘层。藉由于该线路结构的表面上形成导电柱，并以绝缘层包覆该导电柱，故能依深宽比需求制作各种尺寸的导电柱，使终端产品达到轻、薄、短、小的需求。

Description

电子封装件及其制法
技术领域
本发明有关一种电子封装件，尤指一种具轻薄短小化的电子封装件及其制法。
背景技术
随着电子产业的蓬勃发展，电子产品也逐渐迈向多功能、高性能的趋势，其中应用于芯片封装领域的技术包含有：芯片尺寸构装(Chip Scale Package，简称CSP)、芯片直接贴附封装(Direct Chip Attached，简称DCA)或多芯片模组封装(Multi－Chip Module，简称MCM)等覆晶型态的封装模组，或将芯片立体堆迭化整合为三维集成电路(3D IC)芯片堆迭技术等。
图1为悉知3D IC)芯片堆迭的半导体封装件1的剖面示意图，其包含有一硅中介板(Through Silicon interposer，简称TSI)10，该硅中介板10具有相对的置晶侧10a与转接侧10b、及连通该置晶侧10a与转接侧10b的多个导电硅穿孔(Through-silicon via，简称TSV)100，且该转接侧10b上具有多个线路重布层(Redistribution layer，简称RDL)101，以将间距较小的半导体芯片19的电极垫190藉由多个焊锡凸块102电性结合至该置晶侧10a上，再以底胶192包覆该些焊锡凸块102，且形成封装胶体18于该硅中介板10上，以覆盖该半导体芯片19，另于该线路重布层101上藉由多个如凸块的导电元件103电性结合间距较大的封装基板17的焊垫170，并以底胶172包覆该些导电元件103。
此外，制作该半导体封装件1时，先将该半导体芯片19置放于该硅中介板10上，再将该硅中介板10以该些导电元件103接置于该封装基板17上，之后形成该封装胶体18。
此外，于后续应用该半导体封装件1的组装制程时，该半导体封装件1藉由该封装基板17下侧结合至一电路板(图略)上，以利用该些 导电硅穿孔100作为该半导体芯片19与该电路板之间讯号传递的介质。
然而，悉知半导体封装件1的制法中，使用该硅中介板10作为该半导体芯片19与该封装基板17之间讯号传递的介质，因需具备一定深宽比的控制(即该导电硅穿孔100的深宽比为100um/10um)，才能制作出适用的硅中介板10，因而往往需耗费大量制程时间及化学药剂的成本，进而提高制程难度及制作成本。
此外，该封装基板17具有含玻纤材料的核心层，致使该封装基板17厚度相当厚，因而不利于产品的轻薄短小化。
又，该些焊锡凸块102与导电元件103接置该硅中介板10时已进行回焊(reflow)，故当形成该封装胶体18时，该硅中介板10容易因多次加热制程而造成其温度变化过大，致使该硅中介板10发生翘曲现象。
因此，如何克服上述悉知技术的种种问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述悉知技术的种种缺失，本发明提供一种电子封装件及其制法，能依深宽比需求制作各种尺寸的导电柱，使终端产品达到轻、薄、短、小的需求。
本发明的电子封装件，包括：线路结构，其具有相对的第一表面及第二表面，且该第一表面结合有第一线路层，该第二表面结合有第二线路层；金属层，其形成于该线路结构的第一表面上且电性连接该第一线路层；电子元件，其设于该线路结构的第一表面上且电性连接该金属层；封装层，其形成于该线路结构的第一表面上，以包覆该电子元件；多个导电柱，其设于该线路结构的第二表面上且电性连接该第二线路层；以及绝缘层，其形成于该线路结构的第二表面上，以包覆该些导电柱，且令该些导电柱的部分表面外露于该绝缘层。
本发明还提供一种电子封装件的制法，包括：提供一具有相对的第一表面及第二表面的线路结构，且该线路结构的第一表面结合有第一线路层，该第二表面结合有第二线路层；形成多个导电柱于该线路 结构的第二表面上，且该些导电柱电性连接该第二线路层；形成绝缘层于该线路结构的第二表面上，以令该绝缘层包覆该些导电柱；形成金属层于该线路结构的第一表面上，且该金属层电性连接该第一线路层；设置电子元件于该线路结构的第一表面上，且该电子元件电性连接该金属层；形成封装层于该线路结构的第一表面上，以包覆该电子元件；以及移除部分该绝缘层，以外露该导电柱的部分表面。
前述的电子封装件及其制法中，该第一线路层的最小线路宽度小于该第二线路层的最小线路宽度。
前述的电子封装件及其制法中，该金属层为图案化线路层。
前述的电子封装件及其制法中，该封装层的材质与该绝缘层的材质为相同或不相同。
前述的电子封装件及其制法中，该封装层可延伸至该线路结构的侧面。
前述的电子封装件及其制法中，该封装层接触该绝缘层。
前述的电子封装件及其制法中，还包括形成多个导电元件于该些导电柱上。
前述的电子封装件及其制法中，还包括接置于该些导电柱上的电子组件。
由上可知，本发明的电子封装件及其制法，主要藉由于该线路结构上直接长出该些导电柱，且以绝缘层包覆该些导电柱，因而不需形成如悉知硅穿孔，故能依深宽比需求制作各种尺寸的导电柱，使终端产品达到轻、薄、短、小的需求，且能提高产量并节省化学药剂费用支出。
此外，本发明的制法以该绝缘层取代悉知硅中介板，并利用该些导电柱作为该电子元件与电路板之间讯号传递的介质，故相较于悉知技术，本发明的制法无需制作TSV，因而大幅降低制程难度及制作成本。
又，相较于悉知技术，本发明的制法无需使用硅中介板，故不会发生悉知硅中介板因加热而发生翘曲的问题。
另外，藉由直接将高I/O功能的电子元件接置于该线路结构上，因而不需使用一含核心层的封装基板及一具TSV的硅中介板，故可减少该电子封装件的厚度。
附图说明
图1为悉知半导体封装件的剖面示意图；
图2A至图2G为本发明的电子封装件的制法的剖面示意图；
图2H为本发明的电子封装件后续应用的剖面示意图；以及
图3A至图3C为本发明的电子封装件的另一实施例的制法的剖面示意图。
符号说明
1 半导体封装件 10 硅中介板
10a 置晶侧 10b 转接侧
100 导电硅穿孔 101 线路重布层
102,230 焊锡凸块 103,25 导电元件
17 封装基板 170 焊垫
172,192 底胶 18 封装胶体
19 半导体芯片 190 电极垫
2,2’ 电子封装件 20 承载件
200 分隔层 21 线路结构
21’ 第一线路部 21” 第二线路部
21a 第一表面 21b 第二表面
21c 侧面 210 介电层
210’ 绝缘隔层 211 内部线路层
211’ 第一线路层 211” 第二线路层
212 凸块底下金属层 22 金属层
23 电子元件 24,24’ 封装层
26 导电柱 27 绝缘层
28 电子组件 30 整版面基板
300 切割道 9 电路板。
具体实施方式
以下藉由特定的具体实施例说明本发明的实施方式，熟悉此技艺的人士可由本说明书所揭示的内容轻易地了解本发明的其他优点及功 效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供熟悉此技艺的人士的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“第一”、“第二”及“一”等用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
图2A至图2G为本发明的电子封装件2的制法的剖面示意图。
如图2A所示，提供一具有一分隔层200的承载件20，再形成一线路结构21于该承载件20的分隔层200上。接着，形成多个导电柱26于该线路结构21上。
于本实施例中，该承载件20为半导体板体，例如虚设硅晶圆(dummy Si wafer)、玻璃或高分子板材，且该分隔层200为例如热化二氧化硅层(thermal SiO2 layer)或黏着层(较佳为有机黏着层)。
此外，该线路结构21可利用线路重布层(Redistribution layer，简称RDL)制程形成，且该线路结构21具有相对的第一表面21a与第二表面21b，并以该第一表面21a结合于该分隔层200上。
具体地，该线路结构21具有多个介电层210、形成于该介电层210中的内部线路层211、形成于该第一表面21a的介电层210上的第一线路层211’、及形成于该第二表面21b的介电层210上的第二线路层211”，其中，该第一线路层211’的最小线路宽度小于该第二线路层211”的最小线路宽度，且该第二线路层211”上形成有凸块底下金属层(Under BumpMetallurgy，简称UBM)212，以结合该些导电柱26。
又，考量线路的线宽变化，需于该承载件20上先形成细线宽的线路层(如0.7um)，再形成中线宽的线路层(如5um)，接着形成宽线宽的线路层(10um)，之后再做更宽的线路层，以此类推。此乃由于细线路层及其上的介电层平整度较平，如此往上作宽线路时，可符合 上层线路层平整度要求。反之，若于该承载件20的表面依序往上形成宽、中、细的线路层，由于底部的宽线路层平整度不够平整，会产生线路层的可靠度问题，故往上无法依序制作出中、细的线路层。
因此，较佳地，当所需的线路的线宽太小时(如小于或等于1um以下时)，可先以晶圆制程完成第一线路部21’的布线(含绝缘隔层210’)，再送至后端封装制程进行第二线路部21”的布线，使该线路结构21包含相迭的第一线路部21’与第二线路部21”，且该第一线路部21’结合该分隔层200。
然而，本发明的第一线路部21’可包括但不限于一定要用晶圆制程完成(如大于或等于1um以上时)。例如，由于晶圆制程的线路层用的介电层需以化学气相沉积(Chemicalvapor deposition，简称CVD)形成氮化硅或氧化硅，其成本较高，故可采用一般非晶圆制程方式形成线路，即采用成本较低的高分子介电层，如聚酰亚胺(Polyimide，简称PI)、聚对二唑苯(Polybenzoxazole，简称PBO)以涂布方式形成于线路之间进行绝缘。
另外，是以图案化方式(如电镀金属、沉积金属或蚀刻金属等)形成该导电柱26，以于该线路结构21的第二表面21b上形成如铜柱的金属柱。
如图2B所示，形成一绝缘层27于该线路结构21的第二表面21b上，以包覆该些导电柱26。
于本实施例中，形成该绝缘层27的材质为聚酰亚胺(polyimide，简称PI)、干膜(dry film)、环氧树脂(expoxy)或封装材。
如图2C所示，移除该承载件20，且使该分隔层200保留于该线路结构21上。
于本实施例中，当该承载件20为硅晶圆材质时，先研磨移除该承载件20的大部分材质，再利用蚀刻方式清除剩余该承载件20的材质，以保留该分隔层200，其中该分隔层200作为蚀刻停止层。当该承载件20为玻璃材质时，以加热方式或照光方式(如UV光)，使该分隔层200失去部分黏性，以移除该承载件20而保留该分隔层200，其中，该分隔层200作为黏着层使用。
如图2D所示，形成一金属层22于该分隔层200上，且该金属层 22电性连接该线路结构21的第一线路层211’。接着，选择性地对该金属层22与该线路结构21进行电性测试。
于本实施例中，该金属层22为例如以电镀方式制作，故会先形成导电层(图略)于该分隔层200上，且该金属层22为图案化线路层，其包含电性接触垫(pad)与导电迹线(trace)。然而，有关线路制程的方式繁多，如RDL制程，故于此不再赘述。
此外，先进行线路测试，待确认线路结构21与金属层22正常后，再接置良好晶粒(Known Good Die，简称KGD)，即后述的电子元件23，以防止最终封装件因线路结构21与金属层22制作瑕疵，发生良率不佳的问题。
如图2E所示，设置多个电子元件23于该线路结构21的第一表面21a上。接着，形成一封装层24于该线路结构21的第一表面21a上，以包覆该些电子元件23。
于本实施例中，该电子元件23为主动元件、被动元件或其组合者，其中，该主动元件为例如半导体芯片，而该被动元件为例如电阻、电容及电感。
此外，该电子元件23以覆晶方式电性连接该线路结构21。例如，该电子元件23藉由多个焊锡凸块230电性结合至该金属层22上。另外，该电子元件23也可以打线方式电性连接该金属层22。
又，形成该封装层24的材质为聚酰亚胺(PI)、干膜(dry film)、环氧树脂(expoxy)或封装材，且该封装层24与该绝缘层27的材质可为相同或不相同。
如图2F所示，移除部分该绝缘层27，以外露该导电柱26的部分表面。
于本实施例中，于该绝缘层27上进行整平制程，如研磨方式，使该导电柱26的外露表面齐平该绝缘层27的表面。于其它实施例中，可于该绝缘层27上进行开孔制程，使该导电柱26的表面外露于该绝缘层27的开孔。
此外，应可理解地，也可于该封装层24上进行整平制程或开孔制程，使该电子元件23的部分表面外露于该封装层24的表面。
又，可将该金属层22、导电柱26、绝缘层27与线路结构21视为 一封装基板。
如图2G所示，形成多个导电元件25于各该导电柱26上。
于本实施例中，该导电元件25为焊球、金属凸块或金属针等，其结合于各该导电柱26上以电性连接该第二线路层211”。
此外，该线路结构21的第二表面21b、该第二线路层211”与该导电柱26作为植球侧，使该电子封装件2可藉由该些导电元件25直接电性连接至一电路板9(如图2H所示)，而无需再藉由额外的硅中介板，故可降低制作成本，且可降低终端产品的整体厚度。
又，如图3C所示的电子封装件2’，该封装层24’可延伸至该线路结构21的侧面21c以接触该绝缘层27，使该封装层24’与该绝缘层27完整地包覆该线路结构21。具体地，如图3A所示，于图2D的制程，提供一由多个线路结构21所组成的整版面基板30，且藉由切除(diesaw)制程以于该线路结构21的第一表面21a上形成多个切割道300，由于该些切割道300位在该线路结构21四周，故于切割时顺便移除该线路结构21边缘，但未移除该绝缘层27；接着，如图3B所示，进行如图2E的制程，且令该封装层24’填入该些切割道300中，以包覆该线路结构21的侧面21c；最后，沿各该切割道300进行切单制程，以得到如图3C所示的电子封装件2’。
另外，于该些导电柱26上也可利用该导电元件25接置至少一电子组件28，且该电子组件28为主动元件、被动元件或其组合者，其中，该主动元件为例如半导体芯片，而该被动元件为例如电阻、电容及电感。具体地，于图3C中，该电子组件28以被动元件为例。因此，该电子封装件2’形成有第一与第二线路层211’,211”，故于该电子封装件2’的上、下两侧皆可接置电子零组件，因而能提升其电性功能。
应可理解地，于量产时，图2A的制程会采用由多个线路结构21所组成的整版面基板，以于形成多个导电元件25后，进行切单制程，而得到如图2G或图3C所示的电子封装件2,2’。
本发明的制法中藉由于该线路结构21上形成该导电柱26，且以绝缘层27包覆该些导电柱26，因而不需形成孔洞，故能依深宽比需求制作各种尺寸(如深宽比小)的导电柱26，使终端产品达到轻、薄、短、小的需求，且能提高产量(Throughput)并节省化学药剂费用支出。
此外，本发明的制法以该绝缘层27取代悉知硅中介板，并利用该些导电柱26作为该电路板9与该电子元件23之间讯号传递的介质，故相较于悉知技术，本发明的制法无需制作TSV，因而大幅降低制程难度及制作成本。
又，相较于悉知技术，本发明的制法无需使用硅中介板，故不会发生悉知硅中介板因加热而发生翘曲的问题。
另外，本发明的制法直接将高I/O功能的电子元件23接置于该线路结构21的第一线路层211’上，因而不需使用一含核心层的封装基板及一具有TSV的硅中介板，故可减少该电子封装件2,2’的厚度。
本发明还提供一种电子封装件2,2’，包括：一线路结构21、一金属层22、多个电子元件23、一封装层24,24’、多个导电柱26以及一绝缘层27。
所述的线路结构21具有相对的第一表面21a及第二表面21b，且该第一表面21a结合有第一线路层211’，该第二表面21b结合有第二线路层211”。
所述的金属层22形成于该线路结构21的第一表面21a上且电性连接该第一线路层211’。
所述的电子元件23设于该线路结构21的第一表面21a上且电性连接该金属层22。
所述的封装层24,24’形成于该线路结构21的第一表面21a上，以包覆该些电子元件23。
所述的导电柱26设于该线路结构21的第二表面21b上且电性连接该第二线路层211”。
所述的绝缘层27形成于该线路结构21的第二表面21b上，以包覆该些导电柱26，且令该些导电柱26的部分表面外露于该绝缘层27。
于一实施例中，该第一线路层211’的最小线路宽度小于该第二线路层211”的最小线路宽度。
于一实施例中，该金属层22为图案化线路层。
于一实施例中，该封装层24,24’的材质与该绝缘层27的材质为相同。
于一实施例中，该封装层24,24’的材质与该绝缘层27的材质为 不相同。
于一实施例中，该封装层24’接触该绝缘层27。
于一实施例中，该电子封装件2还包括多个导电元件25，其形成于该些导电柱26上。
于一实施例中，该电子封装件2’还包括至少一电子组件28，其接置于该些导电柱26上。
综上所述，本发明的电子封装件及其制法，藉由于该线路结构上直接长出该导电柱，且以该绝缘层包覆该些导电柱，因而不需形成孔洞，故能制作出深宽比较小的导电柱，使终端产品达到轻、薄、短、小的需求，且能提高产量，并节省化学药剂费用支出。
此外，藉由该绝缘层取代悉知硅中介板，并利用该些导电柱作为电路板与电子元件之间讯号传递的介质，故相较于悉知技术，本发明的制法无需制作TSV，因而大幅降低制程难度及制作成本。
又，本发明的制法无需使用硅中介板，故不会发生悉知硅中介板因加热而发生翘曲的问题。
另外，藉由直接将高I/O功能的电子元件接置于该线路结构上，因而不需使用一含核心层的封装基板及一具有TSV的硅中介板，故可减少该电子封装件的厚度。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟习此项技艺的人士均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (14)

1.一种电子封装件，其特征为，该电子封装件包括：
线路结构，其具有相对的第一表面及第二表面，该线路结构包含相迭的第一线路部与第二线路部，且该第一表面结合有该第一线路部的第一线路层，该第二表面结合有该第二线路部的第二线路层，该第一线路层的最小线路宽度小于该第二线路层的最小线路宽度，其中，该第一线路部的布线制程与该第二线路部的布线制程采用不同的线路宽度的规格，且该第一线路层的线路宽度小于或等于1um以下；
金属层，其形成于该线路结构的第一表面上且电性连接该第一线路层；
电子元件，其设于该线路结构的第一表面上且电性连接该金属层；
封装层，其形成于该线路结构的第一表面上且延伸至该线路结构的侧面，以包覆该电子元件；
多个导电柱，其设于该线路结构的第二表面上且电性连接该第二线路层；以及
绝缘层，其形成于该线路结构的第二表面上并接触该封装层，以包覆该多个导电柱，且令各该多个导电柱的部分表面外露于该绝缘层。
2.如权利要求1所述的电子封装件，其特征为，该金属层为图案化线路层。
3.如权利要求1所述的电子封装件，其特征为，该封装层的材质与该绝缘层的材质为相同。
4.如权利要求1所述的电子封装件，其特征为，该封装层的材质与该绝缘层的材质为不相同。
5.如权利要求1所述的电子封装件，其特征为，该电子封装件还包括形成于该多个导电柱上的多个导电元件。
6.如权利要求1所述的电子封装件，其特征为，该电子封装件还包括接置于该多个导电柱上的电子组件。
7.一种电子封装件的制法，其特征为，该制法包括：
提供一具有相对的第一表面及第二表面的线路结构，该线路结构包含相迭的第一线路部与第二线路部，且以晶圆制程形成该第一线路部，以封装制程形成该第二线路部，使该线路结构的第一表面结合有该第一线路部的第一线路层，该第二表面结合有该第二线路部的第二线路层，其中，该第一线路层的最小线路宽度小于该第二线路层的最小线路宽度；
形成多个导电柱于该线路结构的第二表面上，且该多个导电柱电性连接该第二线路层；
形成绝缘层于该线路结构的第二表面上，以令该绝缘层包覆该多个导电柱；
形成金属层于该线路结构的第一表面上，且该金属层电性连接该第一线路层；
设置电子元件于该线路结构的第一表面上，且该电子元件电性连接该金属层；
形成封装层于该线路结构的第一表面上，以包覆该电子元件；以及
移除部分该绝缘层，以外露各该导电柱的部分表面。
8.如权利要求7所述的电子封装件的制法，其特征为，该金属层为图案化线路层。
9.如权利要求7所述的电子封装件的制法，其特征为，该封装层的材质与该绝缘层的材质为相同。
10.如权利要求7所述的电子封装件的制法，其特征为，该封装层的材质与该绝缘层的材质为不相同。
11.如权利要求7所述的电子封装件的制法，其特征为，该封装层可延伸至该线路结构的侧面。
12.如权利要求7所述的电子封装件的制法，其特征为，该封装层接触该绝缘层。
13.如权利要求7所述的电子封装件的制法，其特征为，该制法还包括形成多个导电元件于该多个导电柱上。
14.如权利要求7所述的电子封装件的制法，其特征为，该制法还包括于该多个导电柱上接置电子组件。
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Publication number Priority date Publication date Assignee Title
TWI605557B (zh) * 2015-12-31 2017-11-11 矽品精密工業股份有限公司 電子封裝件及其製法與基板結構
CN109979890A (zh) * 2017-12-28 2019-07-05 凤凰先驱股份有限公司 电子封装件及其制法
KR102419893B1 (ko) * 2018-01-15 2022-07-12 삼성전자주식회사 보호 부재를 가지는 인쇄 회로 기판 및 이를 포함하는 반도체 패키지 제조 방법
US11342246B2 (en) * 2020-07-21 2022-05-24 Qualcomm Incorporated Multi-terminal integrated passive devices embedded on die and a method for fabricating the multi-terminal integrated passive devices
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US9252130B2 (en) * 2013-03-29 2016-02-02 Stats Chippac, Ltd. Methods of manufacturing flip chip semiconductor packages using double-sided thermal compression bonding
TWI541954B (zh) * 2013-08-12 2016-07-11 矽品精密工業股份有限公司 半導體封裝件及其製法
TWI543323B (zh) * 2014-08-12 2016-07-21 矽品精密工業股份有限公司 中介板及其製法
CN204216021U (zh) * 2014-09-28 2015-03-18 南通富士通微电子股份有限公司 晶圆级芯片封装结构
KR101672622B1 (ko) * 2015-02-09 2016-11-03 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
US9437536B1 (en) * 2015-05-08 2016-09-06 Invensas Corporation Reversed build-up substrate for 2.5D

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
利用激光直写技术在塑料基材上三维金属布线;陈蓓等;《印制电路信息》;20070310(第03期);44-47 *

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