CN114121869A - 电子封装件及其制法 - Google Patents
电子封装件及其制法 Download PDFInfo
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- CN114121869A CN114121869A CN202010938890.6A CN202010938890A CN114121869A CN 114121869 A CN114121869 A CN 114121869A CN 202010938890 A CN202010938890 A CN 202010938890A CN 114121869 A CN114121869 A CN 114121869A
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5385—Assembly of a plurality of insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
本发明涉及一种电子封装件及其制法,包括于包覆层中嵌埋线路板与线路块,且于该包覆层的相对两表面上形成线路结构,并将电子元件设于其中一线路结构上,以将该线路块与该线路板分隔嵌埋于该包覆层中,以分开电流传导路径,使该线路板不会有过热的情况,避免该线路板发生翘曲的问题,并且经由该线路块与该线路板分隔嵌埋于该包覆层中可提升该包覆层的结构强度。
Description
技术领域
本发明有关一种半导体装置,尤指一种具有复合式基板的电子封装件及其制法。
背景技术
随着电子产业的蓬勃发展,电子产品也逐渐迈向多功能、高性能的发展趋势。目前应用于芯片封装领域的技术繁多,例如芯片尺寸构装(Chip Scale Package,简称CSP)、芯片直接贴附封装(Direct Chip Attached,简称DCA)或多芯片模块封装(Multi-ChipModule,简称MCM)等覆晶型封装模块,或将芯片立体堆叠化整合为三维积体电路(3D IC)芯片堆叠模块。
图1为现有半导体封装件1的剖面示意图。首先,提供一具有相对的转接侧10a与置晶侧10b的硅中介板(Through Silicon interposer,简称TSI)10,且该硅中介板10具有多个连通该置晶侧10b与转接侧10a的导电硅穿孔(Through-silicon via,简称TSV)100,并于该置晶侧10b上形成一如RDL(redistribution layer)型的线路结构11以供接置一具有较小焊锡凸块150间距的半导体芯片15,再将该硅中介板10以其转接侧10a通过多个导电元件18设于一具有较大线距的封装基板13上,并使该封装基板13电性连接该些导电硅穿孔100。接着,形成封装胶体16于该封装基板13上,以令该封装胶体16包覆该半导体芯片15与该硅中介板10。最后,形成多个焊球12于该封装基板13的下侧植球垫130,以供接置于一电路板1’上。
现有半导体封装件1中,该半导体芯片15与该封装基板13之间经由该线路结构11进行电源/信号的传输。
然而,随着产品功能性需求大增,该半导体芯片15的功能需求也随的增加,故该半导体芯片15的接点(如焊锡凸块150)及该线路结构11的线路布设密度随的增高,于此情况下,RDL型线路结构11的体积过小,致使其结构强度极弱,因而容易受高温影响而产生翘曲(warpage),造成该线路结构11的线路断裂。
另一方面,若为了避免该线路结构11的线路断裂,需将该线路结构11的线路增宽,以经由线路的金属材强化其结构强度而避免产生翘曲,但该线路结构11将无法满足细线路的需求,因而难以提高该线路结构11的线路布设密度,导致无法配合该半导体芯片15的高密度(或多功能)的接点需求。
因此,如何克服上述现有技术的种种问题,实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的种种缺陷,本发明提供一种电子封装件及其制法,可提高结构强度。
本发明的电子封装件,包括:包覆层,其具有相对的第一表面与第二表面;线路板,其嵌埋于该包覆层中;线路块,其嵌埋于该包覆层中;第一线路结构,其形成于该包覆层的第一表面上且电性连接该线路板与线路块;电子元件,其设于该第一线路结构上且电性连接该第一线路结构;以及第二线路结构,其形成于该包覆层的第二表面上且电性连接该线路板与线路块。
本发明还提供一种电子封装件的制法,包括:于一承载件上分开设置一线路板与至少一线路块;形成包覆层于该承载件以包覆该线路板与该线路块,其中,该包覆层具有相对的第一表面与第二表面,且该包覆层以其第二表面结合至该承载件上;形成第一线路结构于该包覆层的第一表面上,以令该第一线路结构电性连接该线路板与线路块;设置电子元件于该第一线路结构上,且令该电子元件电性连接该第一线路结构;移除该承载件;以及形成第二线路结构于该包覆层的第二表面上,且令该第二线路结构电性连接该线路板与线路块。
前述的电子封装件及其制法中,该包覆层中嵌埋有多个相互分开配置的该线路块。
前述的电子封装件及其制法中,该线路板与该线路块为相互分隔。
前述的电子封装件及其制法中,该线路板设有用以配置该线路块的容置空间,且该包覆层还形成于该容置空间中以包覆该线路块。
前述的电子封装件及其制法中,该线路板形成有多个沟槽。例如,该多个沟槽形成十字状沟槽结构。进一步,该包覆层还形成于该沟槽中。
前述的电子封装件及其制法中,该包覆层中还嵌埋有多个导电结构。
前述的电子封装件及其制法中,还包括以封装层包覆该电子元件。
前述的电子封装件及其制法中,还包括形成多个导电元件于该第二线路结构上。
前述的电子封装件及其制法中,该线路块具有至少一绝缘体或至少一半导体基部、以及至少一嵌埋于该绝缘体或该半导体基部中的导电柱。例如,该绝缘体或该半导体基部的相对两侧的至少一者上形成有一电性连接该导电柱的线路部。
前述的电子封装件及其制法中,该绝缘体为封装材,且该半导体基部含有硅。
前述的电子封装件及其制法中,该线路板为无核心层的线路结构。
前述的电子封装件及其制法中,该第一线路结构上设有多个该电子元件,且多个该电子元件的至少其中两者之间具有间隙,以令该线路块对应位于该间隙处,使该线路块电性桥接两该电子元件。
由上可知,本发明的电子封装件及其制法中,主要经由将该线路块与该线路板分隔嵌埋于该包覆层中,以分开电流传导路径,故相比于现有技术,本发明的线路板不会有过热的情况,因而能避免该线路板发生翘曲的问题,进而避免该线路板的线路层发生断裂的问题,并且经由该线路块与该线路板分隔嵌埋于该包覆层中,可提升该包覆层的结构强度。
附图说明
图1为现有半导体封装件的剖面示意图。
图2A至图2H为本发明的电子封装件的制法的剖视示意图。
图2A-1、图2A-2、图2A-3、图2A-4、图2A-5及图2A-6为图2A的线路块的各种实施例的剖视示意图。
图3为图2H的后续制程的剖视示意图。
图4A为本发明的电子封装件的复合式基板的另一实施例的上视示意图。
图4B为本发明的电子封装件的另一实施例的剖面示意图。
附图标记说明
1:半导体封装件
1’:电路板
10:硅中介板
10a:转接侧
10b:置晶侧
100:导电硅穿孔
11:线路结构
12:焊球
13,30:封装基板
130:植球垫
15:半导体芯片
150:焊锡凸块
16:封装胶体
18,28:导电元件
2,4:电子封装件
2a,4a:复合式基板
20,40:线路板
200:绝缘层
201:线路层
21:第一线路块
21’:线路块
21a,21b,21c:线路部
210,220:绝缘体
211,221:导电柱
22:第二线路块
23:包覆层
23a:第一表面
23b:第二表面
24:第一线路结构
240:第一绝缘层
241:第一线路重布层
242:绝缘保护层
243:凸块底下金属层
25,25’:电子元件
25a:作用面
25b:非作用面
250:电极垫
251:导电凸块
252,31:底胶
26:封装层
26a:表面
27:第二线路结构
270:第二绝缘层
271:第二线路重布层
33:散热件
330:顶片
331:支撑脚
34:散热胶
35:粘着层
41,42,43,44:区块
49:导电结构
9:承载件
90:离型层
91:结合层
D:直径
H,h1,h2:高度
L:切割路径
S:容置空间
V:十字状沟槽结构
V1:第一沟槽
V2:第二沟槽。
具体实施方式
以下经由特定的具体实施例说明本发明的实施方式,本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知,本说明书附图所绘示的结构、比例、大小等,均仅用以配合说明书所揭示的内容,以供本领域技术人员的了解与阅读,并非用以限定本发明可实施的限定条件,故不具技术上的实质意义,任何结构的修饰、比例关系的改变或大小的调整,在不影响本发明所能产生的功效及所能达成的目的下,均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时,本说明书中所引用的如“上”、“第一”、“第二”及“一”等的用语,也仅为便于叙述的明了,而非用以限定本发明可实施的范围,其相对关系的改变或调整,在无实质变更技术内容下,当也视为本发明可实施的范畴。
图2A至图2H为本发明的电子封装件2的制法的剖面示意图。
如图2A所示,将一具有至少一容置空间S的线路板20设于一承载件9上,且于该容置空间S中设置至少一第一线路块21及至少一第二线路块22,以令该线路板20、第一线路块21及第二线路块22之间相互间隔配置而未相互接触。
于本实施例中,该线路板20为无核心层(coreless)的线路结构,其包含至少一绝缘层200与设于该绝缘层200上的线路层201。例如,以线路重布层(redistribution layer,简称RDL)方式形成扇出(fan out)型线路层201,其材料为铜,且形成该绝缘层200的材料为如聚对二唑苯(Polybenzoxazole,简称PBO)、聚酰亚胺(Polyimide,简称PI)、预浸材(Prepreg,简称PP)等的介电材或如绿漆、石墨的防焊材。
此外,该第一线路块21为基板(substrate)实施例,其具有一绝缘体210及至少一嵌埋于该绝缘体210中的导电柱211。例如,该导电柱211的宽度(直径)至多50微米(um)。具体地,该绝缘体210的相对两侧的至少一者可依需求形成一电性连接该导电柱211的线路部21a(如图2A-2所示的单侧线路部21a或如图2A-1所示的双侧线路部21a,21b),如扇出(fanout)型重布线路层(redistribution layer,简称RDL)形式,且形成该绝缘体210的材料如聚酰亚胺(polyimide,简称PI)、干膜(dry film)、如环氧树脂(epoxy)的封装胶体或封装材(molding compound),其可用压合(lamination)或模压(molding)的方式形成者,但不限于上述。应可理解地,该该第一线路块21也可采用半导体基部,其含有如硅(Si)、玻璃或其它适当基材,以替代该绝缘体210。
又,该第二线路块22为基板(substrate)实施例,如同第一线路块21,其具有一绝缘体220及至少一嵌埋于该绝缘体220中的导电柱221,但不具线路部21a,21b,如图2A-3所示。例如,该导电柱221仅外露于该绝缘体220的其中一侧以结合该承载件9,且该第二线路块22的高度h2高于该线路板20的高度h1及该第一线路块21的高度h1(即h2>h1),而该线路板20的高度h1大致等于该第一线路块21的高度h1。应可理解地,有关该线路块的形式可依需求调整为如图2A-1所示的第一线路块21、如图2A-3所示的第二线路块22或图2A-2所示的线路块21’等实施例,并无特别限制。
另一实施例中,该第一线路块21可由多个具有该导电柱211的绝缘体210(或半导体基部)及多个如呈扇出型重布线路层(RDL)形式的线路部21c相互堆叠而形成,且各该绝缘体210(或半导体基部)中的导电柱211电性连接该多个线路部21c,其中,各该绝缘体210(或半导体基部)中的导电柱211的宽度(直径)可为相同尺寸或不同尺寸,如图2A-4至图2A-6所示,上层绝缘体210(或半导体基部)中的导电柱211的宽度(直径)可相同或不同于下层绝缘体210(或半导体基部)中的导电柱211的宽度(直径),例如,最下层的绝缘体210(或半导体基部)中的导电柱211的宽度(直径)较大。此外,该第一线路块21的相对两外侧的至少一者可依需求形成该线路部21a,21b,以电性连接该绝缘体210(或半导体基部)中的导电柱211(如图2A-4所示的双侧型线路部21a,21b或如图2A-5所示的单侧型线路部21a)。应可理解地,该第一线路块21的相对两外侧也可为该绝缘体210(或半导体基部)而不配置该线路部21a,21b,21c,如图2A-6所示。
另外,该承载件9例如为半导体材料(如硅或玻璃)的板体,其上形成有一离型层90,以供该线路板20与该些线路块(如第一线路块21、第二线路块22或图2A-2所示的线路块21’)经由如粘胶的结合层91设于该离型层90上。
如图2B所示,形成一包覆层23于该承载件9(离型层90)上,以令该包覆层23包覆该线路板20、第一线路块21与第二线路块22,使该包覆层23、线路板20、第一线路块21与第二线路块22形成复合式基板2a,且该第二线路块22、该第一线路块21及该线路板20的上表面均外露于该包覆层23。
于本实施例中,该包覆层23为绝缘材,如聚酰亚胺(polyimide,简称PI)、干膜(dryfilm)、如环氧树脂(epoxy)的封装胶体或封装材(molding compound)。例如,该包覆层23的制程可选择液态封胶(liquid compound)、喷涂(injection)、压合(lamination)或模压(compression molding)等方式形成于该承载件9(离型层90)上。
此外,该包覆层23具有相对的第一表面23a及第二表面23b,且该包覆层23以其第二表面23b结合至该承载件9(离型层90)上,并依需求进行整平制程,使该第二线路块22的导电柱221、该第一线路块21的线路部21a及该线路板20的线路层201均外露于该包覆层23的第一表面23a。例如,经由研磨方式,移除该第二线路块22的部分材料与该包覆层23的部分材料,使该第二线路块22、该第一线路块21及该线路板20的上表面与该包覆层23的第一表面23a齐平。
因此,该复合式基板2a经由该第一与第二线路块21,22及该线路板20分隔嵌埋于该包覆层23中,以提升该包覆层23的结构强度。
如图2C所示,形成一第一线路结构24于该包覆层23的第一表面23a、该线路板20、第一线路块21与第二线路块22上,且该第一线路结构24电性连接该该线路板20、第一线路块21与第二线路块22。
于本实施例中,该第一线路结构24包括至少一电性连接该些导电柱221、线路层201与该线路部21a的第一线路重布层(redistribution layer,简称RDL)241。例如,形成该第一线路重布层241的材料为铜。
此外,该第一线路结构24还可包括至少一用以布设该第一线路重布层241的第一绝缘层240,且形成该第一绝缘层240的材料为如聚对二唑苯(Polybenzoxazole,简称PBO)、聚酰亚胺(Polyimide,简称PI)、预浸材(Prepreg,简称PP)等的介电材。应可理解地,经由该第一绝缘层240可形成多层该第一线路重布层241。进一步,该第一线路结构24于最外侧的第一绝缘层240上还可形成一如防焊层的绝缘保护层242,且部分外露最外侧的第一线路重布层241。
如图2D所示,于该第一线路结构24上接置至少一电子元件25,25’。
于本实施例中,于该第一线路结构24上配置多个电子元件25,25’,且该电子元件25,25’为主动元件、被动元件或其二者组合等,其中,该主动元件例如为半导体芯片,且该被动元件例如为电阻、电容及电感。例如,该电子元件25,25’为半导体芯片,其具有相对的作用面25a与非作用面25b,且以其作用面25a的电极垫250经由多个如焊锡材料的导电凸块251采用覆晶方式设于该第一线路重布层241上并电性连接该第一线路重布层241,且以底胶252包覆该导电凸块251;或者,该电子元件25,25’以其非作用面25b设于该该第一线路结构24上,并可经由多个焊线(图略)以打线方式电性连接该第一线路重布层241;亦或通过如导电胶或焊锡等导电材料(图略)电性连接该第一线路重布层241。然而,有关该电子元件25,25’电性连接该第一线路重布层241的方式不限于上述。
此外,该多个电子元件25,25’的至少其中两者之间具有间隙,以令该第一线路块21对应位于该间隙处,使该第一线路块21电性桥接该两电子元件25,25’。
又,可形成一凸块底下金属层(Under Bump Metallurgy,简称UBM)(图略)于最外层的第一线路重布层241上,以利于结合该导电凸块251。
如图2E所示,形成一封装层26于该第一线路结构24上,以令该封装层26包覆该电子元件25,25’及该底胶252。接着,移除该承载件9及该离型层90,以外露该结合层91及该包覆层23的第二表面23b。
于本实施例中,该封装层26为绝缘材,如聚酰亚胺(polyimide,简称PI)、干膜(dryfilm)、如环氧树脂(epoxy)的封装胶体或封装材(molding compound),其可用压合(lamination)或模压(molding)的方式形成于该第一线路结构24上。应可理解地,形成该封装层26的材料可相同或不相同该包覆层23的材料。
此外,若未形成该底胶252,该封装层26可包覆该些导电凸块251。
如图2F所示,经由整平制程,如研磨方式,移除该包覆层23的第二表面23b的部分材料,以一并移除该结合层91。
于本实施例中,该第二线路块22、该第一线路块21及该线路板20的下表面与该包覆层23的第二表面23b齐平,即该第二线路块22、该第一线路块21、该线路板20与该包覆层23四者的高度H相等,以令该第二线路块22的导电柱221、该第一线路块21的线路部21b及该线路板20的线路层201均外露于该包覆层23的第二表面23b。
如图2G所示,进行线路重布层(RDL)制程,以形成一第二线路结构27于该包覆层23的第二表面23b上,且该第二线路结构27电性连接该第二线路块22的导电柱221、该第一线路块21的线路部21b及该线路板20的线路层201。
于本实施例中,该第二线路结构27包括至少一第二绝缘层270及设于该第二绝缘层270上的第二线路重布层(RDL)271,且最外层的第二绝缘层270可作为防焊层,以令最外层的第二线路重布层271外露于该防焊层。
此外,形成该第二线路重布层271的材料为铜,且形成该第二绝缘层270的材料为如聚对二唑苯(PBO)、聚酰亚胺(PI)、预浸材(PP)等的介电材。
又,可于该第二线路结构27上形成多个电性连接该第二线路重布层271的导电元件28,并将该些导电元件28结合一支撑件(图略)上。例如,该支撑件如半导体材、介电材、陶瓷材、玻璃或金属材的板体,但不限于此,且该支撑件的尺寸可依需求选择晶圆型基板(Wafer form substrate)或一般整版面型基板(Panel form substrate),其上可具有如离型膜或胶材的绝缘暂时层(图略),以令该些导电元件28嵌埋于该绝缘暂时层(图略)中。
另外,可进行整平制程,使该电子元件25,25’的非作用面25b齐平该封装层26的表面26a。例如,经由研磨方式,移除该电子元件25,25’的部分材料与该封装层26的部分材料。
如图2H所示,移除该支撑件及其上的绝缘暂时层,以外露该第二线路结构27及该些导电元件28,再沿如图2F所示的切割路径L进行切单制程,以获取电子封装件2。
于后续制程中,如图3所示,该电子封装件2可利用该些导电元件28设于一封装基板30上,并以底胶31包覆该些导电元件28,再将一散热件33以其顶片330经由散热胶34结合于该电子封装件2的电子元件25,25’的非作用面25b及该封装层26上,且该散热件33的支撑脚331通过粘着层35架设于该封装基板30上。接着,于该封装基板30下侧形成多个焊球(图略)。
于本实施例中,该第一线路块21作为该些电子元件25,25’与该封装基板30之间的信号传递路径的转传部,且该些第二线路块22作为该些电子元件25,25’与该封装基板30之间的电源传递路径的转传部。例如,该第一线路块21经由该线路部21a,21b的设计,以将信号分别传递至两电子元件25,25’(即该第一线路块21作为该两电子元件25,25’之间的桥接元件)。
因此,本发明的制法主要经由该复合式基板2a的设计,以将该第一线路块21及第二线路块22与该线路板20分隔嵌埋于该包覆层23中,使该第一线路块21供作信号传递路径,且该些第二线路块22供作电源传递路径,故相比于现有技术,本发明的线路板20的线路层201不会有过热的情况,因而能避免该线路板20发生翘曲的问题,进而避免该线路板20的线路层201发生断裂的问题。换言之,当该电子元件25,25’的功能需求增加时,可依需求增加该第一线路块21与第二线路块22的数量,使该线路板20的线路层201可依需求制成细线路规格。
此外,该电子封装件2可依需求形成配置多个导电结构49于该包覆层23中,如图4A及图4B所示的复合式基板4a。例如,该导电结构49可如铜柱的金属柱。因此,当该电子元件25,25’的功能需求增加时,可依需求增加该导电结构49的数量,使该线路板40的体积可依需求微小化。
又,该第一线路块21可位于两该第二线路块22之间,且该些容置空间S可经由多个第一沟槽V1相互连通,如图4A及图4B所示的电子封装件4。例如,可形成多个连通该第一线路块21的第二沟槽V2,使该第一沟槽V1与第二沟槽V2相互垂直交叉,以呈十字状沟槽结构V,故该第一线路块21位于该十字状沟槽结构V的中间交界处,且该些第二线路块22位于该十字状沟槽结构V的其中一沟槽(即第一沟槽V1)的相对两侧,而该多个导电结构49可布设于该十字状沟槽结构V(即第一沟槽V1与第二沟槽V2)中。具体地,该些容置空间S与该十字状沟槽结构V将该线路板40分隔成多个(如四个)区块41,42,43,44。应可理解地,该些沟槽的布设可依需求设计,并不限于十字状沟槽结构V。
因此,经由该些沟槽的设计,使该包覆层23的接合面积增大,以利于分散热应力而增强该复合式基板4a的结构强度,故该复合式基板4a中的导电柱211,221(甚至导电结构49)的尺寸可相比于其它实施例(如复合式基板2a中的导电柱211,221)进一步降低,进而增加该复合式基板4a的接点(I/O)的数量(或密度提高)。换言之,当该电子元件25,25’的功能需求增加时,经由该沟槽的设计,能强化线路板40的结构强度,不仅有利于该线路板40的体积微小化设计,且能避免受高温影响而产生翘曲的问题。
另外,本发明的复合式基板2a,4a(其可视为中介板)以绝缘材配合RDL制程制作,而免用现有硅中介板,故可大幅降低制作成本及降低翘曲的发生率。
本发明还提供一种电子封装件2,4,包括:一包覆层23、一线路板20,40、第一线路块21与第二线路块22、一第一线路结构24、至少一电子元件25,25’以及一第二线路结构27。
所述的包覆层23具有相对的第一表面23a与第二表面23b。
所述的线路板20,40嵌埋于该包覆层23中。
所述的第一线路块21与第二线路块22嵌埋于该包覆层23中。
所述的第一线路结构24形成于该包覆层23的第一表面23a上且电性连接该线路板20,40、第一线路块21与第二线路块22。
所述的电子元件25,25’设于该第一线路结构24上且电性连接该第一线路结构24。
所述的第二线路结构27形成于该包覆层23的第二表面23b上且电性连接该线路板20,40、第一线路块21与第二线路块22。
于一实施例中,该包覆层23中嵌埋有相互分开配置的第一线路块21与第二线路块22。
于一实施例中,该线路板20,40与第一线路块21及第二线路块22为相互分隔。
于一实施例中,该线路板20,40具有配置该第一线路块21与第二线路块22的容置空间S,且该包覆层23还形成于该容置空间S中以包覆该第一线路块21与第二线路块22。
于一实施例中,该线路板40形成有第一沟槽V1与第二沟槽V2。例如,该第一沟槽V1与第二沟槽V2形成十字状沟槽结构V。进一步,该包覆层23还形成于该第一沟槽V1与第二沟槽V2中。
于一实施例中,该包覆层23中还嵌埋有多个导电结构49。
于一实施例中,所述的电子封装件2,4还包括一包覆该电子元件25,25’的封装层26。
于一实施例中,所述的电子封装件2,4还包括多个形成于该第二线路结构27上的导电元件28。
于一实施例中,该第一线路块21具有至少一绝缘体210(或半导体基部)、以及至少一嵌埋于该绝缘体210(或半导体基部)中的导电柱211。例如,该绝缘体210(或半导体基部)的相对两侧的至少一者上形成一电性连接该导电柱211的线路部21a,21b,21c。或者,该绝缘体210为封装材,且该半导体基部含有硅。
于一实施例中,该第二线路块22具有至少一绝缘体220(或半导体基部)、以及至少一嵌埋于该绝缘体220(或半导体基部)中的导电柱221。例如,该绝缘体220(或半导体基部)的相对两侧的至少一者上形成一电性连接该导电柱221的线路部21a,21b,21c。或者,该绝缘体220为封装材,且该半导体基部含有硅。
于一实施例中,该线路板20为无核心层的线路结构。
于一实施例中,该第一线路结构24上设有多个该电子元件25,25’,且多个该电子元件25,25’的至少其中两者之间具有间隙,以令该第一线路块21对应位于该间隙处,使该第一线路块21电性桥接两该电子元件25,25’。
综上所述,本发明的电子封装件及其制法,经由该复合式基板的设计,以将该线路块与该线路板分隔嵌埋于该包覆层中,故本发明的线路板不会有过热的情况,因而能避免该线路板发生翘曲的问题,进而避免该线路板的线路层发生断裂的问题,并且经由该线路块与该线路板分隔嵌埋于该包覆层中,能提升该包覆层的结构强度。
上述实施例用以例示性说明本发明的原理及其功效,而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下,对上述实施例进行修改。因此本发明的权利保护范围,应如权利要求书所列。
Claims (30)
1.一种电子封装件,其特征在于,包括:
包覆层,其具有相对的第一表面与第二表面;
线路板,其嵌埋于该包覆层中;
线路块,其嵌埋于该包覆层中;
第一线路结构,其形成于该包覆层的第一表面上且电性连接该线路板与线路块;
电子元件,其设于该第一线路结构上且电性连接该第一线路结构;以及
第二线路结构,其形成于该包覆层的第二表面上且电性连接该线路板与线路块。
2.如权利要求1所述的电子封装件,其特征在于,该包覆层中嵌埋有多个相互分开配置的该线路块。
3.如权利要求1所述的电子封装件,其特征在于,该线路板与该线路块为相互分隔。
4.如权利要求1所述的电子封装件,其特征在于,该线路板设有用以配置该线路块的容置空间,且该包覆层还形成于该容置空间中以包覆该线路块。
5.如权利要求1所述的电子封装件,其特征在于,该线路板形成有多个沟槽。
6.如权利要求5所述的电子封装件,其特征在于,该多个沟槽形成十字状沟槽结构。
7.如权利要求5所述的电子封装件,其特征在于,该包覆层还形成于该沟槽中。
8.如权利要求1所述的电子封装件,其特征在于,该包覆层中还嵌埋有多个导电结构。
9.如权利要求1所述的电子封装件,其特征在于,该电子封装件还包括包覆该电子元件的封装层。
10.如权利要求1所述的电子封装件,其特征在于,该电子封装件还包括形成于该第二线路结构上的多个导电元件。
11.如权利要求1所述的电子封装件,其特征在于,该线路块具有至少一绝缘体或至少一半导体基部、以及至少一嵌埋于该绝缘体或该半导体基部中的导电柱。
12.如权利要求11所述的电子封装件,其特征在于,该绝缘体为封装材,且该半导体基部含有硅。
13.如权利要求11所述的电子封装件,其特征在于,该绝缘体或该半导体基部的相对两侧的至少一者上形成有一电性连接该导电柱的线路部。
14.如权利要求1所述的电子封装件,其特征在于,该线路板为无核心层的线路结构。
15.如权利要求1所述的电子封装件,其特征在于,该第一线路结构上设有多个该电子元件,且多个该电子元件的至少其中两者之间具有间隙,以令该线路块对应位于该间隙处,使该线路块电性桥接两该电子元件。
16.一种电子封装件的制法,其特征在于,包括:
于一承载件上分开设置一线路板与至少一线路块;
形成包覆层于该承载件以包覆该线路板与该线路块,其中,该包覆层具有相对的第一表面与第二表面,且该包覆层以其第二表面结合至该承载件上;
形成第一线路结构于该包覆层的第一表面上,以令该第一线路结构电性连接该线路板与线路块;
设置电子元件于该第一线路结构上,且令该电子元件电性连接该第一线路结构;
移除该承载件;以及
形成第二线路结构于该包覆层的第二表面上,且令该第二线路结构电性连接该线路板与线路块。
17.如权利要求16所述的电子封装件的制法,其特征在于,该包覆层中嵌埋有多个相互分开配置的该线路块。
18.如权利要求16所述的电子封装件的制法,其特征在于,该线路板与该线路块为相互分隔。
19.如权利要求16所述的电子封装件的制法,其特征在于,该线路板设有用以配置该线路块的容置空间,且该包覆层还形成于该容置空间中以包覆该线路块。
20.如权利要求16所述的电子封装件的制法,其特征在于,该线路板形成有多个沟槽。
21.如权利要求20所述的电子封装件的制法,其特征在于,该多个沟槽形成十字状沟槽结构。
22.如权利要求20所述的电子封装件的制法,其特征在于,该包覆层还形成于该沟槽中。
23.如权利要求16所述的电子封装件的制法,其特征在于,该包覆层中还嵌埋有多个导电结构。
24.如权利要求16所述的电子封装件的制法,其特征在于,该制法还包括以封装层包覆该电子元件。
25.如权利要求16所述的电子封装件的制法,其特征在于,该制法还包括形成多个导电元件于该第二线路结构上。
26.如权利要求16所述的电子封装件的制法,其特征在于,该线路块具有至少一绝缘体或至少一半导体基部、以及至少一嵌埋于该绝缘体或该半导体基部中的导电柱。
27.如权利要求26所述的电子封装件的制法,其特征在于,该绝缘体为封装材,且该半导体基部含有硅。
28.如权利要求26所述的电子封装件的制法,其特征在于,该绝缘体或该半导体基部的相对两侧的至少一者上形成有一电性连接该导电柱的线路部。
29.如权利要求16所述的电子封装件的制法,其特征在于,该线路板为无核心层的线路结构。
30.如权利要求16所述的电子封装件的制法,其特征在于,该第一线路结构上设有多个该电子元件,且多个该电子元件的至少其中两者之间具有间隙,以令该线路块对应位于该间隙处,使该线路块电性桥接两该电子元件。
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