CN114121833A - 电子封装件及其制法与电子结构 - Google Patents

电子封装件及其制法与电子结构 Download PDF

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Publication number
CN114121833A
CN114121833A CN202010919334.4A CN202010919334A CN114121833A CN 114121833 A CN114121833 A CN 114121833A CN 202010919334 A CN202010919334 A CN 202010919334A CN 114121833 A CN114121833 A CN 114121833A
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electronic
conductive
layer
circuit
electrically connected
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CN202010919334.4A
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高灃
王隆源
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Abstract

一种电子封装件及其制法与电子结构，包括将一作为集成稳压器的电子结构及多个导电柱嵌埋于包覆层中，以利于近距离配合电子元件进行电性传输。

Description

电子封装件及其制法与电子结构
技术领域
本发明有关一种半导体装置，尤指一种电子封装件及其制法与电子结构。
背景技术
随着电子产业的蓬勃发展，电子产品也逐渐迈向多功能、高性能的趋势。例如，集成稳压器(IVR)嵌入高性能处理器中，以提高效率，如开关频率、降低功耗，且可提高可靠性，甚至降低制作成本。同时，目前应用于芯片封装领域的技术，包含有例如芯片尺寸构装(Chip Scale Package，简称CSP)、芯片直接贴附封装(Direct Chip Attached，简称DCA)或多芯片模组封装(Multi-Chip Module，简称MCM)等覆晶型态的封装模组，或将芯片立体堆叠化整合为三维集成电路(3D IC)芯片堆叠技术等。
图1为现有3D芯片堆叠的封装结构1的剖面示意图。如图1所示，该封装结构1包括一硅中介板(Through Silicon interposer，简称TSI)1a，其具有一硅板体10及多个形成于其中的导电硅穿孔(Through-silicon via，简称TSV)101，且该硅板体10的表面上形成有一电性连接该导电硅穿孔101的线路重布结构(Redistribution layer，简称RDL)。具体地，该线路重布结构包含一介电层11及一形成于该介电层11上的线路层12，且该线路层12电性连接该导电硅穿孔101，并形成一绝缘保护层13于该介电层11与该线路层12上，且该绝缘保护层13外露部分该线路层12，以结合多个焊锡凸块14。
此外，可先形成另一绝缘保护层15于该硅板体10上，且该绝缘保护层15外露该些导电硅穿孔101的端面，以结合多个焊锡凸块16于该些导电硅穿孔101的端面上，且该焊锡凸块16电性连接该导电硅穿孔101，其中，可选择性于该导电硅穿孔101的端面上形成供接置该焊锡凸块16的凸块底下金属层(Under Bump Metallurgy，简称UBM)160。
另外，该封装结构1还包括一封装基板19，供该硅中介板1a通过该些焊锡凸块16设于其上，使该封装基板19电性连接该些导电硅穿孔101，且以底胶191包覆该些第二导电元件16。
另外，该封装结构1还包括多个系统单芯片(System-On-Chip，简称SOC)型半导体芯片17，其设于该些焊锡凸块14上，使该半导体芯片17电性连接该线路层12，且以底胶171包覆该些焊锡凸块14，并形成封装材18于该封装基板19上，以令该封装材18包覆该半导体芯片17与该硅中介板1a。
于后续应用中，该封装结构1可形成多个焊球192于该封装基板19的下侧，以接置于一电路板1’上。
早期商品化产品中，为将一稳压器(IVR)1b’直接安装于该电路板上，但此方法将造成终端产品的体积无法达到轻薄短小的要求，且该稳压器1b’与该封装结构1的距离过远，造成与其相关电性连接的半导体芯片17传递信号的路径过远，导致电性功能下降，致使功耗随之增加。
因此，业界遂将该稳压器1b整合至与该封装基板19的下侧，以缩短该稳压器1b与该半导体芯片17之间的传输距离，借此缩减该电路板1’的表面积及体积。
然而，随着消费市场需求，现今终端产品的功能需求越加繁多，故接置于该封装基板19上的半导体芯片17越来越多，因而与其配合的稳压器1b的需求量大增，致使该封装基板19的下侧并无多余空间配置更多稳压器1b，导致单一封装结构1已无法符合现今终端产品相关轻薄短小、低功耗、高电性效能等需求。
此外，虽可将该稳压器1b整合于该半导体芯片17中，但需重新设计该封装结构1，不仅增加制作成本，且需扩增该半导体芯片17的尺寸，因而难以符合微小化的需求。
因此，如何克服上述现有技术的种种问题，实已成为目前业界亟待克服的难题。
发明内容
鉴于上述现有技术的种种缺失，本发明提供一种电子封装件及其制法与电子结构，以利于近距离配合电子元件进行电性传输
本发明的电子主体，其具有相对的第一侧与第二侧，其中，该电子主体具有一基部与一形成于该基部上的线路部，以令该基部定义出该第二侧，而该线路部则定义出该第一侧，且该基部中具有多个电性连接该线路部并外露出该第二侧的导电穿孔；多个第一导电体，其形成于该电子主体的第一侧上以电性连接该线路部；多个第二导电体，其形成于该电子主体的第二侧上以电性连接该导电穿孔；一第一绝缘层，其形成于该电子主体的第一侧上以包覆该第一导电体；以及一第二绝缘层，其形成于该电子主体的第二侧上以包覆该第二导电体。
前述的电子结构中，该电子结构作为集成稳压器。
前述的电子结构中，该第一导电体外露出该第一绝缘层。
前述的电子结构中，该第二导电体未外露出该第二绝缘层。
本发明还提供一种电子封装件，包括：一包覆层，其具有相对的第一表面与第二表面；一如前述的电子结构，其嵌埋于该包覆层中；以及多个导电柱，其嵌埋于该包覆层中。
前述的电子封装件中，该导电柱的端面、该第二绝缘层或该第二导电体外露出该包覆层的第二表面。
前述的电子封装件中，还包括形成于该包覆层的第一表面及/或第二表面上的线路结构，其电性连接该多个导电柱与该电子结构。
前述的电子封装件中，还包括形成于该包覆层的第一表面上的多个导电元件，其电性连接该导电柱及/或该第一导电体。
前述的电子封装件中，还包括接置于该包覆层的第二表面上的电子元件，其电性连接该第二导电体及/或该导电柱。
前述的电子封装件中，还包括嵌埋于该包覆层中的电子元件。
本发明还提供一种电子封装件的制法，包括：提供一电子主体，其具有相对的第一侧与第二侧，其中，该电子主体具有一基部与一形成于该基部上的线路部，以令该基部定义出该第二侧，而该线路部则定义出该第一侧，且该基部中具有多个电性连接该线路部并外露出该第二侧的导电穿孔；于该电子主体的第一侧及第二侧上分别形成多个第一导电体及第二导电体，以令该第一导电体电性连接该线路部，而该第二导电体电性连接该导电穿孔，且于该电子主体的第一侧与第二侧上分别形成第一绝缘层与第二绝缘层，使该第一绝缘层与第二绝缘层包覆该第一导电体与第二导电体，以形成电子结构；将该电子结构以其第一绝缘层设于一承载板上，且于该承载板上形成有多个导电柱；形成包覆层于该承载板上，以包覆该电子结构与导电柱，其中，该包覆层具有相对的第一表面与第二表面，且该包覆层以其第一表面结合该承载板；以及移除该承载板。
前述的制法中，该包覆层的第二表面齐平该导电柱的端面、该第二绝缘层或该第二导电体。
前述的制法中，该导电柱的端面、该第二绝缘层或该第二导电体外露出该包覆层的第二表面。
前述的制法中，该承载板上形成有第一线路结构，以接置该电子结构及多个导电柱，且该多个导电柱与该电子结构的第一导电体电性连接该第一线路结构，并使该包覆层以其第一表面结合该第一线路结构。例如，该第一导电体通过导电凸块电性连接该第一线路结构。
前述的制法中，还包括于移除该承载板后，形成多个导电元件于该包覆层的第一表面上，以令该多个导电元件电性连接该导电柱及/或该第一导电体。
前述的制法中，还包括形成第二线路结构于该包覆层的第二表面上，以令该第二线路结构电性连接该导电柱与该第二导电体。例如，还包括于该第二线路结构上接置电子元件，以令该电子元件电性连接该第二线路结构。
前述的制法中，还包括将电子元件接置于该包覆层的第二表面上，以令该电子元件电性连接该第二导电体及/或该导电柱。
前述的制法中，还包括于该电子结构设于该承载板上时，设置电子元件于该承载板上。
由上可知，本发明的电子封装件及其制法与电子结构中，主要通过将该电子结构嵌埋于该包覆层中以近距离配合该电子元件，故相比于现有技术，本发明无需重新设计该电子封装件，因而能大幅节省制作成本，且无需扩增该电子元件的尺寸，以利于满足微小化的需求，并有利于呈现高电性效能。
附图说明
图1为现有封装结构的剖视示意图。
图2A至图2H为本发明的电子封装件的制法的第一实施例的剖视示意图。
图2H’为对应图2H的其它实施例的剖视示意图。
图3为图2H的后续制程的剖视示意图。
图4A至图4B为本发明的电子封装件的制法的第二实施例的剖视示意图。
附图标记说明
1:封装结构
1’:电路板
1a:硅中介板
1b,1b’:稳压器
10:硅板体
101:导电硅穿孔
11:介电层
12:线路层
13,15,203:绝缘保护层
14,16:焊锡凸块
160:凸块底下金属层
17:半导体芯片
171,191,292:底胶
18:封装材
19:封装基板
192:焊球
2,2’,4:电子封装件
2a:整版面晶圆体
2b:电子结构
20:第一线路结构
200:第一介电层
201:第一线路重布层
21:电子主体
21’:基部
21”:线路部
21a:第一侧
21b:第二侧
210:导电穿孔
211:钝化层
212:线路层
22,291:导电凸块
23:导电柱
23b:端面
24:结合层
25:包覆层
25a:第一表面
25b:第二表面
26:第二线路结构
260:第二介电层
261:第二线路重布层
27:导电元件
28a:第一绝缘层
28b:第二绝缘层
280a:第一导电体
280b:第二导电体
29:第一电子元件
29a,41a:作用面
29b,41b:非作用面
290,410,410’:电极垫
41:第二电子元件
411,91:粘着层
8:布线板件
9:承载板
90:离形层
L,S:切割路径
T:封装部。
具体实施方式
以下通过特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知，本说明书所附附图所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的的情况下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“第一”、“第二”、“一”等的用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
图2A至图2H为本发明的电子封装件2的制法的第一实施例的剖面示意图。
如图2A所示，提供一整版面晶圆体2a，其包含多个阵列排列的电子主体21，且该电子主体21具有相对的第一侧21a与第二侧21b。
于本实施例中，该电子主体21为主动元件，如半导体芯片，其具有一硅材基部21’与一形成于该基部21’上的线路部21”，且该基部21’中具有多个外露出该基部21’的导电穿孔210，如导电硅穿孔(Through-silicon via，简称TSV)，以电性连接该线路部21”。例如，该线路部21”包含至少一钝化层211及结合该钝化层211的线路层212，以令该线路层212电性连接该导电穿孔210。具体地，该基部21’定义出该第二侧21b，且该线路部21”定义出该第一侧21a。应可理解地，有关具有该导电穿孔210的主动元件的结构形式繁多，并无特别限制。
如图2B所示，进行薄化制程，如通过研磨方式，移除该电子主体21的第二侧21b(或该基部21’)的部分材质，以令该导电穿孔210外露出该第二侧21b。
如图2C所示，形成多个第一导电体280a与第二导电体280b于该电子主体21的第一侧21a与第二侧21b上，以令该些第一导电体280a与第二导电体280b电性连接该线路层212与导电穿孔210。
于本实施例中，各该导电穿孔210的外露两端分别接触该第一导电体280a与第二导电体280b。例如，该第一导电体280a与第二导电体280b为如铜柱的金属柱。
此外，可分别形成第一绝缘层28a与第二绝缘层28b于该电子主体21的第一侧21a与第二侧21b上，使该第一绝缘层28a与第二绝缘层28b包覆该些第一导电体280a与第二导电体280b。例如，该第一绝缘层28a外露出该第一导电体280a，以结合多个导电凸块22。具体地，该导电凸块22为如铜柱、焊锡球等金属凸块。另一方面，该第二导电体280b未外露出该第二绝缘层28b。
另外，可沿切割路径L进行切单制程，以获取多个电子结构2b，其作为集成稳压器(Integrated Voltage Regulator，简称IVR)。
如图2D所示，提供一设于承载板9上的第一线路结构20，且于该第一线路结构20上形成有多个导电柱23，以将至少一电子结构2b设于该第一线路结构20上。
于本实施例中，该第一线路结构20包含至少一第一介电层200与至少一设于该第一介电层200上的第一线路重布层(Redistribution layer，简称RDL)201。例如，形成该第一线路重布层201的材质为铜，且形成该第一介电层200的材质如聚对二唑苯(Polybenzoxazole，简称PBO)、聚酰亚胺(Polyimide，简称PI)、预浸材(Prepreg，简称PP)或其它等的介电材。
此外，该承载板9例如为半导体材质(如硅或玻璃)的板体，其上可依需求依序形成有一离形层90与一粘着层91，以供该第一线路结构20设于该粘着层91上。
另外，该导电柱23设于该第一线路重布层201上并电性连接该第一线路重布层201，且形成该导电柱23的材质为如铜的金属材或焊锡材。
另外，该电子结构2b通过多个导电凸块22结合至该第一线路结构20上以电性连接该第一线路重布层201。例如，可依需求以如底胶的结合层24包覆该些导电凸块22。
如图2E所示，形成一包覆层25于该第一线路结构20上，以令该包覆层25包覆该电子结构2b、结合层24与该些导电柱23，其中，该包覆层25具有相对的第一表面25a与第二表面25b，且其以第一表面25a结合该第一线路结构20。接着，通过整平制程，使该包覆层25的第二表面25b齐平该导电柱23的端面23b与该电子结构2b的第二绝缘层28b(或该第二导电体280b的端面)，令该导电柱23的端面23b与该电子结构2b的第二绝缘层28b(或该第二导电体280b的端面)外露出该包覆层25的第二表面25b。
于本实施例中，该包覆层25为绝缘材，如环氧树脂的封装胶体，其可用压合(lamination)或模压(molding)的方式形成于该第一线路结构20上。
此外，该整平制程通过研磨方式，移除该导电柱23的部分材质、该电子结构2b的第二绝缘层28b(或该第二导电体280b)的部分材质与该包覆层25的部分材质。
另外，若未形成该结合层24，该包覆层25可包覆该些导电凸块22。
如图2F所示，形成一第二线路结构26于该包覆层25的第二表面25b上，且令该第二线路结构26电性连接该些导电柱23与该电子结构2b的第二导电体280b。
于本实施例中，该第二线路结构26包括多个第二介电层260、及设于该第二介电层260上的多个第二线路重布层(RDL)261，且最外层的第二绝缘层260可作为防焊层，以令最外层的第二线路重布层261部分外露出该防焊层。或者，该第二线路结构26也可仅包括单一第二介电层260及单一第二线路重布层261。
此外，形成该第二线路重布层261的材质为铜，且形成该第二介电层260的材质为如聚对二唑苯(PBO)、聚酰亚胺(PI)、预浸材(PP)或其它等的介电材。
如图2G所示，移除该承载板9及其上的离形层90与粘着层91，以外露该第一线路结构20。
于本实施例中，该包覆层25、电子结构2b与该些导电柱23可作为封装部T，其可依需求包含该第一线路结构20及/或第二线路结构26。
如图2H所示，于最外层的第二线路重布层261上接置至少一第一电子元件29，且可形成多个如焊球的导电元件27于该包覆层25的第一表面25a(或该第一线路结构20)上，以令该多个导电元件27电性连接该导电柱23及/或该第一导电体280a。
于本实施例中，可形成一如防焊层的绝缘保护层203于该第一线路结构20上，且于该绝缘保护层203上形成多个开孔，以令该第一线路重布层201外露出该些开孔，从而供结合该导电元件27，使该导电元件27通过该第一线路结构20电性连接该导电柱23及/或该第一导电体280a。
此外，该第一电子元件29为主动元件、被动元件或其二者组合等，其中，该主动元件例如为半导体芯片，且该被动元件为例如电阻、电容及电感。例如，该第一电子元件29为半导体芯片，如系统单芯片(System-On-Chip，简称SOC)型的功能芯片，其具有相对的作用面29a与非作用面29b，且以其作用面29a的电极垫290通过多个如焊锡材料的导电凸块291采用覆晶方式设于该第二线路重布层261上并电性连接该第二线路重布层261，并以底胶292包覆该些导电凸块291；或者，该第一电子元件29以其非作用面29b设于该第二线路结构26上，并可通过多个焊线(图略)以打线方式电性连接该第二线路重布层261；亦或通过如导电胶或焊锡等导电材料(图略)电性连接该第二线路重布层261。然而，有关该第一电子元件29电性连接该第二线路重布层261的方式不限于上述。
如图2H所示，沿所示的切割路径S对该封装部T进行切单制程，以获取该电子封装件2。
于本实施例中，如图3所示，于后续制程中电子封装件2可通过该些导电元件27接置于一布线板件8上侧，如有机材板体(如具有核心层与线路的封装基板(substrate)或具有线路的无核心层式(coreless)封装基板)或无机材板体(如硅板材)，且该布线板件8下侧可接置于一如电路板的电子装置(图未示)上。
此外，于另一实施例中，如图2H’图所示的电子封装件2’，可依需求省略该第二线路结构26的制作。例如，将该第一电子元件29接置于该包覆层25的第二表面25b上，以令该第一电子元件29电性连接该第二导电体280b及/或该导电柱23。具体地，该第一电子元件29采用覆晶方式通过该些导电凸块291接置于该电子结构2b的第二导电体280b与该导电柱23上，以电性连接该第二导电体280b与该导电柱23，且该底胶292接触该包覆层25的第二表面25b。
因此，本发明的制法通过将作为IVR的电子结构2b嵌埋于该包覆层25中以对接该第一电子元件29，以利于配合不同功能的第一电子元件29，故相比于现有将IVR整合于SOC中，本发明的制法无需重新设计该电子封装件2,2’，因而能大幅节省制作成本，且无需扩增该第一电子元件29的尺寸，以利于满足微小化的需求。
此外，相比于现有将IVR整合至电路板或封装基板上，本发明的电子结构2b与该第一电子元件29之间的电性传输距离可最短化(无需经过封装基板或电路板)，以利于降低损耗及缩小该电子封装件2,2’的尺寸，并提升电性效能。
请参阅图4A及图4B，其为本发明的电子封装件4的制法的第二实施例的剖面示意图。本实施例与第一实施例的差异在于第二电子元件的配置，其它制程大致相同，故以下不再赘述相同处。
如图4A所示，于图2D所示的制程中，当该电子结构2b设于该承载板9(或该第一线路结构20)上时，一并设置至少一第二电子元件41于该承载板9(或该第一线路结构20)上。
于本实施例中，该第二电子元件41为主动元件、被动元件或其二者组合等，其中，该主动元件例如为半导体芯片，且该被动元件例如为电阻、电容及电感。例如，该第二电子元件41为半导体芯片，如硅材架桥(Si bridge)芯片，其具有相对的作用面41a与非作用面41b，该作用面41a具有多个电极垫410，且该第二电子元件41以其非作用面41b通过粘着层411设于该第一线路结构20(或承载板9)上，并以其作用面41a上的电极垫410于后续制程中(如图4B所示)电性连接该第二线路重布层261。
此外，该电子结构2b可于其中一侧上依需求形成至少一电极垫410’，以电性连接该第一电子元件29或该第二线路结构26。
另外，可依需求省略该第一线路结构20的制作，使该电子结构2b与该第二电子元件41设于该承载板9(其上可具有离形层90与粘着层91)上，且该承载板9上形成有多个导电柱23。
如图4B所示，进行如图2E至图2H所示的封装制程中，以获取多个电子封装件4。
于本实施例中，若省略该第一线路结构20的制作，该包覆层25将形成于该承载板9(其上可具有离形层90与粘着层91)上，且于移除该承载板9(一并移除该离形层90与粘着层91)后，该电子结构2b的第一导电体280a与该导电柱23可通过该些导电元件27接置该布线板件8。
因此，本发明的制法通过将该电子结构2b嵌埋于该包覆层25中以对接该第一电子元件29或并排该第二电子元件41，以利于配合不同功能的第一电子元件29或第二电子元件41，故相比于现有将IVR整合于SOC中，本发明的制法无需重新设计该电子封装件4，因而能大幅节省制作成本，且无需扩增该第一电子元件29或第二电子元件41的尺寸，以利于满足微小化的需求。
此外，相比于现有将IVR整合至电路板或封装基板上，本发明的电子结构2b与该第一电子元件29或第二电子元件41之间的电性传输距离可最短化(无需经过封装基板或电路板)，以利于降低损耗及缩小该电子封装件4的尺寸，并提升电性效能。
本发明还提供一种电子结构2b，包括：一电子主体21、多个第一导电体280a、多个第二导电体280b、一第一绝缘层28a以及一第二绝缘层28b。
所述的电子主体21具有相对的第一侧21a与第二侧21b，其中，该电子主体21具有一基部21’与一形成于该基部21’上的线路部21”，以令该基部21’定义出该第二侧21b，而该线路部21”则定义出该第一侧21a，且该基部21’中具有多个电性连接该线路部21”并外露出该第二侧21b的导电穿孔210。
所述的第一导电体280a形成于该电子主体21的第一侧21a上以电性连接该线路部21”。
所述的第二导电体280b形成于该电子主体21的第二侧21b上以电性连接该导电穿孔210。
所述的第一绝缘层28a形成于该电子主体21的第一侧21a上以包覆该第一导电体280a。
所述的第二绝缘层28b形成于该电子主体21的第二侧21b上以包覆该第二导电体280b。
于一实施例中，该电子结构2b作为集成稳压器。
于一实施例中，该第一导电体280a外露出该第一绝缘层28a。
于一实施例中，该第二导电体280b未外露出该第二绝缘层28b。
本发明还提供一种电子封装件2,2’,4，包括：一包覆层25、至少一电子结构2b以及多个导电柱23。
所述的包覆层25具有相对的第一表面25a与第二表面25b。
所述的电子结构2b嵌埋于该包覆层25中。
所述的导电柱23嵌埋于该包覆层25中。
于一实施例中，该导电柱23的端面、该第二绝缘层28b或该第二导电体280b外露出该包覆层25的第二表面25b。
于一实施例中，所述的电子封装件2,2’,4还包括形成于该包覆层25的第一表面25a及/或第二表面25b上的线路结构(即该第一线路结构20与第二线路结构26)，其电性连接该多个导电柱23与该电子结构2b。
于一实施例中，所述的电子封装件2,2’,4还包括形成于该包覆层25的第一表面25a上的多个导电元件27，其电性连接该导电柱23及/或该第一导电体280a。
于一实施例中，所述的电子封装件2,2’,4还包括至少一接置于该包覆层25的第二表面25b上的第一电子元件29，其电性连接该第二导电体280b及/或该导电柱23。
于一实施例中，所述的电子封装件4还包括嵌埋于该包覆层25中的第二电子元件41。
综上所述，本发明的电子封装件及其制法与电子结构，通过将该电子结构嵌埋于该包覆层中以近距离配合该电子元件，故本发明无需重新设计该电子封装件，因而能大幅节省制作成本，且无需扩增该电子元件的尺寸，以利于满足微小化的需求，并有利于呈现高电性效能。
此外，通过将作为IVR的电子结构嵌埋于该包覆层中，使该电子封装件可适用于伺服器或基站处理器。
上述实施例仅用以示例性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如所附权利要求书所列。

Claims (20)

1.一种电子结构，其特征在于，包括：
一电子主体，其具有相对的第一侧与第二侧，其中，该电子主体具有一基部与一形成于该基部上的线路部，以令该基部定义出该第二侧，而该线路部则定义出该第一侧，且该基部中具有多个电性连接该线路部并外露出该第二侧的导电穿孔；
多个第一导电体，其形成于该电子主体的第一侧上以电性连接该线路部；
多个第二导电体，其形成于该电子主体的第二侧上以电性连接该导电穿孔；
一第一绝缘层，其形成于该电子主体的第一侧上以包覆该第一导电体；以及
一第二绝缘层，其形成于该电子主体的第二侧上以包覆该第二导电体。
2.如权利要求1所述的电子结构，其特征在于，该电子结构作为集成稳压器。
3.如权利要求1所述的电子结构，其特征在于，该第一导电体外露出该第一绝缘层。
4.如权利要求1所述的电子结构，其特征在于，该第二导电体未外露出该第二绝缘层。
5.一种电子封装件，其特征在于，包括：
一包覆层，其具有相对的第一表面与第二表面；
一如权利要求1或2所述的电子结构，其嵌埋于该包覆层中；以及
多个导电柱，其嵌埋于该包覆层中。
6.如权利要求5所述的电子封装件，其特征在于，该导电柱的端面、该第二绝缘层或该第二导电体外露出该包覆层的第二表面。
7.如权利要求5所述的电子封装件，其特征在于，该电子封装件还包括形成于该包覆层的第一表面及/或第二表面上的线路结构，其电性连接该多个导电柱与该电子结构。
8.如权利要求5所述的电子封装件，其特征在于，该电子封装件还包括形成于该包覆层的第一表面上的多个导电元件，其电性连接该导电柱及/或该第一导电体。
9.如权利要求5所述的电子封装件，其特征在于，该电子封装件还包括接置于该包覆层的第二表面上的电子元件，其电性连接该第二导电体及/或该导电柱。
10.如权利要求5所述的电子封装件，其特征在于，该电子封装件还包括嵌埋于该包覆层中的电子元件。
11.一种电子封装件的制法，其特征在于，包括：
提供一电子主体，其具有相对的第一侧与第二侧，其中，该电子主体具有一基部与一形成于该基部上的线路部，以令该基部定义出该第二侧，而该线路部则定义出该第一侧，且该基部中具有多个电性连接该线路部并外露出该第二侧的导电穿孔；
于该电子主体的第一侧及第二侧上分别形成多个第一导电体及第二导电体，以令该第一导电体电性连接该线路部，而该第二导电体电性连接该导电穿孔，且于该电子主体的第一侧与第二侧上分别形成第一绝缘层与第二绝缘层，使该第一绝缘层与第二绝缘层包覆该第一导电体与第二导电体，以形成电子结构；
将该电子结构以其第一绝缘层设于一承载板上，且于该承载板上形成有多个导电柱；
形成包覆层于该承载板上，以包覆该电子结构与导电柱，其中，该包覆层具有相对的第一表面与第二表面，且该包覆层以其第一表面结合该承载板；以及
移除该承载板。
12.如权利要求11所述的电子封装件的制法，其特征在于，该包覆层的第二表面齐平该导电柱的端面、该第二绝缘层或该第二导电体。
13.如权利要求11所述的电子封装件的制法，其特征在于，该导电柱的端面、该第二绝缘层或该第二导电体外露出该包覆层的第二表面。
14.如权利要求11所述的电子封装件的制法，其特征在于，该制法还包括于该承载板上形成第一线路结构，以接置该电子结构及多个导电柱，且该多个导电柱与该电子结构的第一导电体电性连接该第一线路结构，并使该包覆层以其第一表面结合该第一线路结构。
15.如权利要求14所述的电子封装件的制法，其特征在于，该第一导电体通过导电凸块电性连接该第一线路结构。
16.如权利要求11所述的电子封装件的制法，其特征在于，该制法还包括于移除该承载板后，形成多个导电元件于该包覆层的第一表面上，以令该多个导电元件电性连接该导电柱及/或该第一导电体。
17.如权利要求11所述的电子封装件的制法，其特征在于，该制法还包括形成第二线路结构于该包覆层的第二表面上，以令该第二线路结构电性连接该导电柱与该第二导电体。
18.如权利要求17所述的电子封装件的制法，其特征在于，该制法还包括于该第二线路结构上接置电子元件，以令该电子元件电性连接该第二线路结构。
19.如权利要求11所述的电子封装件的制法，其特征在于，该制法还包括将电子元件接置于该包覆层的第二表面上，以令该电子元件电性连接该第二导电体及/或该导电柱。
20.如权利要求11所述的电子封装件的制法，其特征在于，该制法还包括于该电子结构设于该承载板上时，设置电子元件于该承载板上。
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