TWI698966B - 電子封裝件及其製法 - Google Patents

電子封裝件及其製法 Download PDF

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Publication number
TWI698966B
TWI698966B TW108116577A TW108116577A TWI698966B TW I698966 B TWI698966 B TW I698966B TW 108116577 A TW108116577 A TW 108116577A TW 108116577 A TW108116577 A TW 108116577A TW I698966 B TWI698966 B TW I698966B
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Taiwan
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conductive
coating layer
circuit structure
electronic package
electronic
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TW108116577A
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English (en)
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TW202042351A (zh
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蘇品境
張正楷
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矽品精密工業股份有限公司
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Priority to TW108116577A priority Critical patent/TWI698966B/zh
Priority to CN201910504912.5A priority patent/CN111952274B/zh
Priority to US16/568,990 priority patent/US20200365489A1/en
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Publication of TWI698966B publication Critical patent/TWI698966B/zh
Publication of TW202042351A publication Critical patent/TW202042351A/zh

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Abstract

一種電子封裝件，係以包覆層包覆一具有導電穿孔之中介板與複數導電柱，且將電子元件設於該包覆層上且電性連接該導電柱與該導電穿孔，藉由該導電柱作為電子元件之部分電性功能之電性傳輸路徑，減少該導電穿孔之製作數量，進而減少製程時間及化學藥劑之成本，且能製作小尺寸的中介板以取代習知大面積矽中介板，進而提高良率。

Description

電子封裝件及其製法
本發明係有關一種封裝結構，尤指一種電子封裝件及其承載基板與製法。
隨著電子產業的蓬勃發展，電子產品也逐漸邁向多功能、高性能的趨勢。目前應用於晶片封裝領域之技術，包含有例如晶片尺寸構裝(Chip Scale Package，簡稱CSP)、晶片直接貼附封裝(Direct Chip Attached，簡稱DCA)或多晶片模組封裝(Multi-Chip Module，簡稱MCM)等覆晶型態的封裝模組，或將晶片立體堆疊化整合為三維積體電路(3D IC)晶片堆疊技術等。
第1圖係為習知3D晶片堆疊之封裝結構1之剖面示意圖。如第1圖所示，該封裝結構1包括一矽中介板(Through Silicon interposer，簡稱TSI)1a，其具有一矽板體10及複數形成於其中之導電矽穿孔(Through-silicon via，簡稱TSV)101，且該矽板體10之表面上形成有一電性連接該導電矽穿孔101之線路重佈結構(Redistribution layer，簡稱RDL)。具體地，該線路重佈結構係包含一介電層11及一形成於該介電層 11上之線路層12，且該線路層12電性連接該導電矽穿孔101，並形成一絕緣保護層13於該介電層11與該線路層12上，且該絕緣保護層13外露部分該線路層11，以結合複數如銲錫凸塊之第一導電元件14。
再者，可先形成另一絕緣保護層15於該矽板體10上，且該絕緣保護層15外露該些導電矽穿孔101之端面，以結合複數第二導電元件16於該些導電矽穿孔101之端面上，且該第二導電元件16電性連接該導電矽穿孔101，其中，該第二導電元件16係含有銲錫材料或銅凸塊，且可選擇性於該導電矽穿孔101之端面上形成供接置該第二導電元件16之凸塊底下金屬層(Under Bump Metallurgy，簡稱UBM)160。
又，該封裝結構1復包括一封裝基板19，供該矽中介板1a藉由該些第二導電元件16設於其上，使該封裝基板19電性連接該些導電矽穿孔101，且以底膠191包覆該些第二導電元件16。
另外，該封裝結構1復包括複數半導體晶片17，其設於該些第一導電元件14上，使該半導體晶片17電性連接該線路層12，其中，該半導體晶片17係以覆晶方式結合該些第一導電元件14，且以底膠171包覆該些第一導電元件14，並形成封裝材18於該封裝基板19上，以令該封裝材18包覆該半導體晶片17與該矽中介板1a。
於後續應用中，該封裝結構1可形成複數銲球192於該封裝基板19之下側，以接置於一如電路板之電子裝置(圖略)上。
惟，現今終端產品之電性功能越加發達，故接置於該矽中介板1a上之電子元件半導體晶片17越來越多，使該矽中介板1a的結合面積 亦會越來越大，因而該導電矽穿孔101之佈設數量亦會增多，導致於製程上會產生以下缺失，造成該封裝結構1之良率下降。
第一點：該矽中介板1a之體積越來越大，則該底膠171及該封裝材18等膠材與該封裝基板19、矽中介板1a及半導體晶片17之間的熱膨脹係數(CTE)不匹配(mismatch)，因而容易發生熱應力不均勻之情況，致使熱循環(thermal cycle)時，該矽中介板1a產生極大之翹曲(warpage)，以致於發生植球狀況不佳(即該第二導電元件16掉落而電性斷路)、第二導電元件16不沾錫(non-wetting)或該封裝基板19分裂等可靠度問題，進而導致應用該封裝結構1之終端電子產品(如電腦、手機等)產生可靠度問題。
第二點：該半導體晶片17之電性功能一定要透過該矽中介板1a才能連接到該封裝基板19，且該半導體晶片17之訊號(signal)電性功能之傳輸速度係為高速需求，以提升終端產品效能，但該半導體晶片17之部分電性功能(如電源或接地)之傳輸速度需求不高，故若該電源或接地之電性功能仍透過該導電矽穿孔101進行傳輸，將導致製作成本的浪費。例如，需製作該電源或接地之電性功能所用之導電矽穿孔101，因而需增加該矽板體10之面積，且於製作該導電矽穿孔101，因需具備一定深寬比之控制(即該導電矽穿孔101之深寬比)，才能製作出適用的矽中介板1a，因而往往需耗費大量製程時間及化學藥劑之成本，進而提高製程難度及製作成本。
因此，如何克服上述習知技術之種種問題，實已成為目前業界亟待克服之難題。
鑑於上述習知技術之種種缺失，本發明提供一種電子封裝件，係包括：一包覆層；至少一中介板，係嵌埋於該包覆層中且具有複數導電穿孔；複數導電柱，係形成於該包覆層中；以及電子元件，係設於該包覆層上且電性連接該導電柱與該導電穿孔。
前述之電子封裝件中，該包覆層之表面係齊平該中介板之表面。
前述之電子封裝件中，該包覆層之表面係齊平該導電柱之端面。
前述之電子封裝件中，該導電穿孔係外露於該包覆層之表面。
前述之電子封裝件中，該導電柱之端面係外露於該包覆層之表面。
前述之電子封裝件中，該電子元件係為主動元件、被動元件或其二者組合。
前述之電子封裝件中，該電子元件藉由線路結構電性連接該導電柱與該導電穿孔。
前述之電子封裝件中，復包括形成於該包覆層上且電性連接該導電柱與該導電穿孔之線路結構。進一步，復包括形成於該線路結構上之複數導電元件，該複數導電元件係藉由該線路結構電性連接該導電柱與該導電穿孔。
前述之電子封裝件中，復包括形成於該包覆層上且電性連接該導電柱與該導電穿孔之複數導電元件。
本發明亦提供一種電子封裝件之製法，係包括：提供一包覆層，其嵌埋有至少一中介板與複數導電柱，其中，該中介板具有複數導電穿孔；以及設置電子元件於該包覆層之其中一側上，且令該電子元件電性連接該導電柱與該導電穿孔。
前述之製法中，復包括：提供第一線路結構；將該導電柱與該中介板結合於該第一線路結構上，以令該第一線路結構電性連接該導電柱與該導電穿孔；以及將該包覆層結合於該第一線路結構上，以令該包覆層包覆該中介板與該導電柱。
前述之製法中，復包括於該包覆層上形成第二線路結構，以令該電子元件設於該第二線路結構上，使該電子元件藉由該第二線路結構電性連接該導電柱與該導電穿孔。
前述之製法中，復包括於該包覆層之另一側上形成複數導電元件，且令該複數導電元件電性連接該導電柱與該導電穿孔。
本發明又提供一種電子封裝件之製法，係包括：提供一電子元件；將複數導電柱與至少一中介板結合於該電子元件上，其中，該中介板具有複數導電穿孔，且令該電子元件電性連接該導電柱與該導電穿孔；以及藉由包覆層包覆該中介板與該導電柱。
前述之製法中，復包括形成第一線路結構於該包覆層上，以令該第一線路結構電性連接該導電柱與該導電穿孔。
前述之製法中，復包括：形成第二線路結構於該電子元件上；將該導電柱與該中介板結合於該第二線路結構上，且令該第二線路結 構電性連接該導電柱與該導電穿孔；以及將該包覆層結合於該第二線路結構上，以令該包覆層包覆該中介板與該導電柱。
前述之製法中，復包括於該包覆層上形成複數導電元件，且令該複數導電元件電性連接該導電柱與該導電穿孔。
前述之兩種製法中，該包覆層係具有相對之第一表面與第二表面，且其第二表面係齊平該中介板之表面。
前述之兩種製法中，該包覆層係具有相對之第一表面與第二表面，且其第二表面係齊平該導電柱之端面。
前述之兩種製法中，該包覆層係具有相對之第一表面與第二表面，且該導電穿孔係外露於該包覆層之第二表面。
前述之兩種製法中，該包覆層係具有相對之第一表面與第二表面，且該導電柱之端面係外露於該包覆層之第二表面。
前述之兩種製法中，該電子元件係為主動元件、被動元件或其二者組合。
由上可知，本發明之電子封裝件及其製法，主要藉由該導電柱作為電子元件之部分電性功能(如電源或接地)之電性傳輸路徑，以減少該導電穿孔之製作數量，故相較於習知技術，本發明不僅能減少製程時間及化學藥劑之成本，且能製作小尺寸的中介板以取代習知大面積矽中介板，因而能提高良率。
再者，藉由該包覆層包覆該中介板，以於後續形成該封裝材時，該包覆層與該封裝材之間的熱膨脹係數相匹配，因而容易平均分散熱應力，故相較於習知技術，本發明於熱循環時，能避免該包覆層產生翹曲，進而避免發生植球狀況不佳等可靠度問題。
1‧‧‧封裝結構
1a‧‧‧矽中介板
10‧‧‧矽板體
101‧‧‧導電矽穿孔
11‧‧‧介電層
12‧‧‧線路層
13,15‧‧‧絕緣保護層
14‧‧‧第一導電元件
16‧‧‧第二導電元件
160‧‧‧凸塊底下金屬層
17‧‧‧半導體晶片
171,191,292‧‧‧底膠
18‧‧‧封裝材
19‧‧‧封裝基板
192‧‧‧銲球
2,2’,2”,3,3’,3”,4,4’‧‧‧電子封裝件
2a‧‧‧中介部
20,30‧‧‧第一線路結構
200‧‧‧第一絕緣層
201‧‧‧第一線路重佈層
21‧‧‧中介板
21a‧‧‧第一側
21b‧‧‧第二側
210‧‧‧導電穿孔
210a,210b‧‧‧端面
22‧‧‧導電體
22a,23a,23b‧‧‧端面
23‧‧‧導電柱
24‧‧‧結合層
25‧‧‧包覆層
25a‧‧‧第一表面
25b‧‧‧第二表面
26,36‧‧‧第二線路結構
260,360‧‧‧第二絕緣層
261,361‧‧‧第二線路重佈層
27‧‧‧導電元件
28‧‧‧絕緣保護層
29‧‧‧電子元件
29a‧‧‧作用面
29b‧‧‧非作用面
290‧‧‧電極墊
291‧‧‧導電凸塊
8‧‧‧佈線板件
8a‧‧‧散熱件
80,91‧‧‧黏著層
9‧‧‧承載板
90‧‧‧離型層
S‧‧‧切割路徑
第1圖係為習知封裝結構之剖視示意圖。
第2A至2G圖係為本發明之電子封裝件之製法之第一實施例之剖視示意圖。
第2G’及2G”圖係為對應第2G圖之其它實施例之剖視示意圖。
第2H圖係為第2G圖之後續製程之剖視示意圖。
第3A至3E圖係為本發明之電子封裝件之製法之第二實施例之剖視示意圖。
第3A’圖係為對應第3A圖之其它實施例之剖視示意圖。
第3E’及3E”圖係為對應第3E圖之其它實施例之剖視示意圖。
第4及4’圖係為本發明之電子封裝件之其它實施例之剖視示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義， 任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」、「第一」、「第二」及「一」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2G圖係為本發明之電子封裝件2之製法之第一實施例的剖面示意圖。
如第2A圖所示，提供一設於承載板9上之第一線路結構20，且該第一線路結構20上形成有複數導電柱23。
於本實施例中，該第一線路結構20係包括至少一第一絕緣層200與至少一設於該第一絕緣層200上之第一線路重佈層(Redistribution layer，簡稱RDL)201。例如，形成該第一線路重佈層201之材質係為銅，且形成該第一絕緣層200之材質係如聚對二唑苯(Polybenzoxazole，簡稱PBO)、聚醯亞胺(Polyimide，簡稱PI)、預浸材(Prepreg，簡稱PP)或其它等之介電材。
再者，該承載板9係例如為半導體材質(如矽或玻璃)之板體，其上以塗佈方式依序形成有一離型層90與一黏著層91，以供該第一線路結構20設於該黏著層91上。
又，該導電柱23係設於該第一線路重佈層201上並電性連接該第一線路重佈層201，且形成該導電柱23之材質係為如銅之金屬材或銲錫材。
如第2B圖所示，將至少一中介板21設於該第一線路結構20上，且該中介板21具有相對之第一側21a與第二側21b。
於本實施例中，該中介板21係為矽中介板(Through Silicon interposer，簡稱TSI)，其具有複數外露於該第一側21a之導電穿孔210，如導電矽穿孔(Through-silicon via，簡稱TSV)。應可理解地，該導電穿孔210之結構態樣繁多，如端處具有墊部，並無特別限制。
再者，該中介板21之第一側21a係以該導電穿孔210之外露端面210a藉由複數導電體22結合至該第一線路結構20上以電性連接該第一線路重佈層201。例如，該導電體22係為如導電線路、或如銅柱、銲錫球等金屬凸塊、或銲線機製作之釘狀(stud)導電物，但不限於此。進一步，可依需求以如底膠之結合層24包覆該些導電體22。
如第2C圖所示，形成一包覆層25於該第一線路結構20上，以令該包覆層25包覆該中介板21、結合層24與該些導電柱23，其中，該包覆層25係具有相對之第一表面25a與第二表面25b，且其以第一表面25a結合該第一線路結構20。接著，藉由整平製程，使該包覆層25之第二表面25b齊平該導電柱23之端面23b與該中介板21之第二側21b(或該導電穿孔210之另一端面210b)，令該導電柱23之端面23b與該中介板21之第二側21b(或該導電穿孔210之另一端面210b)外露於該包覆層25之第二表面25b。
於本實施例中，該包覆層25係為絕緣材，如環氧樹脂之封裝膠體，其可用壓合(lamination)或模壓(molding)之方式形成於該第一線路結構20上。
再者，該整平製程係藉由研磨方式，移除該導電柱23之部分材質、該中介板21之第二側21b之部分材質與該包覆層25之部分材質。
如第2D圖所示，形成一第二線路結構26於該包覆層25之第二表面25b上，且令該第二線路結構26電性連接該些導電柱23與該中介板21之導電穿孔210。
於本實施例中，該第二線路結構26係包括複數第二絕緣層260、及設於該第二絕緣層260上之複數第二線路重佈層(RDL)261，且最外層之第二絕緣層260可作為防銲層，以令最外層之第二線路重佈層261外露於該防銲層。或者，該第二線路結構26亦可僅包括單一第二絕緣層260及單一第二線路重佈層261。
再者，形成該第二線路重佈層261之材質係為銅，且形成該第二絕緣層260之材質係為如聚對二唑苯(PBO)、聚醯亞胺(PI)、預浸材(PP)或其它等之介電材。
如第2E圖所示，移除該承載板9及其上之離型層90與黏著層91，以外露該第一線路結構20。
於本實施例中，該包覆層25、中介板21與該些導電柱23可作為中介部2a，其可依需求包含該第一線路結構20及/或第二線路結構26。
如第2F圖所示，於最外層之第二線路重佈層261上接置一電子元件29，且可於該第一線路結構20上形成複數如銲球之導電元件27。
於本實施例中，可形成一如防銲層之絕緣保護層28於該第一線路結構20上，且於該絕緣保護層28上形成複數開孔，以令該第一線路重佈層201外露於該些開孔，俾供結合該導電元件27。
再者，該電子元件29係為主動元件、被動元件或其二者組合等，其中，該主動元件係例如半導體晶片，且該被動元件係例如電阻、 電容及電感。例如，該電子元件29係為半導體晶片，如邏輯(logic)晶片，其具有相對之作用面29a與非作用面29b，且以其作用面29a之電極墊290藉由複數如銲錫材料之導電凸塊291採用覆晶方式設於該第二線路重佈層261上並電性連接該第二線路重佈層261，並以底膠292包覆該些導電凸塊291；或者，該電子元件29以其非作用面29b設於該第二線路結構26上，並可藉由複數銲線(圖略)以打線方式電性連接該第二線路重佈層261；亦或透過如導電膠或銲錫等導電材料(圖略)電性連接該第二線路重佈層261。然而，有關該電子元件29電性連接該第二線路重佈層261之方式不限於上述。
如第2G圖所示，沿如第2F圖所示之切割路徑S對該中介部2a進行切單製程，以獲取該電子封裝件2。
於本實施例中，可藉由該些導電元件27接置於一佈線板件8上側，如有機材板體(如具有核心層與線路部之封裝基板(substrate)或具有線路部之無核心層式(coreless)封裝基板)或無機材板體(如矽板材)，且該佈線板件8下側可接置於一如電路板之電子裝置(圖未示)上，並於該佈線板件8上側形成封裝材(圖略)以包覆該電子封裝件2。進一步，如第2H圖所示，可依需求配置一散熱件8a於該佈線板件8上，且該散熱件8a係藉由該黏著層80結合於該佈線板件8上，並使該散熱件8a結合於該電子元件29之非作用面29b上。
再者，於另一實施例中，如第2G’圖所示之電子封裝件2’，可依需求省略該第二線路結構26之製作，以令該電子元件29接置於該中介板21與該導電柱23上，底膠292接觸該包覆層25之第二表面25b。具體地，該電子元件29藉由該些導電凸塊291電性連接該導電穿孔210與該導電柱23。
或者，於其它實施例中，如第2G”圖所示之電子封裝件2”，亦可依需求省略該第一線路結構20之製作，以令該中介板21之導電穿孔210與該導電柱23藉由該些導電元件27接置該佈線板件8。
請參閱第3A至3D圖，係為本發明之電子封裝件3之製法之第二實施例的剖面示意圖。本實施例與第一實施例之差異在於電子元件之設置步驟，其它製程大致相同，故以下不再贅述相同處。
如第3A圖所示，先於承載板9之離型層90(或黏著層91)上設置電子元件29，再於該電子元件29上形成第二線路結構36，且該第二線路結構36係包括複數第二絕緣層360及設於該第二絕緣層360上之複數第二線路重佈層(RDL)361。
於另一實施例中，可依需求省略該第二線路結構36之製作，以令該導電柱23接置該電子元件29之電極墊290上，如第3A’圖所示。
如第3B圖所示，接續第3A圖之製程，將中介板21以其第二側21b藉由導電體22與結合層24設於該第二線路結構36上。
如第3C圖所示，以包覆層25包覆該中介板21、結合層24與該些導電柱23，再進行整平製程。接著，形成一第一線路結構30於該包覆層25之第一表面25a上，且該第一線路結構30電性連接該些導電柱23與該中介板21之導電穿孔210。
如第3D圖所示，移除該承載板9及其上之離型層90，以外露該電子元件29，再進行切單製程以獲取該電子封裝件3。
於本實施例中，該電子封裝件3可藉由該些導電元件27接置於一佈線板件8(如第3E圖所示)，且可依需求配置該散熱件8a(見第2G圖)於該佈線板件8上。
再者，若接續第3A’圖之製程，可得到如第3E’圖所示之電子封裝件3’，且中介板21藉由導電體22結合及電性連接該電子元件29。或者，於第3A圖之製程，可依需求省略該第一線路結構30之製作，並令該導電元件27接置於該導電穿孔210與該導電柱23上，以形成如第3E”圖所示之電子封裝件3”。
另外，於第一與第二實施例中，均可依需求省略該第一線路結構20,30與第二線路結構26,36之製作，以形成如第4及4’圖所示之電子封裝件4,4’。
因此，本發明之製法中，係以製作成本極低(如一般封裝製程用之銅柱製程)之導電柱23作為該電子元件29與該佈線板件8之間的電性傳輸結構，故相較於習知技術，即使接置於該中介部2a上之電子元件29之數量繁多，本發明之電子封裝件2,2’,2”,3,3’,3”,4,4’仍可製作較少的導電穿孔210，因而能減少製程時間及化學藥劑之成本，進而降低製程難度及製作成本，以提高良率。
再者，本發明之製法中，係藉由小尺寸的中介板21取代習知大面積矽中介板，故相較於習知技術之單一大尺寸矽中介板之良率(如製作10個TSV之良率為0.910)，本發明之每一個中介板21之良率較高(如單一個中介板21製作5個TSV之良率為0.95)，致使整體中介部2a之良率較高(整體10個TSV之良率為0.95)。
又，藉由該包覆層25包覆該些中介板21，以於後續形成該封裝材時，該包覆層25與該封裝材之間的熱膨脹係數(CTE)相匹配，因而容易平均分散熱應力，故於熱循環(thermal cycle)時，能避免該中介部2a 產生翹曲，因而能避免發生植球狀況不佳(即該導電元件27掉落而電性斷路)、導電元件27不沾錫(non-wetting)或該佈線板件8分裂等可靠度問題，進而能提升應用該電子封裝件之終端電子產品(如電腦、手機等)之可靠度問題。
另外，本發明之電子元件29之部分電性功能(如電源或接地)係藉由導電柱23作為電性傳輸路徑，因而本發明無需製作大面積之中介板21，故相較於習知技術，本發明能有效降低生產成本。
本發明亦提供一種電子封裝件2,2’,2”,3,3’,3”,4,4’，係包括一包覆層25、至少一中介板21、複數導電柱23以及至少一電子元件29。
所述之包覆層25係具有相對之第一表面25a與第二表面25b。
所述之中介板21係嵌埋於該包覆層25中，且該中介板21具有相對之第一側21a與第二側21b、及複數連通該第一側21a與第二側21b之導電穿孔210。
所述之導電柱23係形成於該包覆層25中並連通該包覆層25之第一表面25a與第二表面25b。
所述之電子元件29係形成於該包覆層25之第二表面25b上且電性連接該導電柱23與該導電穿孔210。
於一實施例中，該包覆層25之第一表面25a係齊平該中介板21之第一側21a之表面(如第2G”、3E、3E”、4及4’圖所示)；或者，該包覆層25之第二表面25b係齊平該中介板21之第二側21b之表面(如第2G、2G’、3E’、4及4’圖所示)。
於一實施例中，該包覆層25之第一表面25a係齊平該導電柱23之端面23a(如第2G”、3E、3E”、4及4’圖所示)；或者，該包覆層25之第二表面25b係齊平該導電柱23之端面23b(如第2G、2G’、3E’、4及4’圖所示)。
於一實施例中，該導電穿孔210係外露於該包覆層25之第一表面25a或第二表面25b。
於一實施例中，該導電柱23之端面23a係外露於該包覆層25之第一表面25a；或者，該導電柱23之端面23b係外露於該包覆層25之第二表面25b。
於一實施例中，該電子元件29係為主動元件、被動元件或其二者組合。
於一實施例中，該電子元件29藉由該第二線路結構26,36電性連接該導電柱23與該導電穿孔210。
於一實施例中，所述之電子封裝件2,2’,3,3’復包括形成於該包覆層25上之第一線路結構20,30及/或第二線路結構26,36，係電性連接該導電柱23與該導電穿孔210。例如，可於該包覆層25上之第一線路結構20,30上形成複數導電元件27，其藉由該第一線路結構20,30電性連接該導電柱23與該導電穿孔210。
於一實施例中，所述之電子封裝件2”,3”,4,4’復包括形成於該包覆層25之第一表面25a上的複數導電元件27，其電性連接該導電柱23與該導電穿孔210。
綜上所述，本發明之電子封裝件及其製法中，係藉由該導電柱與該中介板嵌埋於該包覆層中以作為中介部，以減少中介板中導電穿孔之數量，故不僅能降低成本，且能提高良率。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2‧‧‧電子封裝件
20‧‧‧第一線路結構
21‧‧‧中介板
210‧‧‧導電穿孔
23‧‧‧導電柱
25‧‧‧包覆層
25a‧‧‧第一表面
25b‧‧‧第二表面
26‧‧‧第二線路結構
27‧‧‧導電元件
29‧‧‧電子元件
8‧‧‧佈線板件

Claims (23)

  1. 一種電子封裝件，係包括：一包覆層；至少一中介板，係嵌埋於該包覆層中且具有複數導電穿孔；複數導電柱，係形成於該包覆層中；以及至少一電子元件，係設於該包覆層上且電性連接該導電柱與該導電穿孔。
  2. 如申請專利範圍第1項所述之電子封裝件，其中，該包覆層之表面係齊平該中介板之表面。
  3. 如申請專利範圍第1項所述之電子封裝件，其中，該包覆層之表面係齊平該導電柱之端面。
  4. 如申請專利範圍第1項所述之電子封裝件，其中，該導電穿孔係外露於該包覆層之表面。
  5. 如申請專利範圍第1項所述之電子封裝件，其中，該導電柱之端面係外露於該包覆層之表面。
  6. 如申請專利範圍第1項所述之電子封裝件，其中，該電子元件係為主動元件、被動元件或其二者組合。
  7. 如申請專利範圍第1項所述之電子封裝件，其中，該電子元件藉由線路結構電性連接該導電柱與該導電穿孔。
  8. 如申請專利範圍第1項所述之電子封裝件，復包括形成於該包覆層上且電性連接該導電柱與該導電穿孔之線路結構。
  9. 如申請專利範圍第8項所述之電子封裝件，復包括形成於該線路結構上之複數導電元件，且該複數導電元件係藉由該線路結構電性連接該導電柱與該導電穿孔。
  10. 如申請專利範圍第1項所述之電子封裝件，復包括形成於該包覆層上之複數導電元件，且該複數導電元件係電性連接該導電柱與該導電穿孔。
  11. 一種電子封裝件之製法，係包括：提供一包覆層，其嵌埋有至少一中介板與複數導電柱，且該中介板具有複數導電穿孔；以及設置電子元件於該包覆層之其中一側上，且令該電子元件電性連接該導電柱與該導電穿孔。
  12. 如申請專利範圍第11項所述之電子封裝件之製法，復包括：提供第一線路結構；將該導電柱與該中介板結合於該第一線路結構上，以令該第一線路結構電性連接該導電柱與該導電穿孔；以及將該包覆層結合於該第一線路結構上，以令該包覆層包覆該中介板與該導電柱。
  13. 如申請專利範圍第11或12項所述之電子封裝件之製法，復包括於該包覆層上形成第二線路結構，以令該電子元件設於該第二線路結構上，使該電子元件藉由該第二線路結構電性連接該導電柱與該導電穿孔。
  14. 如申請專利範圍第11項所述之電子封裝件之製法，復包括於該包覆層之另一側上形成複數導電元件，以令該複數導電元件電性連接該導電柱與該導電穿孔。
  15. 一種電子封裝件之製法，係包括：提供一電子元件；將複數導電柱與至少一中介板結合於該電子元件上，其中，該中介板具有複數導電穿孔，且令該導電柱與該導電穿孔電性連接該電子元件；以及藉由包覆層包覆該中介板與該導電柱。
  16. 如申請專利範圍第15項所述之電子封裝件之製法，復包括形成第一線路結構於該包覆層上，以令該第一線路結構電性連接該導電柱與該導電穿孔。
  17. 如申請專利範圍第15或16項所述之電子封裝件之製法，復包括：形成第二線路結構於該電子元件上；將該導電柱與該中介板結合於該第二線路結構上，以令該第二線路結構電性連接該導電柱與該導電穿孔；以及將該包覆層結合於該第二線路結構上，以令該包覆層包覆該中介板與該導電柱。
  18. 如申請專利範圍第15項所述之電子封裝件之製法，復包括於該包覆層上形成複數導電元件，以令該複數導電元件電性連接該導電柱與該導電穿孔。
  19. 如申請專利範圍第11或15項所述之電子封裝件之製法，其中，該包覆層係具有相對之第一表面與第二表面，且該第二表面係齊平該中介板之表面。
  20. 如申請專利範圍第11或15項所述之電子封裝件之製法，其中，該包覆層係具有相對之第一表面與第二表面，且該第二表面係齊平該導電柱之端面。
  21. 如申請專利範圍第11或15項所述之電子封裝件之製法，其中，該包覆層係具有相對之第一表面與第二表面，且該導電穿孔係外露於該包覆層之第二表面。
  22. 如申請專利範圍第11或15項所述之電子封裝件之製法，其中，該包覆層係具有相對之第一表面與第二表面，且該導電柱之端面係外露於該包覆層之第二表面。
  23. 如申請專利範圍第11或15項所述之電子封裝件之製法，其中，該電子元件係為主動元件、被動元件或其二者組合。
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