TWI778406B - 電子封裝件及其製法 - Google Patents

電子封裝件及其製法 Download PDF

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Publication number
TWI778406B
TWI778406B TW109129145A TW109129145A TWI778406B TW I778406 B TWI778406 B TW I778406B TW 109129145 A TW109129145 A TW 109129145A TW 109129145 A TW109129145 A TW 109129145A TW I778406 B TWI778406 B TW I778406B
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Taiwan
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electronic
conductive
electrically connected
conductor
cladding layer
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TW109129145A
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English (en)
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TW202209508A (zh
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高灃
王隆源
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矽品精密工業股份有限公司
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Priority to TW109129145A priority Critical patent/TWI778406B/zh
Priority to CN202010919334.4A priority patent/CN114121833A/zh
Priority to US17/101,277 priority patent/US11984393B2/en
Publication of TW202209508A publication Critical patent/TW202209508A/zh
Application granted granted Critical
Publication of TWI778406B publication Critical patent/TWI778406B/zh
Priority to US18/389,105 priority patent/US20240162140A1/en

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Abstract

一種電子封裝件，係將一作為集成穩壓器之電子結構及複數導電柱嵌埋於包覆層中，以利於近距離配合電子元件進行電性傳輸。

Description

電子封裝件及其製法
本發明係有關一種半導體裝置，尤指一種電子封裝件及其製法與電子結構。
隨著電子產業的蓬勃發展，電子產品也逐漸邁向多功能、高性能的趨勢。例如，集成穩壓器(IVR)嵌入高性能處理器中，以提高效率，如開關頻率、降低功耗，且可提高可靠性，甚至降低製作成本。同時，目前應用於晶片封裝領域之技術，包含有例如晶片尺寸構裝(Chip Scale Package，簡稱CSP)、晶片直接貼附封裝(Direct Chip Attached，簡稱DCA)或多晶片模組封裝(Multi-Chip Module，簡稱MCM)等覆晶型態的封裝模組，或將晶片立體堆疊化整合為三維積體電路(3D IC)晶片堆疊技術等。
圖1係為習知3D晶片堆疊之封裝結構1之剖面示意圖。如圖1所示，該封裝結構l包括一矽中介板(Through Silicon interposer，簡稱TSI)1a，其具有一矽板體10及複數形成於其中之導電矽穿孔(Through-silicon via，簡稱TSV)101，且該矽板體10之表面上形成有一電性連接該導電矽穿孔101之線路重佈結構(Redistribution layer，簡稱RDL)。具體地，該線路重佈結構係包含一介電層11及 一形成於該介電層11上之線路層12，且該線路層12電性連接該導電矽穿孔101，並形成一絕緣保護層13於該介電層11與該線路層12上，且該絕緣保護層13外露部分該線路層12，以結合複數銲錫凸塊14。
再者，可先形成另一絕緣保護層15於該矽板體10上，且該絕緣保護層15外露該些導電矽穿孔101之端面，以結合複數銲錫凸塊16於該些導電矽穿孔101之端面上，且該銲錫凸塊16電性連接該導電矽穿孔101，其中，可選擇性於該導電矽穿孔101之端面上形成供接置該銲錫凸塊16之凸塊底下金屬層(Under Bump Metallurgy，簡稱UBM)160。
又，該封裝結構1復包括一封裝基板19，供該矽中介板1a藉由該些銲錫凸塊16設於其上，使該封裝基板19電性連接該些導電矽穿孔101，且以底膠191包覆該些第二導電元件16。
另外，該封裝結構1復包括複數系統單晶片(System-On-Chip，簡稱SOC)型半導體晶片17，其設於該些銲錫凸塊14上，使該半導體晶片17電性連接該線路層12，且以底膠171包覆該些銲錫凸塊14，並形成封裝材18於該封裝基板19上，以令該封裝材18包覆該半導體晶片17與該矽中介板1a。
於後續應用中，該封裝結構1可形成複數銲球192於該封裝基板19之下側，以接置於一電路板1’上。
早期商品化產品中，係將一穩壓器(IVR)1b’直接安裝於該電路板上，但此方法將造成終端產品的體積無法達到輕薄短小的要求，且該穩壓器1b’與該封裝結構1之距離過遠，造成與其相關電性連接的半導體晶片17傳遞訊號之路徑過遠，導致電性功能下降，致使功耗隨之增加。
因此，業界遂將該穩壓器1b整合至與該封裝基板19之下側，以縮短該穩壓器1b與該半導體晶片17之間的傳輸距離，藉此縮減該電路板1’之表面積及體積。
惟，隨著消費市場需求，現今終端產品之功能需求越加繁多，故接置於該封裝基板19上之半導體晶片17越來越多，因而與其配合之穩壓器1b之需求量大增，致使該封裝基板19之下側並無多餘空間配置更多穩壓器1b，導致單一封裝結構1已無法符合現今終端產品相關輕薄短小、低功耗、高電性效能等需求。
再者，雖可將該穩壓器1b整合於該半導體晶片17中，但需重新設計該封裝結構1，不僅增加製作成本，且需擴增該半導體晶片17之尺寸，因而難以符合微小化之需求。
因此，如何克服上述習知技術之種種問題，實已成為目前業界亟待克服之難題。
鑑於上述習知技術之種種缺失，本發明係提供一種電子主體，其具有相對之第一側與第二側，其中，該電子主體係具有一基部與一形成於該基部上之線路部，以令該基部定義出該第二側，而該線路部則定義出該第一側，且該基部中具有複數電性連接該線路部並外露出該第二側之導電穿孔；複數第一導電體，係形成於該電子主體之第一側上以電性連接該線路部；複數第二導電體，係形成於該電子主體之第二側上以電性連接該導電穿孔；一第一絕緣層，係形成 於該電子主體之第一側上以包覆該第一導電體；以及一第二絕緣層，係形成於該電子主體之第二側上以包覆該第二導電體。
前述之電子結構中，該電子結構係作為集成穩壓器。
前述之電子結構中，該第一導電體係外露出該第一絕緣層。
前述之電子結構中，該第二導電體係未外露出該第二絕緣層。
本發明亦提供一種電子封裝件，係包括：一包覆層，係具有相對之第一表面與第二表面；一如前述之電子結構，係嵌埋於該包覆層中；以及複數導電柱，係嵌埋於該包覆層中。
前述之電子封裝件中，該導電柱之端面、該第二絕緣層或該第二導電體係外露出該包覆層之第二表面。
前述之電子封裝件中，復包括形成於該包覆層之第一表面及/或第二表面上之線路結構，其電性連接該複數導電柱與該電子結構。
前述之電子封裝件中，復包括形成於該包覆層之第一表面上的複數導電元件，其電性連接該導電柱及/或該第一導電體。
前述之電子封裝件中，復包括接置於該包覆層之第二表面上的電子元件，其電性連接該第二導電體及/或該導電柱。
前述之電子封裝件中，復包括嵌埋於該包覆層中之電子元件。
本發明復提供一種電子封裝件之製法，係包括：提供一電子主體，其具有相對之第一側與第二側，其中，該電子主體係具有一基部與一形成於該基部上之線路部，以令該基部定義出該第二側，而該線路部則定義出該第一側，且該基部中具有複數電性連接該線路部並外露出該第二側之導電穿孔；於該電子主體之第一側及第二側上分別形成複數第一導電體及第二導電體，以令該第一導電體電性連接該線路部，而該第二導電體電性連接該導電穿孔，且於該電子主體之第一側與第二側上分別形成第一絕緣層與第二絕緣層，使該第一絕緣層與 第二絕緣層包覆該第一導電體與第二導電體，以形成電子結構；將該電子結構以其第一絕緣層設於一承載板上，且於該承載板上形成有複數導電柱；形成包覆層於該承載板上，以包覆該電子結構與導電柱，其中，該包覆層係具有相對之第一表面與第二表面，且該包覆層以其第一表面結合該承載板；以及移除該承載板。
前述之製法中，該包覆層之第二表面係齊平該導電柱之端面、該第二絕緣層或該第二導電體。
前述之製法中，該導電柱之端面、該第二絕緣層或該第二導電體係外露出該包覆層之第二表面。
前述之製法中，該承載板上係形成有第一線路結構，以接置該電子結構及複數導電柱，且該複數導電柱與該電子結構之第一導電體係電性連接該第一線路結構，並使該包覆層以其第一表面結合該第一線路結構。例如，該第一導電體係藉由導電凸塊電性連接該第一線路結構。
前述之製法中，復包括於移除該承載板後，形成複數導電元件於該包覆層之第一表面上，以令該複數導電元件電性連接該導電柱及/或該第一導電體。
前述之製法中，復包括形成第二線路結構於該包覆層之第二表面上，以令該第二線路結構電性連接該導電柱與該第二導電體。例如，復包括於該第二線路結構上接置電子元件，以令該電子元件電性連接該第二線路結構。
前述之製法中，復包括將電子元件接置於該包覆層之第二表面上，以令該電子元件電性連接該第二導電體及/或該導電柱。
前述之製法中，復包括於該電子結構設於該承載板上時，設置電子元件於該承載板上。
由上可知，本發明之電子封裝件及其製法與電子結構中，主要藉由將該電子結構嵌埋於該包覆層中以近距離配合該電子元件，故相較於習知 技術，本發明無需重新設計該電子封裝件，因而能大幅節省製作成本，且無需擴增該電子元件之尺寸，以利於滿足微小化之需求，並有利於呈現高電性效能。
1:封裝結構
1’:電路板
1a:矽中介板
1b,1b’:穩壓器
10:矽板體
101:導電矽穿孔
11:介電層
12:線路層
13,15,203:絕緣保護層
14,16:銲錫凸塊
160:凸塊底下金屬層
17:半導體晶片
171,191,292:底膠
18:封裝材
19:封裝基板
192:銲球
2,2’,4:電子封裝件
2a:整版面晶圓體
2b:電子結構
20:第一線路結構
200:第一介電層
201:第一線路重佈層
21:電子主體
21’:基部
21”:線路部
21a:第一側
21b:第二側
210:導電穿孔
211:鈍化層
212:線路層
22,291:導電凸塊
23:導電柱
23b:端面
24:結合層
25:包覆層
25a:第一表面
25b:第二表面
26:第二線路結構
260:第二介電層
261:第二線路重佈層
27:導電元件
28a:第一絕緣層
28b:第二絕緣層
280a:第一導電體
280b:第二導電體
29:第一電子元件
29a,41a:作用面
29b,41b:非作用面
290,410,410’:電極墊
41:第二電子元件
411,91:黏著層
8:佈線板件
9:承載板
90:離形層
L,S:切割路徑
T:封裝部
圖1係為習知封裝結構之剖視示意圖。
圖2A至圖2H係為本發明之電子封裝件之製法之第一實施例之剖視示意圖。
圖2H’係為對應圖2H之其它實施例之剖視示意圖。
圖3係為圖2H之後續製程之剖視示意圖。
圖4A至圖4B係為本發明之電子封裝件之製法之第二實施例之剖視示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」、「第一」、「第二」、「一」等之用語，亦僅為便於敘述之 明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
圖2A至圖2H係為本發明之電子封裝件2之製法之第一實施例的剖面示意圖。
如圖2A所示，提供一整版面晶圓體2a，其包含複數陣列排列之電子主體21，且該電子主體21具有相對之第一側21a與第二側21b。
於本實施例中，該電子主體21係為主動元件，如半導體晶片，其具有一矽材基部21’與一形成於該基部21’上之線路部21”，且該基部21’中具有複數外露出該基部21’之導電穿孔210，如導電矽穿孔(Through-silicon via，簡稱TSV)，以電性連接該線路部21”。例如，該線路部21”係包含至少一鈍化層211及結合該鈍化層211之線路層212，以令該線路層212電性連接該導電穿孔210。具體地，該基部21’係定義出該第二側21b，且該線路部21”係定義出該第一側21a。應可理解地，有關具有該導電穿孔210之主動元件之結構態樣繁多，並無特別限制。
如圖2B所示，進行薄化製程，如藉由研磨方式，移除該電子主體21之第二側21b(或該基部21’)之部分材質，以令該導電穿孔210外露出該第二側21b。
如圖2C所示，形成複數第一導電體280a與第二導電體280b於該電子主體21之第一側21a與第二側21b上，以令該些第一導電體280a與第二導電體280b電性連接該線路層212與導電穿孔210。
於本實施例中，各該導電穿孔210之外露兩端分別接觸該第一導電體280a與第二導電體280b。例如，該第一導電體280a與第二導電體280b係為如銅柱之金屬柱。
再者，可分別形成第一絕緣層28a與第二絕緣層28b於該電子主體21之第一側21a與第二側21b上，使該第一絕緣層28a與第二絕緣層28b包覆該些第一導電體280a與第二導電體280b。例如，該第一絕緣層28a係外露出該第一導電體280a，以結合複數導電凸塊22。具體地，該導電凸塊22係為如銅柱、銲錫球等金屬凸塊。另一方面，該第二導電體280b係未外露出該第二絕緣層28b。
又，可沿切割路徑L進行切單製程，以獲取複數電子結構2b，其作為集成穩壓器(Integrated Voltage Regulator，簡稱IVR)。
如圖2D所示，提供一設於承載板9上之第一線路結構20，且於該第一線路結構20上形成有複數導電柱23，以將至少一電子結構2b設於該第一線路結構20上。
於本實施例中，該第一線路結構20係包含至少一第一介電層200與至少一設於該第一介電層200上之第一線路重佈層(Redistribution layer，簡稱RDL)201。例如，形成該第一線路重佈層201之材質係為銅，且形成該第一介電層200之材質係如聚對二唑苯(Polybenzoxazole，簡稱PBO)、聚醯亞胺(Polyimide，簡稱PI)、預浸材(Prepreg，簡稱PP)或其它等之介電材。
再者，該承載板9係例如為半導體材質(如矽或玻璃)之板體，其上可依需求依序形成有一離形層90與一黏著層91，以供該第一線路結構20設於該黏著層91上。
又，該導電柱23係設於該第一線路重佈層201上並電性連接該第一線路重佈層201，且形成該導電柱23之材質係為如銅之金屬材或銲錫材。
另外，該電子結構2b係藉由複數導電凸塊22結合至該第一線路結構20上以電性連接該第一線路重佈層201。例如，可依需求以如底膠之結合層24包覆該些導電凸塊22。
如圖2E所示，形成一包覆層25於該第一線路結構20上，以令該包覆層25包覆該電子結構2b、結合層24與該些導電柱23，其中，該包覆層25係具有相對之第一表面25a與第二表面25b，且其以第一表面25a結合該第一線路結構20。接著，藉由整平製程，使該包覆層25之第二表面25b齊平該導電柱23之端面23b與該電子結構2b之第二絕緣層28b(或該第二導電體280b之端面)，令該導電柱23之端面23b與該電子結構2b之第二絕緣層28b(或該第二導電體280b之端面)外露出該包覆層25之第二表面25b。
於本實施例中，該包覆層25係為絕緣材，如環氧樹脂之封裝膠體，其可用壓合(lamination)或模壓(molding)之方式形成於該第一線路結構20上。
再者，該整平製程係藉由研磨方式，移除該導電柱23之部分材質、該電子結構2b之第二絕緣層28b(或該第二導電體280b)之部分材質與該包覆層25之部分材質。
又，若未形成該結合層24，該包覆層25可包覆該些導電凸塊22。
如圖2F所示，形成一第二線路結構26於該包覆層25之第二表面25b上，且令該第二線路結構26電性連接該些導電柱23與該電子結構2b之第二導電體280b。
於本實施例中，該第二線路結構26係包括複數第二介電層260、及設於該第二介電層260上之複數第二線路重佈層(RDL)261，且最外層之第二絕緣層260可作為防銲層，以令最外層之第二線路重佈層261部分外露出該防銲層。或者，該第二線路結構26亦可僅包括單一第二介電層260及單一第二線路重佈層261。
再者，形成該第二線路重佈層261之材質係為銅，且形成該第二介電層260之材質係為如聚對二唑苯(PBO)、聚醯亞胺(PI)、預浸材(PP)或其它等之介電材。
如圖2G所示，移除該承載板9及其上之離形層90與黏著層91，以外露該第一線路結構20。
於本實施例中，該包覆層25、電子結構2b與該些導電柱23可作為封裝部T，其可依需求包含該第一線路結構20及/或第二線路結構26。
如圖2H所示，於最外層之第二線路重佈層261上接置至少一第一電子元件29，且可形成複數如銲球之導電元件27於該包覆層25之第一表面25a(或該第一線路結構20)上，以令該複數導電元件27電性連接該導電柱23及/或該第一導電體280a。
於本實施例中，可形成一如防銲層之絕緣保護層203於該第一線路結構20上，且於該絕緣保護層203上形成複數開孔，以令該第一線路重佈層201外露出該些開孔，俾供結合該導電元件27，使該導電元件27藉由該第一線路結構20電性連接該導電柱23及/或該第一導電體280a。
再者，該第一電子元件29係為主動元件、被動元件或其二者組合等，其中，該主動元件係例如半導體晶片，且該被動元件係例如電阻、電容及電感。例如，該第一電子元件29係為半導體晶片，如系統單晶片(System-On-Chip，簡稱SOC)型之功能晶片，其具有相對之作用面29a與非作用面29b，且以其作用面29a之電極墊290藉由複數如銲錫材料之導電凸塊291採用覆晶方式設於該第二線路重佈層261上並電性連接該第二線路重佈層261，並以底膠292包覆該些導電凸塊291；或者，該第一電子元件29以其非作用面29b設於該第二線路結構26上，並可藉由複數銲線(圖略)以打線方式電性連接該第二線路重佈層261；亦或透過如導電膠或銲錫等導電材料(圖略)電性連接該第二線路重佈層261。然而，有關該第一電子元件29電性連接該第二線路重佈層261之方式不限於上述。
如圖2H所示，沿所示之切割路徑S對該封裝部T進行切單製程，以獲取該電子封裝件2。
於本實施例中，如圖3所示，於後續製程中電子封裝件2可藉由該些導電元件27接置於一佈線板件8上側，如有機材板體(如具有核心層與線路之封裝基板(substrate)或具有線路之無核心層式(coreless)封裝基板)或無機材板體(如矽板材)，且該佈線板件8下側可接置於一如電路板之電子裝置(圖未示)上。
再者，於另一實施例中，如圖2H’圖所示之電子封裝件2’，可依需求省略該第二線路結構26之製作。例如，將該第一電子元件29接置於該包覆層25之第二表面25b上，以令該第一電子元件29電性連接該第二導電體280b及/或該導電柱23。具體地，該第一電子元件29係採用覆晶方式藉由該些導電凸塊291接置於該電子結構2b之第二導電體280b與該導電柱23上，以電性連接該第二導電體280b與該導電柱23，且該底膠292接觸該包覆層25之第二表面25b。
因此，本發明之製法藉由將作為IVR之電子結構2b嵌埋於該包覆層25中以對接該第一電子元件29，以利於配合不同功能之第一電子元件29，故相較於習知將IVR整合於SOC中，本發明之製法無需重新設計該電子封裝件2,2’，因而能大幅節省製作成本，且無需擴增該第一電子元件29之尺寸，以利於滿足微小化之需求。
再者，相較於習知將IVR整合至電路板或封裝基板上，本發明之電子結構2b與該第一電子元件29之間的電性傳輸距離可最短化(無需經過封裝基板或電路板)，以利於降低損耗及縮小該電子封裝件2,2’之尺寸，並提升電性效能。
請參閱圖4A及圖4B，係為本發明之電子封裝件4之製法之第二實施例的剖面示意圖。本實施例與第一實施例之差異在於第二電子元件之配置，其它製程大致相同，故以下不再贅述相同處。
如圖4A所示，於圖2D所示之製程中，當該電子結構2b設於該承載板9(或該第一線路結構20)上時，一併設置至少一第二電子元件41於該承載板9(或該第一線路結構20)上。
於本實施例中，該第二電子元件41係為主動元件、被動元件或其二者組合等，其中，該主動元件係例如半導體晶片，且該被動元件係例如電阻、電容及電感。例如，該第二電子元件41係為半導體晶片，如矽材架橋(Si bridge)晶片，其具有相對之作用面41a與非作用面41b，該作用面41a具有複數電極墊410，且該第二電子元件41以其非作用面41b藉由黏著層411設於該第一線路結構20(或承載板9)上，並以其作用面41a上之電極墊410於後續製程中(如圖4B所示)電性連接該第二線路重佈層261。
再者，該電子結構2b可於其中一側上依需求形成至少一電極墊410’，以電性連接該第一電子元件29或該第二線路結構26。
又，可依需求省略該第一線路結構20之製作，使該電子結構2b與該第二電子元件41設於該承載板9(其上可具有離形層90與黏著層91)上，且該承載板9上形成有複數導電柱23。
如圖4B所示，進行如圖2E至圖2H所示之封裝製程中，以獲取複數電子封裝件4。
於本實施例中，若省略該第一線路結構20之製作，該包覆層25將形成於該承載板9(其上可具有離形層90與黏著層91)上，且於移除該承載板9(一併移除該離形層90與黏著層91)後，該電子結構2b之第一導電體280a與該導電柱23可藉由該些導電元件27接置該佈線板件8。
因此，本發明之製法藉由將該電子結構2b嵌埋於該包覆層25中以對接該第一電子元件29或並排該第二電子元件41，以利於配合不同功能之第一電子元件29或第二電子元件41，故相較於習知將IVR整合於SOC中，本發明之製 法無需重新設計該電子封裝件4，因而能大幅節省製作成本，且無需擴增該第一電子元件29或第二電子元件41之尺寸，以利於滿足微小化之需求。
再者，相較於習知將IVR整合至電路板或封裝基板上，本發明之電子結構2b與該第一電子元件29或第二電子元件41之間的電性傳輸距離可最短化(無需經過封裝基板或電路板)，以利於降低損耗及縮小該電子封裝件4之尺寸，並提升電性效能。
本發明復提供一種電子結構2b，係包括：一電子主體21、複數第一導電體280a、複數第二導電體280b、一第一絕緣層28a以及一第二絕緣層28b。
所述之電子主體21係具有相對之第一側21a與第二側21b，其中，該電子主體21係具有一基部21’與一形成於該基部21’上之線路部21”，以令該基部21’定義出該第二側21b，而該線路部21”則定義出該第一側21a，且該基部21’中具有複數電性連接該線路部21”並外露出該第二側21b之導電穿孔210。
所述之第一導電體280a係形成於該電子主體21之第一側21a上以電性連接該線路部21”。
所述之第二導電體280b係形成於該電子主體21之第二側21b上以電性連接該導電穿孔210。
所述之第一絕緣層28a係形成於該電子主體21之第一側21a上以包覆該第一導電體280a。
所述之第二絕緣層28b係形成於該電子主體21之第二側21b上以包覆該第二導電體280b。
於一實施例中，該電子結構2b係作為集成穩壓器。
於一實施例中，該第一導電體280a係外露出該第一絕緣層28a。
於一實施例中，該第二導電體280b係未外露出該第二絕緣層28b。
本發明亦提供一種電子封裝件2,2’,4，係包括：一包覆層25、至少一電子結構2b以及複數導電柱23。
所述之包覆層25係具有相對之第一表面25a與第二表面25b。
所述之電子結構2b係嵌埋於該包覆層25中。
所述之導電柱23係嵌埋於該包覆層25中。
於一實施例中，該導電柱23之端面、該第二絕緣層28b或該第二導電體280b係外露出該包覆層25之第二表面25b。
於一實施例中，所述之電子封裝件2,2’,4復包括形成於該包覆層25之第一表面25a及/或第二表面25b上之線路結構(即該第一線路結構20與第二線路結構26)，其電性連接該複數導電柱23與該電子結構2b。
於一實施例中，所述之電子封裝件2,2’,4復包括形成於該包覆層25之第一表面25a上的複數導電元件27，其電性連接該導電柱23及/或該第一導電體280a。
於一實施例中，所述之電子封裝件2,2’,4復包括至少一接置於該包覆層25之第二表面25b上的第一電子元件29，其電性連接該第二導電體280b及/或該導電柱23。
於一實施例中，所述之電子封裝件4復包括嵌埋於該包覆層25中之第二電子元件41。
綜上所述，本發明之電子封裝件及其製法與電子結構，係藉由將該電子結構嵌埋於該包覆層中以近距離配合該電子元件，故本發明無需重新設計該電子封裝件，因而能大幅節省製作成本，且無需擴增該電子元件之尺寸，以利於滿足微小化之需求，並有利於呈現高電性效能。
再者，藉由將作為IVR之電子結構嵌埋於該包覆層中，使該電子封裝件可適用於伺服器或基站處理器。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2:電子封裝件
2b:電子結構
20:第一線路結構
21:電子主體
21’:基部
21”:線路部
210:導電穿孔
23:導電柱
25:包覆層
25a:第一表面
25b:第二表面
26:第二線路結構
27:導電元件
29:第一電子元件
8:佈線板件

Claims (20)

  1. 一種電子封裝件，係包括：一包覆層，係具有相對之第一表面與第二表面；一種電子結構，係嵌埋於該包覆層中，更包括：一電子主體，其具有相對之第一側與第二側，其中，該電子主體係具有一基部與一形成於該基部上之線路部，以令該基部定義出該第二側，而該線路部則定義出該第一側，且該基部中具有複數電性連接該線路部並外露出該第二側之導電穿孔；複數第一導電體，係形成於該電子主體之第一側上以電性連接該線路部；複數第二導電體，係形成於該電子主體之第二側上以電性連接該導電穿孔；一第一絕緣層，係形成於該電子主體之第一側上以包覆該第一導電體；及一第二絕緣層，係形成於該電子主體之第二側上以包覆該第二導電體；複數導電柱，係嵌埋於該包覆層中；以及一第一線路結構，係形成於該包覆層之第一表面上以電性連接該導電柱與該第一導電體，且該第一導電體係藉由導電凸塊電性連接該第一線路結構。
  2. 一種電子封裝件，係包括：一包覆層，係具有相對之第一表面與第二表面；一種電子結構，係嵌埋於該包覆層中，更包括： 一電子主體，其具有相對之第一側與第二側，其中，該電子主體係具有一基部與一形成於該基部上之線路部，以令該基部定義出該第二側，而該線路部則定義出該第一側，且該基部中具有複數電性連接該線路部並外露出該第二側之導電穿孔；複數第一導電體，係形成於該電子主體之第一側上以電性連接該線路部；複數第二導電體，係形成於該電子主體之第二側上以電性連接該導電穿孔；一第一絕緣層，係形成於該電子主體之第一側上以包覆該第一導電體；及一第二絕緣層，係形成於該電子主體之第二側上以包覆該第二導電體；複數導電柱，係嵌埋於該包覆層中；以及一第二線路結構，係形成於該包覆層之第二表面上以電性連接該導電柱與該第二導電體。
  3. 如請求項1或2所述之電子封裝件，其中，該第一導電體係外露出該第一絕緣層。
  4. 如請求項1或2所述之電子封裝件，其中，該第二導電體係未外露出該第二絕緣層。
  5. 如請求項1或2所述之電子封裝件，其中，該電子結構係作為集成穩壓器。
  6. 如請求項1或2所述之電子封裝件，其中，該導電柱之端面、該第二絕緣層或該第二導電體係外露出該包覆層之第二表面。
  7. 如請求項1所述之電子封裝件，復包括形成於該第一線路結構上的複數導電元件，其電性連接該導電柱及/或該第一導電體。
  8. 如請求項2所述之電子封裝件，復包括形成於該包覆層之第一表面上的複數導電元件，其電性連接該導電柱及/或該第一導電體。
  9. 如請求項1所述之電子封裝件，復包括接置於該包覆層之第二表面上的電子元件，其電性連接該第二導電體及/或該導電柱。
  10. 如請求項2所述之電子封裝件，復包括接置於該第二線路結構上的電子元件，其電性連接該第二導電體及/或該導電柱。
  11. 如請求項1或2所述之電子封裝件，復包括嵌埋於該包覆層中之電子元件。
  12. 一種電子封裝件之製法，係包括：提供一電子主體，其具有相對之第一側與第二側，其中，該電子主體係具有一基部與一形成於該基部上之線路部，以令該基部定義出該第二側，而該線路部則定義出該第一側，且該基部中具有複數電性連接該線路部並外露出該第二側之導電穿孔；於該電子主體之第一側及第二側上分別形成複數第一導電體及第二導電體，以令該第一導電體電性連接該線路部，而該第二導電體電性連接該導電穿孔，且於該電子主體之第一側與第二側上分別形成第一絕緣層與第二絕緣層，使該第一絕緣層與第二絕緣層包覆該第一導電體與第二導電體，以形成電子結構；將該電子結構以其第一絕緣層設於一承載板上，且於該承載板上形成有複數導電柱及第一線路結構，該第一線路結構接置該電子結構及該複數導電柱，且該複數導電柱與該電子結構之第一導電體係電性連接該第一線路結構； 形成包覆層於該第一線路結構上，以包覆該電子結構與導電柱，其中，該包覆層係具有相對之第一表面與第二表面，且該包覆層以其第一表面結合該第一線路結構；以及移除該承載板。
  13. 如請求項12所述之電子封裝件之製法，其中，該包覆層之第二表面係齊平該導電柱之端面、該第二絕緣層或該第二導電體。
  14. 如請求項12所述之電子封裝件之製法，其中，該導電柱之端面、該第二絕緣層或該第二導電體係外露出該包覆層之第二表面。
  15. 如請求項12所述之電子封裝件之製法，其中，該第一導電體係藉由導電凸塊電性連接該第一線路結構。
  16. 如請求項12所述之電子封裝件之製法，復包括於移除該承載板後，形成複數導電元件於該包覆層之第一表面上，以令該複數導電元件電性連接該導電柱及/或該第一導電體。
  17. 如請求項12所述之電子封裝件之製法，復包括形成第二線路結構於該包覆層之第二表面上，以令該第二線路結構電性連接該導電柱與該第二導電體。
  18. 如請求項17所述之電子封裝件之製法，復包括於該第二線路結構上接置電子元件，以令該電子元件電性連接該第二線路結構。
  19. 如請求項12所述之電子封裝件之製法，復包括將電子元件接置於該包覆層之第二表面上，以令該電子元件電性連接該第二導電體及/或該導電柱。
  20. 如請求項12所述之電子封裝件之製法，復包括於該電子結構設於該承載板上時，設置電子元件於該承載板上。
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