TW202029425A - 經封裝裝置及其形成方法 - Google Patents

經封裝裝置及其形成方法 Download PDF

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TW202029425A
TW202029425A TW108147194A TW108147194A TW202029425A TW 202029425 A TW202029425 A TW 202029425A TW 108147194 A TW108147194 A TW 108147194A TW 108147194 A TW108147194 A TW 108147194A TW 202029425 A TW202029425 A TW 202029425A
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Taiwan
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package
die
component
packaging component
dielectric layer
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TW108147194A
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TWI724706B (zh
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賴季暉
余振華
劉重希
蔡豪益
潘國龍
郭庭豪
賴昱嘉
淑蓉 鄭
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台灣積體電路製造股份有限公司
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Abstract

一種經封裝半導體裝置及一種經封裝半導體裝置的形成方法，經封裝半導體裝置包含設置於電力模組與含積體電路的封裝之間的含積體被動裝置的封裝組件。在一實施例中，裝置包含：第一封裝組件，包含第一積體電路晶粒、至少部分地包圍第一積體電路晶粒的第一包封體以及位於第一包封體上且耦接至第一積體電路晶粒的重佈線結構；第二封裝組件，接合至第一封裝組件，第二封裝組件包含積體被動裝置以及至少部分地包圍積體被動裝置的第二包封體；以及電力模組，經由第二封裝組件附接至第一封裝組件。

Description

積體電路封裝及方法
由於各種電子組件（例如電晶體、二極體、電阻器、電容器等）的積集度的持續提高，半導體行業已經歷快速發展。在很大程度上，積集度的提高源自於最小特徵尺寸的持續減小，其允許較多組件整合至給定區域中。隨著對於縮小的電子裝置的需求增長，已出現對於更小且更具創造性的半導體晶粒的封裝技術的需求。此類封裝系統的實例為疊層封裝（Package-on-Package；PoP）技術。在PoP裝置中，頂部半導體封裝堆疊於底部半導體封裝的頂部上，以提供高積集度及高組件密度。PoP技術通常使得能夠產生具有增強的功能性且在印刷電路板（printed circuit board；PCB）上的佔據面積小的半導體裝置。
以下揭露內容提供用以實施本發明的不同特徵的許多不同實施例或實例。以下描述組件及配置的特定實例以簡化本揭露內容。當然，此等組件及配置僅為實例且並不意欲為限制性的。舉例而言，在以下描述中，第一特徵在第二特徵上方或在第二特徵上的形成可包含第一特徵與第二特徵直接接觸地形成的實施例，且亦可包含額外特徵可在第一特徵與第二特徵之間形成使得第一特徵與第二特徵可不直接接觸的實施例。另外，本揭露內容可在各種實例中重複附圖標號及/或字母。此重複是出於簡化及清楚的目的，且本身並不指示所論述的各種實施例及/或配置之間的關係。
另外，為易於描述，本文中可使用例如「在...之下」、「在...下方」、「下部」、「在...上方」、「上部」以及其類似者的空間相對術語來描述如圖式中所示出的一個裝置或特徵相對於另一裝置或特徵的關係。除圖式中描繪的定向之外，空間相對術語亦意欲涵蓋裝置在使用或操作中的不同定向。裝置可以其他方式定向（旋轉90度或處於其他定向）且本文中所使用的空間相對描述詞可同樣相應地進行解釋。
儘管下文詳細地描述實施例，但本文中提供本揭露內容的通用描述。在一般意義上，本文中所描述的實施例提供一種封裝，其中藉由在電力模組（有時稱作插座（socket））與積體扇出型（integrated fan-out；InFO）結構之間堆疊積體被動裝置（integrated passive device；IPD）封裝而將IPD封裝並整合至系統晶圓（SoW）封裝（例如，超大扇出型晶圓級封裝）中。實施例的SoW封裝可包含10,000平方毫米（mm2 ）或大於10,000平方毫米的封裝面積中的互連功能晶粒的任何組合。舉例而言，SoW封裝內的互連功能晶粒可提供完整電氣系統的每一組件，以在資料中心應用、伺服器應用或類似者中提供高性能計算（high performance computing；HPC）（例如人工智慧（artificial intelligence；AI）伺服器的加速器、雲計算系統、邊緣計算系統或類似者）。電力模組可經由IPD封裝連接到SoW封裝的功能晶粒。每一電力模組可為SoW封裝內的單一功能晶粒或多個功能晶粒提供電力管理。
本文中所描述的實施例中的一些或全部的有利特徵可包含IPD與功能晶粒之間的較短距離，其可增強電力分佈網路（power distribution network；PDN）性能。一些實施例可提供3D堆疊IPD與InFO製程的整合，從而使實施例的採用變得實用。在一些實施例中，IPD的3D堆疊避免了自插座位置（socket landscape）（例如，封裝的佔據位置）移除球柵陣列封裝（ball grid array；BGA）連接件的需求，從而允許藉由增大用於電流處理的面積（例如，更多BGA連接件）來提高電流處理。
圖1至圖16C示出根據一些實施例的用於形成第一封裝組件100（圖式中示出的第一封裝組件100A、第一封裝組件100B以及第一封裝組件100C統稱為第一封裝組件100）的製程期間的中間步驟的截面圖。第一封裝組件100為包括一或多個IPD的IPD封裝，其可根據各種實施例實施於模組（例如圖17A至圖17C中示出的模組160）與SoW封裝（例如圖24中示出的SoW封裝400）之間。圖1示出第一封裝區101A及第二封裝區101B，例如下文參考圖4所論述的IPD 50A的一或多個IPD可被封裝於其中。
在圖1中，提供載板基底102，並在載板基底102上形成釋放層（release layer）104。載板基底102可為玻璃載板基底、陶瓷載板基底或類似者。載板基底102可為晶圓，以使得多個封裝可在載板基底102上同時形成。
釋放層104可由聚合物類材料形成，可將所述聚合物類材料連同載板基底102一起自將在後續步驟中形成的上覆結構移除。在一些實施例中，釋放層104為在加熱時失去其黏著性的環氧類熱釋放材料，例如光-熱轉換（light-to-heat-conversion；LTHC）釋放塗層。在其他實施例中，釋放層104可為在暴露於UV光時失去其黏著性的紫外線（ultra-violet；UV）黏膠。釋放層104可以液體點膠並被固化，可為層壓至載板基底102上的層壓膜，或可為類似物。釋放層104的頂部表面可經水平化，且可具有高平坦度。
圖2中，可在釋放層104上形成背側重佈線結構106。在所繪示的實施例中，背側重佈線結構106包含介電層108、金屬化圖案110（有時稱作重佈線層或重佈線）以及介電層112。背側重佈線結構106為可選用的（optional）。在一些實施例中，不含金屬化圖案的介電層代替背側重佈線結構106形成於釋放層104上。
介電層108可形成於釋放層104上。介電層108的底部表面可與釋放層104的頂部表面接觸。在一些實施例中，介電層108例如由以下的聚合物形成：聚苯并噁唑（polybenzoxazole；PBO）、聚醯亞胺、苯并環丁烯（benzocyclobutene；BCB）或類似者。在其他實施例中，介電層108由以下材料形成：氮化物，例如氮化矽；氧化物，例如氧化矽、磷矽酸鹽玻璃（phosphosilicate glass；PSG）、硼矽酸鹽玻璃（borosilicate glass；BSG）、硼摻雜磷矽酸鹽玻璃（boron-doped phosphosilicate glass；BPSG）或類似者；或類似者。介電層108可藉由任何可接受的沈積製程形成，例如旋轉塗佈、化學氣相沈積（chemical vapor deposition；CVD）、疊層（laminating）、類似者或其組合。
金屬化圖案110可形成於介電層108上。舉例而言，金屬化圖案110可藉由以下製程來形成：首先在介電層108上方形成晶種層。在一些實施例中，晶種層為金屬層，其可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層及位於鈦層上方的銅層。可使用例如物理氣相沈積（physical vapor deposition；PVD）或類似者來形成晶種層。隨後在晶種層上形成光阻並將所述光阻圖案化。光阻可藉由旋轉塗佈或類似方法來形成，且可暴露於光以用於圖案化。光阻的圖案對應於金屬化圖案110。圖案化形成穿過光阻的開口以暴露晶種層。在光阻的開口中及晶種層的暴露部分上形成導電材料。導電材料可藉由鍍覆形成，所述鍍覆例如是電鍍或無電鍍覆或類似者。導電材料可包括金屬，例如銅、鈦、鎢、鋁或類似者。隨後，將光阻及晶種層的其上未形成導電材料的部分移除。可藉由可接受的灰化或剝離製程（例如，使用氧電漿或類似者的製程）來移除光阻。一旦移除光阻，就使用例如濕式蝕刻或乾式蝕刻等可接受的蝕刻製程來移除晶種層的暴露部分。晶種層的剩餘部分及導電材料的剩餘部分形成金屬化圖案110。
介電層112可形成於金屬化圖案110及介電層108上。在一些實施例中，介電層112由聚合物形成，所述聚合物可為可使用微影罩幕圖案化的感光性材料，例如PBO、聚醯亞胺、BCB或類似者。在其他實施例中，介電層112由以下材料形成：氮化物，例如氮化矽；氧化物，例如氧化矽、PSG、BSG、BPSG；或類似者。介電層112可藉由旋轉塗佈、疊層、CVD、類似者或其組合形成。介電層112可經圖案化以形成開口114，開口114暴露出金屬化圖案110的部分。圖案化可藉由可接受的製程執行，例如當介電層112為感光性材料時藉由使介電層112暴露於光或藉由使用例如非等向性蝕刻來蝕刻。在介電層112為感光性材料的實施例中，介電層112可在暴露於光之後顯影。
應瞭解，背側重佈線結構106可包含任何數目的介電層及金屬化圖案。若要形成更多介電層及金屬化圖案，則可重複上文所論述的步驟及製程。金屬化圖案可包含導電線及導通孔。導通孔可在金屬化圖案的形成期間藉由在下伏介電層的開口中形成金屬化圖案的晶種層及導電材料來形成。導通孔可互連且電耦接金屬化圖案的各種導電線。
在圖3中，在開口114中形成穿孔116，且穿孔116在背側重佈線結構106的最頂部介電層（例如圖3所示實施例中的介電層112）之上延伸。作為一個實例，穿孔116可藉由以下製程來形成：首先在背側重佈線結構106上方（例如在介電層112及金屬化圖案110的被開口114暴露的部分上）形成晶種層。在一些實施例中，晶種層為金屬層，其可為單層或包括由不同材料形成的多個子層的複合層。在特定實施例中，晶種層包括鈦層及位於鈦層上方的銅層。可使用例如PVD或類似者來形成晶種層。在晶種層上形成光阻並將所述光阻圖案化。光阻可藉由旋轉塗佈或類似方法來形成，且可暴露於光以用於圖案化。光阻的圖案對應於穿孔116。圖案化形成穿過光阻的開口以暴露晶種層。在光阻的開口中及晶種層的暴露部分上形成導電材料。導電材料可藉由鍍覆形成，所述鍍覆例如是電鍍或無電鍍覆或類似者。導電材料可包括金屬，例如銅、鈦、鎢、鋁或類似者。將光阻及晶種層的其上未形成導電材料的部分移除。可藉由可接受的灰化或剝離製程（例如使用氧電漿或類似者的製程）來移除光阻。一旦光阻被移除，就使用例如濕式蝕刻或乾式蝕刻等可接受的蝕刻製程來移除晶種層的暴露部分。晶種層及導電材料的剩餘部分形成穿孔116。
在圖4中，包含IPD 50A、離散被動裝置50B以及主動裝置晶粒50C的晶粒50（圖式中示出的IPD 50A、離散被動裝置50B以及主動裝置晶粒50C統稱為晶粒50）藉由黏著劑118黏附至介電層112。將所需類型及量的晶粒50黏附於第一封裝區101A及第二封裝區101B中的每一者中。在各種實施例中，例如IPD 50A及離散被動裝置50B的被動裝置可在第一封裝區101A及第二封裝區101B中的每一者中佔據大於百分之50的面積。在所示出的實施例中，多個晶粒50彼此相鄰黏附。IPD 50A及主動裝置晶粒50C各自在下文中分別相對於圖5A及圖5B更詳細地描述。
離散被動裝置50B可包含例如一或多個離散電容器、電感器、其組合或類似者。當多個離散被動裝置50B設置於第一封裝區101A及第二封裝區101B中的每一者中時，離散被動裝置50B可以堆疊配置（如所示出）接合在一起，或直接在背側重佈線結構106上並排地設置。如圖4中所示出，離散被動裝置50B中的每一者可包含半導體基底52B、延伸穿過半導體基底52B的穿孔53B、設置於半導體基底52B及穿孔53B上方的接墊62B、設置在半導體基底52B及接墊62B上的鈍化層64B以及延伸穿過鈍化層64B的晶粒連接件66B。離散被動裝置50B及主動裝置晶粒50C為可選用的，且在一些實施例中，可自第一封裝區101A及/或第二封裝區101B省略離散被動裝置50B及/或主動裝置晶粒50C。
IPD 50A、離散被動裝置50B以及主動裝置晶粒50C可具有不同尺寸（例如不同高度及/或表面面積），或可具有相同尺寸（例如相同高度及/或表面面積）。在第一封裝區101A及第二封裝區101B中可供用於穿孔116的空間可能受限，尤其在IPD 50A、離散被動裝置50B以及主動裝置晶粒50C包含具有大佔據面積的裝置（例如系統晶片（SoC））時。當第一封裝區101A及第二封裝區101B具有可用於穿孔116的有限空間時，使用背側重佈線結構106可以改善內連線配置。
黏著劑118位於IPD 50A、離散被動裝置50B以及主動裝置晶粒50C的背側上，並將IPD 50A、離散被動裝置50B以及主動裝置晶粒50C黏附至背側重佈線結構106，例如黏附至介電層112。黏著劑118可為任何合適的黏著劑、環氧樹脂、晶粒附接膜（die attach film；DAF）或類似者。黏著劑118可被施加至IPD 50A、離散被動裝置50B以及主動裝置晶粒50C的背側，或可施加於載板基底102上的介電層112的表面上。舉例而言，黏著劑118可在單體化以分隔開IPD 50A、離散被動裝置50B以及主動裝置晶粒50C之前施加至IPD 50A、離散被動裝置50B以及主動裝置晶粒50C的背側。
圖5A示出根據一些實施例的IPD 50A。IPD 50A可包含各種各樣的被動裝置，例如平衡-非平衡轉換器（balun）、耦合器、分離器（splitter）、過濾器、雙工器（diplexer）、電感器、電容器、電阻器或類似者。在一些實施例中，IPD 50A可為多層陶瓷電容器（multi-layer ceramic capacitor；MLCC）、線圈電感器、薄膜電阻器或類似者。根據一些實施例，IPD 50A中不存在例如電晶體或二極體的主動裝置。
IPD 50A可形成於晶圓中，所述晶圓可包含在後續步驟中經單體化以形成多個IPD 50A的不同裝置區。IPD 50A可根據適用的製造製程經處理以形成積體電路。舉例而言，IPD 50A可包含半導體基底52A，例如摻雜矽或未摻雜矽，或絕緣層上半導體（semiconductor-on-insulator；SOI）基底的主動層。半導體基底52A可包含其他半導體材料，例如鍺；化合物半導體，包含碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦；合金半導體，包含SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP；或其組合。亦可使用其他基底，例如多層基底或梯度基底。半導體基底52A具有有時稱作前側的主動表面（例如圖5A中面向上的表面）及有時稱作背側的非主動表面（例如圖5A中面向下的表面）。
層間介電（inter-layer dielectric；ILD）56A形成在半導體基底52A的前側上方。ILD 56A可包含由以下材料形成的一或多個介電層：例如磷矽酸鹽玻璃（PSG）、硼矽酸鹽玻璃（BSG）、硼摻雜磷矽酸鹽玻璃（BPSG）、未摻雜矽酸鹽玻璃（undoped silicate glass；USG）或類似者。
在ILD 56A上方包括內連線結構60A。內連線結構60A可用以互連IPD 50A中包含的各種被動裝置。內連線結構60A可進一步定義IPD 50A中所包含的各種被動裝置。舉例而言，內連線結構60A的區域70A可定義電阻器，內連線結構60A的區域70B可定義電容器，且內連線結構60A的區域70C可定義電感器。然而，區域70A、區域70B以及區域70C中的每一者可定義IPD 50A的任何被動裝置。
內連線結構60A可例如由ILD 56A上的介電層中的金屬化圖案形成。金屬化圖案包含形成於一或多個低介電常數（低k）介電層中的金屬線及通孔。內連線結構60A的金屬化圖案電耦合至IPD 50A的被動裝置。
IPD 50A更包括接墊62，例如鋁接墊，所述接墊用以進行外部連接。接墊62A位於IPD 50A的前側上，例如在內連線結構60A中及/或在所述內連線結構60A上。一或多個鈍化膜64A位於IPD 50A上，例如位於內連線結構60A及接墊62A的部分上。開口穿過鈍化膜64A延伸至接墊62A。晶粒連接件66A，例如導電柱（例如由例如銅的金屬形成），延伸穿過鈍化膜64A中的開口，且物理及電性耦接至各個接墊62A。晶粒連接件66A可藉由例如鍍覆或類似方法形成。晶粒連接件66A將IPD 50A的各個被動裝置電耦接至外部裝置。
可選的，可在接墊62A上設置焊料區（例如焊料球或焊料凸塊）。焊料球可用於對IPD 50A執行晶片探針（chip probe；CP）測試。可對IPD 50A執行CP測試以確定IPD 50A是否為已知良好晶粒（known good die；KGD）。因此，僅封裝經歷後續處理的為KGD的IPD 50A，且不封裝未通過CP測試的晶粒。在測試之後，可在後續處理步驟中移除焊料區。
在IPD 50A的前側上（例如在鈍化膜64A及晶粒連接件66A上）可包含介電層68A。介電層68A橫向包封晶粒連接件66A，且介電層68A與IPD 50A橫向共端（coterminous）。最初，介電層68A可掩埋晶粒連接件66A，使得介電層68A的最頂表面在晶粒連接件66A的最頂表面之上。在焊料區設置在晶粒連接件66A上的一些實施例中，介電層68A亦可掩埋焊料區。替代地，可在形成介電層68A之前移除焊料區。
介電層68A可為聚合物，例如PBO、聚醯亞胺、BCB或類似者；氮化物，例如氮化矽或類似者；氧化物，例如氧化矽、PSG、BSG、BPSG或類似者；類似物，或其組合。介電層68A可例如藉由旋轉塗佈、疊層、化學氣相沈積（CVD）或類似者形成。在一些實施例中，晶粒連接件66A在IPD 50A的形成期間被介電層68A暴露出來。在一些實施例中，晶粒連接件66A保持掩埋且在用於封裝IPD 50A的後續製程期間暴露。暴露晶粒連接件66A可移除可能存在於晶粒連接件66A上的任何焊料區。
在一些實施例中，IPD 50A可為包含多個半導體基底52A的堆疊裝置。在此類實施例中，IPD 50A包含由基底穿孔（through-substrate vias；TSV）互連的多個半導體基底52A。半導體基底52A中的每一者可具有內連線結構60A。
圖5B示出根據一些實施例的主動裝置晶粒50C。主動裝置晶粒50C將在後續處理中經封裝以形成積體電路封裝。主動裝置晶粒50C可為：邏輯晶粒（例如中央處理單元（central processing unit；CPU）、圖形處理單元（graphics processing unit；GPU）、系統晶片（system-on-a-chip；SoC）、應用程式處理器（application processor；AP）、微控制器或類似者）；記憶體晶粒（例如動態隨機存取記憶體（dynamic random access memory；DRAM）晶粒、靜態隨機存取記憶體（static random access memory；SRAM）晶粒、高頻寬記憶體（high bandwidth memory；HBM）晶粒或類似者）；輸入/輸出（input/output；I/O）介面晶粒；電力管理晶粒（例如電力管理積體電路（power management integrated circuit；PMIC）晶粒或類似者）；射頻（radio frequency；RF）晶粒；感測器晶粒；微機電系統（micro-electro-mechanical-system；MEMS）晶粒；訊號處理晶粒（例如數位訊號處理（digital signal processing；DSP）晶粒或類似者）；前端晶粒（例如類比前端（analog front-end；AFE）晶粒或類似者）；類似者或其組合。
主動裝置晶粒50C可形成於晶圓中，所述晶圓可包含在後續步驟中經單體化以形成多個主動裝置晶粒的不同裝置區。主動裝置晶粒50C可根據適用的製造製程經處理以形成積體電路。舉例而言，主動裝置晶粒50C包含半導體基底52C，例如摻雜矽或未摻雜矽，或絕緣層上半導體（SOI）基底的主動層。半導體基底52C可包含其他半導體材料，例如鍺；化合物半導體，包含碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦；合金半導體，包含SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP；或其組合。亦可使用其他基底，例如多層基底或梯度基底。半導體基底52C具有有時稱作前側的主動表面（例如圖5B中面向上的表面）及有時稱作背側的非主動表面（例如圖5B中面向下的表面）。
裝置54可形成於半導體基底52C的前側處。裝置54可為主動裝置（例如電晶體、二極體或類似者）、電容器、電阻器或類似者。層間介電（ILD）56C形成在半導體基底52C的前側上方。ILD 56C包圍且可覆蓋裝置54。ILD 56C可包含由例如以下材料所形成的一或多個介電層：磷矽酸鹽玻璃（PSG）、硼矽酸鹽玻璃（BSG）、硼摻雜磷矽酸鹽玻璃（BPSG）、未摻雜矽酸鹽玻璃（USG）或類似者。
導電插塞58延伸穿過ILD 56C以電耦接及實體耦接裝置54。舉例而言，當裝置54為電晶體時，導電插塞58可耦接電晶體的閘極及源極/汲極區。導電插塞58可由鎢、鈷、鎳、銅、銀、金、鋁、類似者或其組合形成。在ILD 56C及導電插塞58上方包括內連線結構60C。內連線結構60C將裝置54互連以形成積體電路。內連線結構60C可由例如ILD 56C上的介電層中的金屬化圖案形成。金屬化圖案包含形成於一或多個低k介電層中的金屬線及通孔。內連線結構60C的金屬化圖案藉由導電插塞58電耦接至裝置54。
主動裝置晶粒50C更包含接墊62C，例如鋁接墊，所述接墊用以進行外部連接。接墊62C位於主動裝置晶粒50C的主動側上，例如在內連線結構60C中及/或在所述內連線結構60C上。一或多個鈍化膜64C位於主動裝置晶粒50C上，例如在內連線結構60C及接墊62C的部分上。開口穿過鈍化膜64C延伸至接墊62C。晶粒連接件66C，例如導電柱（例如由例如銅的金屬形成）延伸穿過鈍化膜64C中的開口，且實體及電性耦接至各個接墊62C。晶粒連接件66C可藉由例如鍍覆或類似方法形成。晶粒連接件66C電耦接主動裝置晶粒50C的各個積體電路。
可選的，可在接墊62C上設置焊料區（例如焊料球或焊料凸塊）。焊料球可用於對主動裝置晶粒50C執行晶片探針（CP）測試。可對主動裝置晶粒50C執行CP測試以確定主動裝置晶粒50C是否為已知良好晶粒（KGD）。因此，僅封裝經歷後續處理的為KGD的主動裝置晶粒50C，且不封裝未通過CP測試的晶粒。在測試之後，可在後續處理步驟中移除焊料區。
介電層68C可位於主動裝置晶粒50C的前側上，例如位於鈍化膜64C及晶粒連接件66C上。介電層68C橫向包封晶粒連接件66C，且介電層68C與主動裝置晶粒50C橫向共端。最初，介電層68C可掩埋晶粒連接件66C，使得介電層68C的最頂表面在晶粒連接件66C的最頂表面之上。在焊料區設置在晶粒連接件66C上的一些實施例中，介電層68C亦可掩埋焊料區。替代地，可在形成介電層68C之前移除焊料區。
介電層68C可為聚合物，例如PBO、聚醯亞胺、BCB或類似者；氮化物，例如氮化矽或類似者；氧化物，例如氧化矽、PSG、BSG、BPSG或類似者；類似物，或其組合。介電層68C可例如藉由旋轉塗佈、疊層、CVD或類似者形成。在一些實施例中，晶粒連接件66C在主動裝置晶粒50C的形成期間被介電層68C暴露出來。在一些實施例中，晶粒連接件66C保持掩埋且在用於封裝主動裝置晶粒50C的後續製程期間暴露出來。暴露晶粒連接件66C可移除可能存在於晶粒連接件66C上的任何焊料區。
在一些實施例中，主動裝置晶粒50C為包含多個半導體基底52C的堆疊裝置。舉例而言，主動裝置晶粒50C可為記憶體裝置，例如混合記憶體立方體（hybrid memory cube；HMC）模組、高頻寬記憶體（HBM）模組或包含多個記憶體晶粒的類似者。在此類實施例中，主動裝置晶粒50C包含由基底穿孔（TSV）互連的多個半導體基底52C。半導體基底52C中的每一者可具有內連線結構60C。
在圖6中，在晶粒50及穿孔116上且圍繞所述晶粒50及所述穿孔116形成包封體120。在形成之後，包封體120包封穿孔116、IPD 50A、離散被動裝置50B以及主動裝置晶粒50C。包封體120可為模製化合物、環氧樹脂或類似者。包封體120可藉由壓縮模製、轉移模製或類似製程來施加，且可形成在載板基底102上方使得穿孔116及/或IPD 50A、離散被動裝置50B以及主動裝置晶粒50C被掩埋或覆蓋。包封體120進一步形成於IPD 50A、離散被動裝置50B與主動裝置晶粒50C之間的間隙區中。包封體120可以液體或半液體形式施加且接著被固化。
在圖7中，對包封體120執行平坦化製程以暴露出穿孔116及晶粒連接件66A、晶粒連接件66B以及晶粒連接件66C。平坦化製程亦可移除穿孔116、介電層68A及介電層68C及/或晶粒連接件66A、晶粒連接件66B以及晶粒連接件66C的材料，直至晶粒連接件66A、晶粒連接件66B以及晶粒連接件66C及穿孔116暴露出來。在平坦化製程之後，穿孔116、晶粒連接件66A、晶粒連接件66B以及晶粒連接件66C、介電層68A及介電層68C以及包封體120的頂部表面可彼此齊平（例如共面）。平坦化製程可為例如化學機械拋光（chemical-mechanical polish；CMP）製程、研磨製程、回蝕製程或類似者。在一些實施例中，例如如果穿孔116及/或晶粒連接件66A、晶粒連接件66B以及晶粒連接件66C已暴露，則可省略平坦化製程。
在圖8至圖11中，在包封體120、穿孔116、IPD 50A、離散被動裝置50B以及主動裝置晶粒50C上方形成前側重佈線結構122（參看圖11）。前側重佈線結構122包含介電層124、介電層128、介電層132以及介電層136；以及金屬化圖案126、金屬化圖案130以及金屬化圖案134。金屬化圖案亦可稱作重佈線層或重佈線。圖11中示出的前側重佈線結構122包含三層金屬化圖案層及四層介電層；然而，前側重佈線結構122中可包含更多或更少的金屬化圖案及介電層。若要形成更少介電層及金屬化圖案，則可省略下文所論述的步驟及製程。若要形成更多介電層及金屬化圖案，則可重複下文所論述的步驟及製程。
在圖8中，將介電層124沈積於包封體120、穿孔116以及晶粒連接件66A、晶粒連接件66B以及晶粒連接件66C上。在一些實施例中，介電層124由例如PBO、聚醯亞胺、BCB或類似者的感光性材料形成，所述感光性材料可使用微影罩幕來圖案化。介電層124可藉由旋轉塗佈、疊層、CVD、類似者或其組合形成。介電層124隨後被圖案化。圖案化形成開口以暴露出穿孔116及晶粒連接件66A、晶粒連接件66B以及晶粒連接件66C的部分。圖案化可藉由適合的製程來進行，例如當介電層124為感光性材料時藉由將介電層124暴露於光或藉由使用例如非等向性蝕刻來蝕刻。若介電層124為感光性材料，則介電層124可在曝光之後顯影。
隨後形成金屬化圖案126。金屬化圖案126包含在介電層124的主表面上且沿所述主表面延伸的線路部分（亦稱作導電線）。金屬化圖案126更包含通孔部分（亦稱作導通孔），所述通孔部分延伸穿過介電層124以實體耦接且電耦接穿孔116及IPD 50A、離散被動裝置50B以及主動裝置晶粒50C。作為一個實例，金屬化圖案126可藉由以下製程來形成：首先在介電層124上方且在延伸穿過介電層124的開口中形成晶種層。在一些實施例中，晶種層為金屬層，其可為單層或包括由不同材料所形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層及在鈦層上方的銅層。可使用例如PVD或類似者來形成晶種層。隨後在晶種層上形成光阻並將所述光阻圖案化。光阻可藉由旋轉塗佈或類似方法來形成，且可暴露於光以用於圖案化。光阻的圖案對應於金屬化圖案126。圖案化形成穿過光阻的開口以暴露晶種層。隨後在光阻的開口中及晶種層的暴露部分上形成導電材料。導電材料可藉由鍍覆形成，所述鍍覆例如是電鍍或無電鍍覆或類似者。導電材料可包括金屬，比如銅、鈦、鎢、鋁或類似者。導電材料與其下方的部分晶種層組合形成金屬化圖案126。將光阻及晶種層的其上未形成導電材料的部分移除。可藉由可接受的灰化或剝離製程（例如使用氧電漿或類似者）來移除光阻。一旦光阻被移除，就使用例如濕式蝕刻或乾式蝕刻等可接受的蝕刻製程來移除晶種層的暴露部分。
在圖9中，在金屬化圖案126及介電層124上沈積介電層128。介電層128可以類似於介電層124的方式形成，且可由與介電層124的材料類似的材料形成。
隨後形成金屬化圖案130。金屬化圖案130包含在介電層128的主表面上且沿所述主表面延伸的線路部分。金屬化圖案130更包含延伸穿過介電層128以實體耦接且電耦接金屬化圖案126的通孔部分。金屬化圖案130可以類似於金屬化圖案126的方式形成，且可由與金屬化圖案126的材料類似的材料形成。在一些實施例中，金屬化圖案130具有與金屬化圖案126不同的尺寸。舉例而言，金屬化圖案130的導電線及/或通孔可比金屬化圖案126的導電線及/或通孔更寬或更厚。此外，金屬化圖案130可以比金屬化圖案126更大的間距形成。
在圖10中，在金屬化圖案130及介電層128上沈積介電層132。介電層132可以類似於介電層124的方式形成，且可由與介電層124的材料類似的材料形成。
隨後形成金屬化圖案134。金屬化圖案134包含在介電層132的主表面上且沿所述主表面延伸的線路部分。金屬化圖案134更包含延伸穿過介電層132以實體耦接且電耦接金屬化圖案130的通孔部分。金屬化圖案134可以類似於金屬化圖案126的方式形成，且可由與金屬化圖案126的材料類似的材料形成。金屬化圖案134為前側重佈線結構122的最頂部金屬化圖案。因而，前側重佈線結構122的所有中間金屬化圖案（例如金屬化圖案126及金屬化圖案130）設置於金屬化圖案134與IPD 50A、離散被動裝置50B以及主動裝置晶粒50C之間。在一些實施例中，金屬化圖案134具有與金屬化圖案126及金屬化圖案130不同的尺寸。舉例而言，金屬化圖案134的導電線及/或通孔可比金屬化圖案126及金屬化圖案130的導電線及/或通孔更寬或更厚。此外，金屬化圖案134可以比金屬化圖案130更大的間距形成。
在圖11中，在金屬化圖案134及介電層132上沈積介電層136。介電層136可以類似於介電層124的方式形成，且可由與介電層124的材料類似的材料形成。介電層136為前側重佈線結構122的最頂部介電層。因而，前側重佈線結構122的所有金屬化圖案（例如金屬化圖案126、金屬化圖案130以及金屬化圖案134）設置於介電層136與IPD 50A、離散被動裝置50B以及主動裝置晶粒50C之間。此外，前側重佈線結構122的所有中間介電層（例如介電層124、介電層128、介電層132）設置於介電層136與IPD 50A、離散被動裝置50B以及主動裝置晶粒50C之間。
在圖12中，形成凸塊下金屬（UBM）138以用於至前側重佈線結構122的外部連接。UBM 138具有在介電層136的主表面上且沿所述主表面延伸的凸塊部分，且具有延伸穿過介電層136以實體耦接且電耦接至金屬化圖案134的通孔部分。因此，UBM 138電耦接至穿孔116及IPD 50A、離散被動裝置50B以及主動裝置晶粒50C。UBM 138可由與金屬化圖案126相同的材料形成。在一些實施例中，UBM 138可具有與金屬化圖案126、金屬化圖案130以及金屬化圖案134不同的尺寸。
在圖13中，在UBM 138上形成導電連接件150。導電連接件150可為球柵陣列封裝（BGA）連接件、焊料球、金屬柱、受控塌陷晶粒連接（controlled collapse chip connection；C4）凸塊、微凸塊、化學鍍鎳鈀浸金（electroless nickel-electroless palladium-immersion gold technique；ENEPIG）形成的凸塊，或類似者。導電連接件150可包含導電材料，例如焊料、銅、鋁、金、鎳、銀、鈀、錫、類似者或其組合。在一些實施例中，導電連接件150藉由以下製程來形成：首先藉由蒸鍍、電鍍、列印、焊料轉移、植球或類似方法形成焊料層。一旦焊料層已形成於結構上，就可執行回焊以便將材料塑形成所需凸塊形狀。在另一實施例中，導電連接件150包括藉由濺鍍、列印、電鍍、無電鍍覆、CVD或類似者形成的金屬柱（例如銅柱）。金屬柱可不包括焊料且具有實質上豎直的側壁。在一些實施例中，在金屬柱的頂部上形成金屬頂蓋層。金屬頂蓋層可包含鎳、錫、錫鉛、金、銀、鈀、銦、鎳鈀金、鎳金、類似者或其組合，且可由鍍覆製程形成。
在圖14中，將圖13的結構翻轉並放置於膠帶149上，且將載板基底102自背側重佈線結構106（例如介電層108）分離。根據一些實施例，所述分離包含將光（例如雷射光或UV光）投射於釋放層104上，以使得釋放層104在光熱下分解並使得可移除載板基底102。所述結構隨後被翻轉並放置於膠帶149上。
另外，在圖14中，前側重佈線結構122可被預切割。切割裝置可部分地切割至第一封裝區101A與第二封裝區101B之間的切割道區域中的前側重佈線結構122中，以在前側重佈線結構122中形成凹槽（未單獨地示出）。在一些實施例中，用於預切割製程的切割裝置為雷射。預切割製程可防止後續單體化製程（參見例如圖16A至圖16C）期間前側重佈線結構122與其各層分層。
在圖15中，形成穿過介電層108的開口151，以暴露出金屬化圖案110的一些部分。開口151可例如使用雷射鑽孔、蝕刻或類似者來形成。
在圖16A至圖16C中，在開口151中形成各種外部連接件，以在第一封裝區域101A及第二封裝區101B中形成第一封裝組件100A。在圖16A中，在開口151中形成導電連接件152於金屬化圖案110上，從而在第一封裝區101A及第二封裝區101B中形成第一封裝組件100A。導電連接件152可為球柵陣列封裝（BGA）連接件、焊料球、金屬柱、受控塌陷晶粒連接（C4）凸塊、微凸塊、化學鍍鎳鈀浸金（ENEPIG）形成的凸塊，或類似者。導電連接件152可包含導電材料，例如焊料、銅、鋁、金、鎳、銀、鈀、錫、類似者或其組合。在一些實施例中，導電連接件152藉由以下製程來形成：首先藉由例如蒸鍍、電鍍、列印、焊料轉移、植球或其類似者等此類常用方法形成焊料層。一旦焊料層已形成於所述結構上，就可執行回焊以便將材料塑形成所需凸塊形狀。
在圖16B中，在開口151中形成接墊154於金屬化圖案110上，從而在第一封裝區101A及第二封裝區101B中形成第一封裝組件100B。接墊154用於耦接至導電連接件156，且可稱作凸塊下金屬（under bump metallurgies；UBM）154。在所示出的實施例中，接墊154形成於開口151中，且穿過介電層108至金屬化圖案110。
舉例而言，接墊154可藉由以下製程來形成：首先在介電層108上方及在延伸穿過介電層108的開口151中形成晶種層。在一些實施例中，晶種層為金屬層，其可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層及位於鈦層上方的銅層。可使用例如PVD或類似者來形成晶種層。隨後在晶種層上形成光阻並將所述光阻圖案化。光阻可藉由旋轉塗佈或類似方法來形成，且可暴露於光以用於圖案化。光阻的圖案對應於接墊154。圖案化形成穿過光阻的開口以暴露晶種層。隨後在光阻的開口中及晶種層的暴露部分上形成導電材料。導電材料可藉由鍍覆形成，所述鍍覆例如是電鍍或無電鍍覆或類似者。導電材料可包括金屬，比如銅、鈦、鎢、鋁或類似者。在一些實施例中，所述接墊154可包括合金，例如化學鍍鎳鈀浸金（electroless nickel, electroless palladium, immersion gold；ENEPIG）、化學鍍鎳浸金（electroless nickel-immersion gold；ENIG）或類似者。導電材料與其下方的部分晶種層組合形成接墊154。光阻及晶種層的其上未形成導電材料的部分被移除。可藉由可接受的灰化或剝離製程（例如使用氧電漿或類似者）來移除光阻。一旦光阻被移除，就使用例如濕式蝕刻或乾式蝕刻的可接受的蝕刻製程來移除晶種層的暴露部分。
接下來，在接墊154上方形成導電連接件156。導電連接件156可以類似於導電連接件152的方式形成，且可由與導電連接件152的材料類似的材料形成。
圖16C示出形成接墊154而沒有在接墊154上方形成導電連接件的實施例，從而在第一封裝區101A及第二封裝區101B中形成第一封裝組件100C。接墊154可以與參考圖16B所論述的材料及方式類似的材料及方式形成。
在圖17A至圖17C中，將模組160（圖式中示出的模組160A、模組160B及模組160C統稱為模組160）接合至背側重佈線結構106。模組160可為電力供應模組、記憶體模組、電壓調節器模組、積體被動裝置（IPD）模組或類似者。在一些實施例中，模組160可包含覆晶接合、引線接合或類似者。模組160可為晶片級封裝（chip-scale package；CSP）、多晶片模組（multi-chip module；MCM）或類似者。模組160可為根據一些實施例的包含離散積體電路及被動裝置的封裝電路板（packaged circuit board；PCB）模組。
圖17A示出接合至圖16A中所示的第一封裝組件100A的模組160A。如圖17A中所示出，模組160A可包含接墊162，導電連接件158形成在所述接墊162上。接墊162可以類似於接墊154的方式形成，且可由與接墊154的材料類似的材料形成。導電連接件158可以類似於導電連接件152的方式形成，且可由與導電連接件152的材料類似的材料形成。可使用取放機器或類似者來將模組160A放置於第一封裝區101A及第二封裝區101B中。一旦放置模組160A，就可回焊導電連接件152及導電連接件158，以將模組160A接合至背側重佈線結構106。
可形成底部填充物164以填充模組160A與背側重佈線結構106之間的間隙。底部填充物164可在附接模組160A之後藉由毛細流動製程形成，或可在附接模組160A之前藉由合適的沈積方法形成。
圖17B示出接合至圖16B中所示的第一封裝組件100B的模組160A。接墊162可以類似於接墊154的方式形成，且可由與接墊154的材料類似的材料形成。可使用取放機器或類似者來將模組160A放置於第一封裝區101A及第二封裝區101B中。一旦放置模組160A，就可回焊導電連接件152以將模組160A接合至背側重佈線結構106。
可形成底部填充物164以填充模組160A與背側重佈線結構106之間的間隙。底部填充物164可在附接模組160A之後藉由毛細流動製程形成，或可在附接模組160A之前藉由合適的沈積方法來形成。
圖17C示出電耦接至圖16C中所示的第一封裝組件100C的模組160B。如圖17C中所示出，模組160B可包含彈簧式接觸件166。可使用取放機器或類似者來將模組160B放置在第一封裝組件100C上方，使得彈簧式接觸件166設置在接墊154上。可隨後使用固定件將模組160B附接至第一封裝組件100B，所述固定件例如下文關於圖30及圖32所論述的固定件450。彈簧式接觸件166可由例如以下的材料形成：銅、銅合金、鍍鈹銅（例如鍍鎳（Ni）電且隨後鍍金（Au）的鈹銅（beryllium copper；BeCu））、其組合或類似者。彈簧式接觸件166可藉由冷成型製程（cold forming process）或類似者形成。包含彈簧式接觸件166允許在不需要接合或結合製程的情況下將模組160B機械地固定至第一封裝組件100C，且允許模組160B易於替換。如圖17C中所示出，在彈簧式接觸件166用於將模組160B附接至背側重佈線結構106的實施例中，模組160B與背側重佈線結構106之間可不包含底部填充物材料。
在圖18A至圖18E中，將第一封裝區101A及第二封裝區101B中的第一封裝組件100單體化，並將第一封裝組件100中的每一者（具有附接模組160或不具有附接模組160）放置於托盤170中。可使用分割製程來將第一封裝組件100單體化，所述分割製程例如是鋸割、雷射鑽孔或類似者。如圖18A至圖18E中所示，第一封裝組件100包含前側重佈線結構122、被包封的晶粒50、背側重佈線結構106以及導電連接件152、接墊154以及導電連接件156中的任一者。第一封裝200（圖式中示出的第一封裝200A、第一封裝200B、第一封裝200C及第一封裝200D統稱為第一封裝200）包含接合至第一封裝組件100的模組160。在第一封裝組件100被單體化之後，第一封裝200中的每一者自膠帶149移除且放置於托盤170中。托盤170可用以為第一封裝200提供保護直至在後續3D封裝製程（例如用以將第一封裝200附接至圖25中所示的SoW封裝400的製程）期間放置第一封裝200為止。將第一封裝200放置在托盤170中可改善藉由當前申請的方法所生產的封裝的可靠性及良率。
圖18A示出包含接合至第一封裝組件100A的模組160A的第一封裝200A。模組160A藉由導電連接件152與導電連接件158之間的焊料接合來接合至第一封裝組件100A。模組160A經由接墊162、導電連接件158、導電連接件152以及背側重佈線結構106耦接至第一封裝組件100A的晶粒50。圖18B示出包含接合至第一封裝組件100B的模組160A的第一封裝200B。模組160A藉由導電連接件156與接墊162之間的焊料接合來接合至第一封裝組件100B。模組160A經由接墊162、導電連接件156、接墊154以及背側重佈線結構106耦接至第一封裝組件100B的晶粒50。圖18C示出包含接合至第一封裝組件100C的模組160B的第一封裝200C。模組160B利用設置在接墊154上的彈簧式接觸件166而放置於第一封裝組件100C上。如將關於圖30描述，可接著使用機械支架450A或類似者將模組160B固定至第一封裝組件100C。模組160B經由彈簧式接觸件166、接墊154以及背側重佈線結構106耦接至第一封裝組件100C的晶粒50。圖18D示出經單體化的第一封裝組件100C，其包括接墊154且在接墊154上不具有導電連接件，所述第一封裝組件100C在無模組160附接至第一封裝組件100C的情況下放置於托盤170中。
圖18E示出包含接合至第一封裝組件100B的模組160C的第一封裝200D。模組160C可包含與其表面齊平的導電接墊（未單獨地示出）。導電連接件156接合至模組160C的導電接墊。模組160C可使用與用以將模組160A接合至第一封裝組件100B的製程（上文參考圖17B所論述）類似的製程接合至第一封裝組件100B。模組160C經由導電連接件156、接墊154以及背側重佈線結構106耦接至第一封裝組件100B的晶粒50。
圖19至圖24示出根據一些實施例的用於形成系統晶圓（SoW）封裝400A的製程期間的中間步驟的截面圖。在圖19中，提供載板基底402，並將積體電路晶粒405附接至載板基底402。可在載板基底402上形成釋放層404。載板基底402可為玻璃載板基底、陶瓷載板基底或類似者。載板基底402可為晶圓，以使得多個封裝可在載板基底402上同時形成。釋放層404可與載板基底402一起從將在後續步驟中形成的上覆結構移除。在一些實施例中，釋放層404為任何合適的黏著劑、環氧樹脂、晶粒附接膜（DAF）或類似者，且被施加在載板基底402的表面上。
使用釋放層404將積體電路晶粒405附接至載板基底402。可將所需類型及量的積體電路晶粒405附接至載板基底102。積體電路晶粒405可與主動裝置晶粒50C相同或類似。舉例而言，積體電路晶粒405中的每一者可為：邏輯晶粒（例如中央處理單元（CPU）、圖形處理單元（GPU）、系統晶片（SoC）、應用程式處理器（AP）、微控制器或類似者）；記憶體晶粒（例如動態隨機存取記憶體（DRAM）晶粒、靜態隨機存取記憶體（SRAM）晶粒、高頻寬記憶體（HBM）晶粒或類似者）；輸入/輸出（I/O）介面晶粒；電力管理晶粒（例如電力管理積體電路（PMIC）晶粒或類似者）；射頻（RF）晶粒；感測器晶粒；微機電系統（MEMS）晶粒；訊號處理晶粒（例如數位訊號處理（DSP）晶粒或類似者）；前端晶粒（例如類比前端（AFE）晶粒或類似者）；類似者或其組合。
如圖19中所示出，積體電路晶粒405可包含與主動裝置晶粒50C相同的組件。舉例而言，積體電路晶粒可包含半導體基底52C、半導體基底52C上的裝置54、環繞裝置54的ILD 56C、ILD 56C上方的內連線結構60C、內連線結構60C上方的接墊62C、內連線結構60C及接墊62C上方的鈍化膜64C、耦接至接墊62C的晶粒連接件66C以及包圍晶粒連接件66C的介電層68C。
在圖20中，在釋放層404上方形成環繞積體電路晶粒405的包封體406。在形成之後，包封體406包封積體電路晶粒405。包封體406可為模製化合物、環氧樹脂或類似者，且可藉由壓縮模製、轉移模製或類似者來施加。包封體406可以液體或半液體形式施加且接著被固化。在一些實施例中，包封體406形成在載板基底402上方使得積體電路晶粒405被掩埋或覆蓋，且隨後對包封體406執行平坦化製程。平坦化製程可使包封體406及積體電路晶粒的介電層68C平坦化，且可暴露積體電路晶粒405的晶粒連接件66C。包封體406、晶粒連接件66C以及介電層68的最頂表面可在平坦化製程之後彼此齊平。平坦化製程可例如為化學機械拋光（CMP）。
在圖21至圖23中，在包封體406及積體電路晶粒405上方形成具有精細特徵部分414及粗特徵部分426的重佈線結構430（參看圖23）。重佈線結構430包含金屬化圖案、介電層以及凸塊下金屬（UBM）。金屬化圖案亦可稱作重佈線層或重佈線。重佈線結構430繪示為具有四層金屬化圖案層的實例。更多或更少介電層及金屬化圖案可形成於重佈線結構430中。若要形成更少介電層及金屬化圖案，則可省略下文所論述的步驟及製程。若要形成更多介電層及金屬化圖案，則可重複下文所論述的步驟及製程。重佈線結構430的精細特徵部分414及粗特徵部分426包含不同尺寸的金屬化圖案及介電層。
在圖21中，形成重佈線結構430的精細特徵部分414。重佈線結構430的精細特徵部分414包含介電層408及介電層411，以及金屬化圖案410及金屬化圖案412。在一些實施例中，介電層408及介電層411由相同介電材料形成，且形成為相同厚度。同樣地，在一些實施例中，金屬化圖案410及金屬化圖案412的導電特徵由相同導電材料形成，且形成為相同厚度。特定而言，介電層408及介電層411具有較小的第一厚度T1 ，例如介於約5微米至約40微米的範圍內，且金屬化圖案410及金屬化圖案412的導電特徵具有較小的第二厚度T2 ，例如介於約1微米至約25微米的範圍內。
作為形成重佈線結構430的精細特徵部分414的一個實例，介電層408沈積在包封體406、介電層68C以及晶粒連接件66C上。在一些實施例中，介電層408由例如PBO、聚醯亞胺、BCB或類似者的感光性材料形成，所述感光性材料可使用微影罩幕來圖案化。介電層408可藉由旋轉塗佈、疊層、CVD、類似者或其組合形成。隨後將介電層408圖案化。圖案化形成開口以暴露晶粒連接件66C的一些部分。圖案化可藉由可接受的製程來進行，例如當介電層408為感光性材料時藉由將介電層408暴露於光或藉由使用例如非等向性蝕刻來蝕刻。若介電層408為感光性材料，則介電層408可在曝光之後顯影。
隨後形成金屬化圖案410。金屬化圖案410具有在介電層408的主表面上且沿所述主表面延伸的線路部分（亦稱作導電線或跡線），且具有延伸穿過介電層408以實體耦接且電耦接積體電路晶粒405的晶粒連接件66C的通孔部分（亦稱作導通孔）。作為一個實例，金屬化圖案410可藉由以下製程來形成：在介電層408上方以及在延伸穿過介電層408的開口中形成晶種層。在一些實施例中，晶種層為金屬層，其可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層及位於鈦層上方的銅層。可使用例如物理氣相沈積（PVD）或類似者來形成晶種層。隨後在晶種層上形成光阻並圖案化所述光阻。光阻可藉由旋轉塗佈或類似方法來形成，且可暴露於光以用於圖案化。光阻的圖案對應於金屬化圖案410。圖案化形成穿過光阻的開口以暴露晶種層。隨後在光阻的開口中及晶種層的暴露部分上形成導電材料。導電材料可藉由鍍覆形成，所述鍍覆例如是電鍍或無電鍍覆或類似者。導電材料可包括金屬，例如銅、鈦、鎢、鋁或類似者。導電材料與其下方的晶種層組合形成金屬化圖案410。光阻及晶種層的其上未形成導電材料的部分被移除。可藉由可接受的灰化或剝離製程（例如使用氧電漿或類似者）來移除光阻。一旦光阻被移除，就使用例如濕式蝕刻或乾式蝕刻等可接受的蝕刻製程來移除晶種層的暴露部分。
隨後將介電層411沈積於金屬化圖案410及介電層408上。介電層411可以類似於介電層408的方式形成，且可由與介電層408的材料類似的材料形成。隨後形成金屬化圖案412。金屬化圖案412具有在介電層411的主表面上且沿所述主表面延伸的線路部分，且具有延伸穿過介電層411以實體耦接且電耦接金屬化圖案410的通孔部分。金屬化圖案412可以類似於金屬化圖案410的方式形成，且可由與金屬化圖案410的材料類似的材料形成。儘管精細特徵部分414示出為包含兩個介電層及兩個金屬化圖案，但可形成任何數目的介電層及金屬化圖案於精細特徵部分414中。
在圖22中，形成重佈線結構430的粗特徵部分426。重佈線結構430的粗特徵部分426包含介電層416、介電層420以及介電層424，以及金屬化圖案418及金屬化圖案422。在一些實施例中，介電層416、介電層420以及介電層424由相同介電材料形成，且形成為相同厚度。同樣地，在一些實施例中，金屬化圖案418及金屬化圖案422的導電特徵由相同導電材料形成，且形成為相同厚度。特定而言，介電層416、介電層420以及介電層424具有較大的第三厚度T3 ，例如介於約5微米至約40微米的範圍內，且金屬化圖案418及金屬化圖案422的導電特徵具有較大的第四厚度T4 ，例如介於約1微米至約25微米的範圍內。在各種實施例中，第三厚度T3 可大於第一厚度T1 （參看圖21），且第四厚度T4 可大於第二厚度T2 （參看圖21）。
為形成重佈線結構430的粗特徵部分426，可在金屬化圖案412及介電層411上沈積介電層416。介電層416可以類似於介電層408的方式形成，且可由與介電層408的材料類似的材料形成。隨後形成金屬化圖案418。金屬化圖案418具有在介電層416的主表面上且沿所述主表面延伸的線路部分，且具有延伸穿過介電層416以實體耦接且電耦接金屬化圖案412的通孔部分。金屬化圖案418可以類似於金屬化圖案410的方式形成，且可由與金屬化圖案410的材料類似的材料形成。
隨後在金屬化圖案418及介電層416上沈積介電層420。介電層420可以類似於介電層408的方式形成，且可由與介電層408的材料類似的材料形成。隨後形成金屬化圖案422。金屬化圖案422具有在介電層420的主表面上且沿所述主表面延伸的線路部分，且具有延伸穿過介電層420以實體耦接且電耦接金屬化圖案418的通孔部分。金屬化圖案422可以類似於金屬化圖案410的方式形成，且可由與金屬化圖案410的材料類似的材料形成。
隨後在金屬化圖案422及介電層420上沈積介電層424。介電層424可以類似於介電層408的方式形成，且可由與介電層408的材料類似的材料形成。儘管粗特徵部分426示出為包含三個介電層及兩個金屬化圖案，但可形成任何數目的介電層及金屬化圖案於粗特徵部分426中。在一些實施例中，精細特徵部分414及粗特徵部分426可各自包含3個介電層及3個金屬化圖案。
歸因於包含在粗特徵部分426及精細特徵部分414中金屬化圖案的的厚度，粗特徵部分426可具有比精細特徵部分414更低的電阻。由於電阻更低，因此粗特徵部分426可用於佈設電力線。精細特徵部分414可用以佈設訊號線，所述訊號線並不需要更低的電阻。包含粗特徵部分426及精細特徵部分414兩者允許佈設電力線以及訊號線，同時最小化重佈線結構430的厚度。
在圖23中，形成用於外部連接至重佈線結構430的UBM 428。UBM 428具有在介電層424的主表面上且沿所述主表面延伸的凸塊部分，且具有延伸穿過介電層424以實體耦接且電耦接金屬化圖案422的通孔部分。因此，UBM 428電耦接至積體電路晶粒405。UBM 428可以與金屬化圖案410類似的方式及類似的材料形成。在一些實施例中，UBM 428具有與金屬化圖案410、金屬化圖案412、金屬化圖案418以及金屬化圖案422（參看圖22）不同的尺寸。
在圖24中，在UBM 428上形成導電連接件432，從而形成SoW封裝400A。導電連接件432可為球柵陣列封裝（BGA）連接件、焊料球、金屬柱、受控塌陷晶粒連接（C4）凸塊、微凸塊、化學鍍鎳鈀浸金（ENEPIG）形成的凸塊、化學鍍鎳浸金（ENIG）形成的凸塊或類似者。導電連接件432可包含導電材料，例如焊料、銅、鋁、金、鎳、銀、鈀、錫、類似者或其組合。在一些實施例中，導電連接件432藉由以下製程來形成：首先經由蒸鍍、電鍍、列印、焊料轉移、植球或類似者形成焊料層或焊錫膏層。一旦焊料層已形成於所述結構上，就可執行回焊以將材料塑形成所需凸塊形狀。
在圖25中，第一封裝200A及外部連接件434A接合至SoW封裝400A，所述第一封裝包含接合至第一封裝組件100A的模組160A。在各種實施例中，SoW封裝400A可以是面積為10,000平方毫米或大於10,000平方毫米的超大扇出型晶圓級封裝。可使用取放機器或類似者來將第一封裝200A放置在SoW封裝400A上方。一旦放置第一封裝200A，就可回焊導電連接件432及導電連接件150以將第一封裝200A接合至SoW封裝400A。儘管圖25示出將第一封裝200A附接至SoW封裝400A，但可替代地或另外地將第一封裝200B或第一封裝200C附接至SoW封裝400A。
此外，將外部連接件434A附接至SoW封裝400A。外部連接件434A為用於SoW封裝400A至其他SoW封裝400A、其他外部系統或類似者的電學介面及實體介面。舉例而言，在SoW封裝400A安裝為較大外部系統（例如資料中心）的部分時，外部連接件434A可用以將SoW封裝400A耦接至外部系統。外部連接件434A的實例包含較大引線接合、用於帶狀電纜的接收器、可撓性印刷電路或類似者。外部連接件434A包含接墊438，所述接墊438可類似於UBM 428。外部連接件434A可包含不同的組件，例如底盤（chassis）、接墊438以及外部連接引腳，所述不同的組件可包括不同材料。外部連接件434A亦包含接墊438上的導電連接件436，所述導電連接件436可類似於導電連接件432。接墊438及導電連接件432用於實體連接及電連接至SoW封裝400A。附接外部連接件434A可包含使用取放機器或類似者來將外部連接件434A放置在SoW封裝400A上，且隨後回焊導電連接件436及導電連接件432以實體耦接且電耦接接墊438及UBM 428。
可形成底部填充物440以填充第一封裝200A與SoW封裝400A之間的間隙。底部填充物440可在附接第一封裝200A之後藉由毛細流動製程形成，或可在附接第一封裝200A之前藉由合適的沈積方法形成。
在圖26中，將載板基底402自包封體406及積體電路晶粒405分離，以形成經封裝裝置500A。根據一些實施例，所述分離包含將光（例如雷射光或UV光）投射於釋放層404上，以使得釋放層404在光熱下分解並使得載板基底402可被移除。
圖27示出將第一封裝組件100C接合至SoW封裝400A的實施例，而非如圖25中所示出的將第一封裝200A接合至SoW封裝。可使用取放機器或類似者來將第一封裝組件100C放置在SoW封裝400A上方。一旦放置第一封裝組件100C，就可回焊導電連接件432及導電連接件150，以將第一封裝組件100C接合至SoW封裝400A。亦使用與上文參考圖25所論述的相同的方法將包含接墊438及導電連接件436的外部連接件434A接合至SoW封裝400A。
可形成底部填充物440以填充第一封裝組件100C與SoW封裝400A之間的間隙。底部填充物440可在附接第一封裝組件100C之後藉由毛細流動製程形成，或可在附接第一封裝組件100C之前藉由合適的沈積方法形成。
在圖28中，將載板基底402自包封體406及積體電路晶粒405分離，並形成穿過SoW封裝400A的螺栓孔442。根據一些實施例，所述分離包括將光（例如雷射光或UV光）投射於釋放層404上，以使得釋放層404在光熱下分解並使得可移除載板基底402。螺栓孔442可藉由例如雷射鑽孔、機械鑽孔或類似者的鑽孔製程而形成。螺栓孔442可藉由以下方式形成：利用鑽孔製程鑽出用於螺栓孔442的輪廓，且隨後移除由該輪廓分隔開的材料。
在圖29中，將包含彈簧式接觸件166的模組160B放置於第一封裝組件100C上，以形成第一封裝200C。模組160B可與上文參考圖17C所論述的模組160B類似或相同，且彈簧式接觸件166可與上文參考圖17C所論述的彈簧式接觸件166相同或類似。可使用取放機器或類似者來將模組160B放置在第一封裝組件100C上方。
在圖30中，安裝機械支架450A以將模組160B固定至第一封裝組件100C及SoW封裝400A，從而形成經封裝裝置500B。機械支架450A為剛性支撐件，其可由具有高剛度的材料形成，所述材料例如是可包含鋼、鈦、鈷或類似者的金屬。機械支架450A實體地嚙合模組160B的部分。使用機械支架450A來夾持模組160B至第一封裝組件100C及SoW封裝400A可減少經封裝裝置500B中的任何翹曲。
利用螺栓452A將模組160B固定在第一封裝組件100C與機械支架450A之間。螺栓452A旋擰穿過SoW封裝400的螺栓孔442（參看圖29）且穿過機械支架450A中的對應螺栓孔。固定件454A旋擰至螺栓452A上並擰緊以將模組160B夾持在第一封裝組件100C與機械支架450A之間。固定件454A可為例如旋擰至螺栓452A的螺帽。固定件454A可在螺栓452A上擰緊，使得彈簧式接觸件166被壓縮。在附接之後，機械支架450A的部分設置於模組160B與外部連接件434A之間。圖30中所示出的實施例可不包含設置於模組160B與第一封裝組件100C之間的底部填充物，且模組160B的部分可藉由開口或間隙與第一封裝組件100C分隔開。
圖31示出根據一實施例的經封裝裝置500C，經封裝裝置500C包含第一封裝200B（其包含接合至第一封裝組件100B的模組160A）、第一封裝200D（其包含接合至第一封裝組件100B的模組160C）以及SoW封裝400B。SoW封裝400B可以類似於SoW封裝400A的方式形成，且可由與SoW封裝400A的材料類似的材料形成，但可包含兩個區域，第一封裝200B與第一封裝200D接合在所述兩個區域中。在各種實施例中，SoW封裝400B可以是面積為10,000平方毫米或大於10,000平方毫米的超大扇出型晶圓級封裝。第一封裝200B可與第二封裝200D分隔開約0.05毫米至約10毫米、例如約0.5毫米的距離。
可使用取放機器或類似者來將第一封裝200B及第一封裝200D放置在SoW封裝400B上方。一旦放置第一封裝200B及第一封裝200D，就可回焊導電連接件432及導電連接件150以將第一封裝200B及第一封裝200D接合至SoW封裝400B。儘管圖31示出將第一封裝200B及第一封裝200D附接至SoW封裝400B，但可替代地或另外地將第一封裝200A至第一封裝200D的任何組合附接至SoW封裝400B。可形成底部填充物440以填充第一封裝200B及第一封裝200D與SoW封裝400B之間的間隙。底部填充物440可在附接第一封裝200B及第一封裝200D之後藉由毛細流動製程形成，或可在附接第一封裝200B及第一封裝200D之前藉由合適的沈積方法形成。
此外，外部連接件434B附接至SoW封裝400B。外部連接件434B為用於SoW封裝400B至其他SoW封裝400B、其他外部系統或類似者的電學介面及實體介面。舉例而言，當SoW封裝400B安裝為較大外部系統（例如資料中心）的部分時，外部連接件434B可用以將SoW封裝400B耦接至外部系統。外部連接件434B的實例包含較大引線接合、用於帶狀電纜的接收器、可撓性印刷電路或類似者。外部連接件434B包含接墊438，所述接墊438可類似於UBM 428。外部連接件434B可包含不同的組件，例如底盤、接墊438以及外部連接引腳，所述不同的組件可包括不同材料。外部連接件434B亦包含位於接墊438上的導電連接件436，所述導電連接件436可類似於導電連接件432。接墊438及導電連接件432用於實體連接及電連接至SoW封裝400B。附接外部連接件434B可包含使用取放機器或類似者來將外部連接件434B放置在SoW封裝400B上，且隨後回焊導電連接件436及導電連接件432以實體耦接且電耦接接墊438及UBM 428。
安裝機械支架450B以將散熱模組460固定至SoW封裝400B的背側。散熱模組460可為散熱片、熱散播器、冷板或類似者。機械支架450B為可由具有高剛度的材料所形成的剛性支撐件，所述材料例如是可包含鋼、鈦、鈷或類似者的金屬。機械支架450B實體地嚙合SoW封裝400B的部分。使用機械支架450B來夾持散熱模組460至SoW封裝400B可減少SoW封裝400B中的任何翹曲。
利用螺栓452B將散熱模組460固定至SoW封裝400B的背側。螺栓452B旋擰穿過形成於SoW 封裝400B中的螺栓孔442且穿過機械支架450B中的對應螺栓孔。固定件454B旋擰至螺栓452B上並擰緊以將散熱模組460夾持至SoW封裝400B，其中SoW封裝400B設置於機械支架450B與散熱模組460之間。固定件454B可為例如旋擰至螺栓452B的螺帽。在附接之後，機械支架450B的部分設置於第一封裝200B與第一封裝200D之間，且設置於外部連接件434B外部。
在將散熱模組460與SoW封裝400B固定在一起之前，熱界面材料（thermal interface material；TIM）462可施配於SoW封裝400B的背側上，從而將散熱模組460實體耦接且熱耦接至SoW封裝400B。在一些實施例中，TIM 462由包括以下的膜形成：銦、導熱膏（thermal grease）、導熱片、相變材料、其組合或類似者。在固定期間，將固定件454B擰緊，由此增大藉由散熱模組460及機械支架450B施加至SoW封裝400B的機械力。將固定件454B擰緊直至散熱模組460對TIM 462施加所需量的壓力為止。
圖32示出包含模組160B、第一封裝組件100C、機械支架450C、機械支架450B、散熱模組460以及SoW封裝400C的經封裝裝置500D。SoW封裝400C可以類似於SoW封裝400A的方式形成，且可由與SoW封裝400A的材料類似的材料形成，但可包含兩個區域，在所述兩個區域中接合第一封裝組件100C。在各種實施例中，SoW封裝400C可以是面積為10,000平方毫米或大於10,000平方毫米的超大扇出型晶圓級封裝。
可使用取放機器或類似者來將第一封裝組件100C中的每一者放置在SoW封裝400C上方。一旦放置第一封裝組件100C，就可回焊導電連接件432及導電連接件150以將第一封裝組件100C接合至SoW封裝400C。儘管圖32示出第一封裝200C附接至SoW封裝400C，但可替代地或另外地將第一封裝200A至第一封裝200D的任何組合附接至SoW封裝400C。可形成底部填充物440以填充第一封裝組件100C與SoW封裝400C之間的間隙。底部填充物440可在附接第一封裝組件100C之後藉由毛細流動製程形成，或可在附接第一封裝組件100C之前藉由合適的沈積方法形成。
此外，外部連接件434B附接至SoW封裝400C。外部連接件434B為用於SoW封裝400C至其他SoW封裝400C、其他外部系統或類似者的電學介面及實體介面。舉例而言，當SoW封裝400C安裝為較大外部系統（例如資料中心）的部分時，外部連接件434B可用以將SoW封裝400C耦接至外部系統。外部連接件434B的實例包含較大引線接合、用於帶狀電纜的接收器、可撓性印刷電路或類似者。外部連接件434B包含接墊438，所述接墊438可類似於UBM 428。外部連接件434B可包含不同的組件，例如底盤、接墊438以及外部連接引腳，所述不同的組件可包括不同材料。外部連接件434B亦包含接墊438上的導電連接件436，所述導電連接件436可類似於導電連接件432。接墊438及導電連接件432用於實體連接及電連接至SoW封裝400C。附接外部連接件434B可包含使用取放機器或類似者來將外部連接件434B放置在SoW封裝400C上，且隨後回焊導電連接件436及導電連接件432以實體耦接且電耦接接墊438及UBM 428。
可使用取放機器或類似者來將模組160B中的每一者放置在相應的第一封裝組件100C上方。隨後安裝機械支架450C以將模組160B中的每一者固定至相應第一封裝組件100C，從而形成第一封裝200C。機械支架450C為可由具有高剛度的材料所形成的剛性支撐件，所述材料例如是可包含鋼、鈦、鈷或類似者的金屬。機械支架450C實體地嚙合模組160B的部分。使用機械支架450C來將模組160B夾持至第一封裝組件100C及SoW封裝400C，可減少經封裝裝置500D中的任何翹曲。
利用螺栓452C將模組160B固定在第一封裝組件100C與機械支架450C之間。螺栓452C旋擰穿過SoW封裝400C的螺栓孔442且穿過機械支架450C中的對應螺栓孔。固定件454C旋擰至螺栓452C上並擰緊以夾持第一封裝組件100C與機械支架450C之間的模組160B。固定件454C可為例如旋擰至螺栓452C的螺帽。固定件454C可在螺栓452C上擰緊，使得壓縮彈簧式接觸件166。在附接之後，機械支架450C的部分設置於第一封裝組件100C與第一封裝組件100C之間以及第一封裝組件100C與外部連接件434B之間。
安裝機械支架450B以將散熱模組460固定至SoW封裝400C的背側。機械支架450C亦可將散熱模組460固定至SoW封裝400C的背側。散熱模組460可為散熱片、熱散播器、冷板或類似者。機械支架450B為可由具有高剛度的材料所形成的剛性支撐件，所述材料例如是可包含鋼、鈦、鈷或類似者的金屬。機械支架450B實體地嚙合SoW封裝400C的部分。使用機械支架450B來將散熱模組460夾持至SoW封裝400C可減少SoW封裝400C中的任何翹曲。
利用螺栓452B將散熱模組460緊固至SoW封裝400C的背側。螺栓452B旋擰穿過形成於SoW封裝400C中的螺栓孔442且穿過機械支架450B中的對應螺栓孔。固定件454B旋擰至螺栓452B上並擰緊以將散熱模組460夾持至SoW封裝400C，其中SoW封裝400C設置於機械支架450B與散熱模組460之間。固定件454B可為例如旋擰至螺栓452B的螺帽。在附接之後，機械支架450B的部分設置在外部連接件434B的外部。
在將散熱模組460與SoW封裝400C固定在一起之前，可將熱界面材料（TIM）462施配於SoW封裝400C的背側上，從而將散熱模組460實體耦接且熱耦接至SoW封裝400C。在一些實施例中，TIM 462由包括以下的膜形成：銦、導熱膏、導熱片、相變材料、其組合或類似者。在固定期間，將固定件454B及固定件454C擰緊，由此增大藉由散熱模組460以及機械支架450B及機械支架450C施加至SoW封裝400C的機械力。將固定件454B及固定件454C擰緊直至散熱模組460對TIM 462施加所需量的壓力為止。
圖33至圖38示出根據各種實施例的SoW封裝400的俯視圖。在圖33至圖35中示出的實施例中，SoW封裝400具有圓形形狀。圖33至圖35中示出的SoW封裝400可為中間結構，其可經歷鋸割、分割或類似製程以形成圖36至圖38中示出的SoW封裝400。SoW封裝400包含各種積體電路晶粒405，例如計算晶粒405A、記憶體晶粒405B以及輸入/輸出（I/O）晶粒405C（圖式中示出的計算晶粒405A、記憶體晶粒405B以及輸入/輸出（I/O）晶粒405C統稱為積體電路晶粒405）。在一些實施例中，計算晶粒405A可包含中央處理單元（CPU）、圖形處理單元（GPU）、特殊應用積體電路（application-specific integrated circuit；ASIC）、場可程式化閘陣列（field programmable gate array；FPGA）或類似者。記憶體晶粒405B可包含高頻寬記憶體（HBM）晶粒、動態隨機存取記憶體（DRAM）晶粒、混合記憶體立方體（HMC）或類似者。
在圖33中示出的實施例中，第一封裝200設置於積體電路晶粒405中的每一者上方。第一封裝200可為上文所論述的第一封裝200A至第一封裝200E中的任一者。在圖34中示出的實施例中，每一對兩個記憶體晶粒405B共享第一封裝200，且每一組四個計算晶粒405A共享第一封裝200。在圖35中示出的實施例中，可為I/O晶粒405C中的每一者提供第一封裝200中的兩個，且可為計算晶粒405A中的每一者提供四個第一封裝200。其他配置為可能的，且可為任何數目的積體電路晶粒405提供任何數目的第一封裝200。SoW封裝400更包含外部連接件434。
在圖36至圖38中示出的實施例中，SoW封裝400具有八邊形形狀。此可允許互連的SoW封裝400被放置為更接近於彼此。SoW封裝400包含各種積體電路晶粒405，例如計算晶粒405A、記憶體晶粒405B以及輸入/輸出（I/O）晶粒405C。在圖36中示出的實施例中，第一封裝200設置於積體電路晶粒405中的每一者上方。第一封裝200可為上文所論述的第一封裝200A至第一封裝200E中的任一者。在圖37中示出的實施例中，每一對兩個記憶體晶粒405B共享第一封裝200，且每一組四個計算晶粒405A共享第一封裝200。在圖38中示出的實施例中，可為I/O晶粒405C中的每一者提供第一封裝200中的兩個，且可為計算晶粒405A中的每一者提供四個第一封裝200。其他配置為可能的，且可為任何數目的積體電路晶粒405提供任何數目的第一封裝200。SoW封裝400更包含外部連接件434。
提供包含設置於模組160與SoW封裝400之間的第一封裝組件100（包含設置於其中的晶粒50）的經封裝裝置500減小IPD與功能晶粒之間的距離，所述IPD包含於第一封裝組件100中，所述功能晶粒包含於SoW封裝400中。此增強電力分佈網路（power distribution network；PDN）性能。上文所論述的各種實施例可適用於資料中心應用、伺服器應用或類似者中的高性能計算（HPC）（例如人工智慧（AI）伺服器的加速器、雲計算系統、邊緣計算系統或類似者）。
亦可包含其他特徵及製程。舉例而言，可包含測試結構以輔助對3D封裝或3DIC裝置的驗證測試。測試結構可包含例如形成於重佈線層中或形成在基底上的測試接墊，其允許測試3D封裝或3DIC、使用探針及/或探針卡以及類似者。可對中間結構以及最終結構執行驗證測試。另外，本文中所揭露的結構及方法可結合併有對已知良好晶粒的中間驗證的測試方法使用，以提高良率及降低成本。
根據一實施例，一種裝置包含：第一封裝組件，其包含第一積體電路晶粒；至少部分地包圍第一積體電路晶粒的第一包封體；以及位於第一包封體上且耦接至第一積體電路晶粒的重佈線結構；第二封裝組件，接合至第一封裝組件，第二封裝組件包含積體被動裝置；以及至少部分地包圍積體被動裝置的第二包封體；以及電力模組，經由第二封裝組件附接至第一封裝組件。在一實施例中，所述裝置更包含耦接至重佈線結構的電連接件，所述電連接件環繞第二封裝組件。在一實施例中，第二封裝並不包含設置於第二包封體中的主動裝置。在一實施例中，電力模組使用焊料接合來接合至第二封裝組件。在一實施例中，電力模組使用彈簧式接觸件來耦接至第二封裝。在一實施例中，所述裝置更包含延伸穿過第一封裝組件的機械支架，所述機械支架接觸電力模組，所述機械支架將電力模組附接至第二封裝組件。在一實施例中，所述裝置更包含附接至第一封裝組件的散熱模組，所述第二封裝組件設置在第一封裝組件的第一側上，且第二封裝組件設置在第一封裝組件的與第一側相對的第二側上。在一實施例中，所述裝置更包含設置於散熱模組與第一封裝組件之間的熱界面材料，機械支架將散熱模組附接至第一封裝組件。
根據另一實施例，一種方法包含：形成第一封裝組件，形成第一封裝組件包含將第一積體被動裝置附接至第一重佈線結構；利用包封體包封第一積體被動裝置；以及在第一積體被動裝置及包封體上方形成第二重佈線結構；將電力模組附接至第二重佈線結構；以及將第一重佈線結構接合至第二封裝組件的第三重佈線結構，所述第二封裝組件包含耦接至第三重佈線結構的第一積體電路晶粒。在一實施例中，所述方法更包含在將電力模組附接至第一封裝組件之後且在將第一封裝組件接合至第二封裝組件之前將第一封裝組件單體化。在一實施例中，在第一封裝組件接合至第二封裝組件之後，將電力模組附接至第一封裝組件。在一實施例中，將電力模組附接至第一封裝包含：使用取放機器將電力模組放置在第一封裝組件上方；以及使用機械支架來將電力模組固定至第一封裝組件，所述機械支架包含延伸穿過第二封裝組件的螺栓。在一實施例中，電力模組包含彈簧式接觸件，且機械支架向彈簧式接觸件施加壓力以壓縮彈簧式接觸件。在一實施例中，所述方法更包含：在電力模組與第一封裝組件的第一側之間沈積第一底部填充物材料；以及在第一封裝組件的第二側與第二封裝組件之間沈積第二底部填充物材料。
根據又一實施例，一種裝置包含：第一封裝，其包含多個積體電路晶粒；多個電力模組，位於第一封裝上方，電力模組中的每一者在垂直於第一封裝的主表面的方向上設置在積體電路晶粒正上方；以及多個封裝組件，插置於積體電路晶粒與電力模組之間，封裝組件中的每一者包含積體被動裝置（IPD）。在一實施例中，在積體電路晶粒中的每一者上方設置電力模組中的一者及封裝組件中的一者。在一實施例中，在積體電路晶粒中的每一者上方設置多於一個的電力模組及多於一個的封裝組件。在一實施例中，在多於一個的積體電路晶粒上方設置一個電力模組及一個封裝組件。在一實施例中，封裝組件中的每一者包含：前側重佈線結構，設置於所述前側重佈線結構上方的IPD；包封體，設置於前側重佈線結構上方且包圍IPD；穿孔，延伸穿過包封體且耦接至前側重佈線結構；以及背側重佈線結構，位於穿孔、IPD以及包封體上方，所述背側重佈線結構經由穿孔耦接至前側重佈線結構。在一實施例中，第一封裝在俯視圖中具有八邊形形狀。
前文概述若干實施例的特徵，使得本領域的技術人員可更佳地理解本揭露內容的態樣。本領域的技術人員應理解，其可易於使用本揭露內容作為設計或修改用於實現本文中所引入之實施例的相同目的及/或達成相同優勢的其他製程及結構的基礎。本領域的技術人員亦應認識到，此類等效構造並不脫離本揭露內容的精神及範疇，且本領域的技術人員可在不脫離本揭露內容的精神及範疇的情況下在本文中作出各種改變、替代以及更改。
50A:積體被動裝置 50B:離散被動裝置 50C:主動裝置晶粒 52A、52B、52C:半導體基底 53B、116:穿孔 54:裝置 56、56A、56C:層間介電 58:導電插塞 60A、60C:內連線結構 62A、62B、62C、154、162、438:接墊 64A、64C:鈍化膜 64B:鈍化層 66A、66B、66C:晶粒連接件 68A、68C、108、112、124、128、132、136、408、411、416、420、424:介電層 70A、70B、70C:區域 100A、100B、100C:第一封裝組件 101A、101B:封裝區 102、402:載板基底 104、404:釋放層 106:背側重佈線結構 110、126、130、134、410、412、418、422:金屬化圖案 114、151:開口 118:黏著劑 120、406:包封體 122:前側重佈線結構 138、428:凸塊下金屬 149:膠帶 150、152、156、158、432、436:導電連接件 160A、160B、160C:模組 164、440:底部填充物 166:彈簧式接觸件 170:托盤 200A、200B、200C、200D、200E:第一封裝 400、400A、400B、400C:系統晶圓封裝 405:積體電路晶粒 405A:計算晶粒 405B:記憶體晶粒 405C:輸入/輸出晶粒 414:精細特徵部分 426:粗特徵部分 430:重佈線結構 434、434A、434B:外部連接件 442:螺栓孔 450、454A、454B、454C:固定件 450A、450B、450C:機械支架 452A、452B、452C:螺栓 460:散熱模組 462:熱界面材料 500、500A、500B、500C、500D:經封裝裝置 T1、T2、T3、T4:厚度
結合附圖閱讀以下具體實施方式將最佳地理解本揭露內容的態樣。應注意，根據業界中的標準慣例，各種特徵未按比例繪製。事實上，可出於論述清楚起見而任意地增加或減小各種特徵的尺寸。 圖1至圖4、圖5A、圖5B、圖6至圖15、圖16A至圖16C、圖17A至圖17C、圖18A至圖18E示出根據一些實施例的用於形成第一封裝的製程期間的中間步驟的截面圖。 圖19至圖24示出根據一些實施例的用於形成系統晶圓（system-on-wafer；SoW）封裝的製程期間的中間步驟的截面圖。 圖25至圖32示出根據一些實施例的用於形成經封裝裝置的製程期間的中間步驟的截面圖。 圖33至圖38示出根據一些實施例的經封裝裝置的俯視圖。
50A:積體被動裝置
50B:離散被動裝置
50C:主動裝置晶粒
100A:第一封裝組件
160A:模組
200A:第一封裝
400A:系統晶圓封裝
405:積體電路晶粒
406:包封體
428:凸塊下金屬
432、436:導電連接件
434A:外部連接件
438:接墊
440:底部填充物
500A:經封裝裝置

Claims (20)

  1. 一種裝置，包括： 第一封裝組件，包括： 第一積體電路晶粒； 第一包封體，至少部分地包圍所述第一積體電路晶粒；以及 重佈線結構，位於所述第一包封體上且耦接至所述第一積體電路晶粒； 第二封裝組件，接合至所述第一封裝組件，所述第二封裝組件包括： 積體被動裝置；以及 第二包封體，至少部分地包圍所述積體被動裝置；以及 電力模組，經由所述第二封裝組件附接至所述第一封裝組件。
  2. 如申請專利範圍第1項所述的裝置，更包括耦接至所述重佈線結構的電連接件，所述電連接件環繞所述第二封裝組件。
  3. 如申請專利範圍第2項所述的裝置，其中所述第二封裝不包括設置於所述第二包封體中的主動裝置。
  4. 如申請專利範圍第1項所述的裝置，其中所述電力模組使用焊料接合來接合至所述第二封裝組件。
  5. 如申請專利範圍第1項所述的裝置，其中所述電力模組使用彈簧式接觸件來耦接至所述第二封裝。
  6. 如申請專利範圍第5項所述的裝置，更包括延伸穿過所述第一封裝組件的機械支架，所述機械支架接觸所述電力模組，所述機械支架將所述電力模組附接至所述第二封裝組件。
  7. 如申請專利範圍第1項所述的裝置，更包括附接至所述第一封裝組件的散熱模組，其中所述第二封裝組件設置在所述第一封裝組件的第一側上，且其中所述第二封裝組件設置在所述第一封裝組件的與所述第一側相對的第二側上。
  8. 如申請專利範圍第7項所述的裝置，更包括設置於所述散熱模組與所述第一封裝組件之間的熱界面材料，其中機械支架將所述散熱模組附接至所述第一封裝組件。
  9. 一種方法，包括： 形成第一封裝組件，其中形成所述第一封裝組件包括： 將第一積體被動裝置附接至第一重佈線結構； 利用包封體包封所述第一積體被動裝置；以及 在所述第一積體被動裝置及所述包封體上方形成第二重佈線結構； 將電力模組附接至所述第二重佈線結構；以及 將所述第一重佈線結構接合至第二封裝組件的第三重佈線結構，所述第二封裝組件包括耦接至所述第三重佈線結構的第一積體電路晶粒。
  10. 如申請專利範圍第9項所述的方法，更包括在將所述電力模組附接至所述第一封裝組件之後且在將所述第一封裝組件接合至所述第二封裝組件之前將所述第一封裝組件單體化。
  11. 如申請專利範圍第9項所述的方法，其中在所述第一封裝組件接合至所述第二封裝組件之後，將所述電力模組附接至所述第一封裝組件。
  12. 如申請專利範圍第11項所述的方法，其中將所述電力模組附接至所述第一封裝包括：使用取放機器將所述電力模組放置在所述第一封裝組件上方；以及使用機械支架來將所述電力模組固定至所述第一封裝組件，所述機械支架包含延伸穿過所述第二封裝組件的螺栓。
  13. 如申請專利範圍第12項所述的方法，其中所述電力模組包括彈簧式接觸件，且其中所述機械支架向所述彈簧式接觸件施加壓力以壓縮所述彈簧式接觸件。
  14. 如申請專利範圍第9項所述的方法，更包括：在所述電力模組與所述第一封裝組件的第一側之間沈積第一底部填充物材料；以及在所述第一封裝組件的第二側與所述第二封裝組件之間沈積第二底部填充物材料。
  15. 一種裝置，包括： 第一封裝，包括多個積體電路晶粒； 多個電力模組，位於所述第一封裝上方，所述多個電力模組中的每一者在垂直於所述第一封裝的主表面的方向上設置於所述積體電路晶粒的正上方；以及 多個封裝組件，插置於所述積體電路晶粒與所述電力模組之間，所述多個封裝組件中的每一者包括積體被動裝置。
  16. 如申請專利範圍第15項所述的裝置，其中在所述積體電路晶粒中的每一者上方設置所述多個電力模組中的一者及所述多個封裝組件中的一者。
  17. 如申請專利範圍第15項所述的裝置，其中在所述積體電路晶粒中的每一者上方設置所述多個電力模組中的多於一者及所述多個封裝組件中的多於一者。
  18. 如申請專利範圍第15項所述的裝置，其中在所述積體電路晶粒中的多於一者上方設置所述多個電力模組中的一者及所述多個封裝組件中的一者。
  19. 如申請專利範圍第15項所述的裝置，其中所述封裝組件中的每一者包括： 前側重佈線結構，所述積體被動裝置設置於所述前側重佈線結構上方； 包封體，設置於所述前側重佈線結構上方且包圍所述積體被動裝置； 穿孔，延伸穿過所述包封體且耦接至所述前側重佈線結構；以及 背側重佈線結構，位於所述穿孔、所述積體被動裝置以及所述包封體上方，所述背側重佈線結構經由所述穿孔耦接至所述前側重佈線結構。
  20. 如申請專利範圍第15項所述的裝置，其中所述第一封裝在俯視圖中具有八邊形形狀。
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