CN112713126A - 多裸片封装结构、芯片及方法 - Google Patents

多裸片封装结构、芯片及方法 Download PDF

Info

Publication number
CN112713126A
CN112713126A CN202011610872.1A CN202011610872A CN112713126A CN 112713126 A CN112713126 A CN 112713126A CN 202011610872 A CN202011610872 A CN 202011610872A CN 112713126 A CN112713126 A CN 112713126A
Authority
CN
China
Prior art keywords
die
chip
flip
substrate
embedded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202011610872.1A
Other languages
English (en)
Inventor
蒲应江
蒋航
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chengdu Monolithic Power Systems Co Ltd
Original Assignee
Chengdu Monolithic Power Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chengdu Monolithic Power Systems Co Ltd filed Critical Chengdu Monolithic Power Systems Co Ltd
Priority to CN202011610872.1A priority Critical patent/CN112713126A/zh
Publication of CN112713126A publication Critical patent/CN112713126A/zh
Priority to US17/545,229 priority patent/US12002787B2/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48235—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本申请公开了一种多裸片封装结构、芯片及方法。该多裸片封装结构包括：嵌入裸片，被埋在基板中；倒装裸片，被放置在基板的上方，通过导体与基板电连接；贴合裸片，被贴在倒装裸片上方，通过键合线与基板电连接。所述多裸片封装结构降低了成本、提高了性能。

Description

多裸片封装结构、芯片及方法
技术领域
本发明涉及一种半导体封装，更具体地说，本发明涉及一种多裸片封装结构、芯片及方法。
背景技术
近几年来，客户端电子产品的要求在显著提高。微型化和可便携性成为势不可挡的趋势，促使芯片封装更加紧凑。相应地，便携式电子设备在具有更多功能和更好性能的同时，其体积也变得越来越小。因此，现今的功率供应系统被要求具有更小的尺寸、更高的功率输出、更多的功能和更高的效率。在这些要求下，有些技术将开关器件如场效应晶体管和控制器集成进单片裸片。但是，通常来说，控制器采用互补金属氧化物半导体工艺(CMOS工艺)，需要18至20层掩膜制作工艺；而开关器件通常采用双扩散金属氧化物半导体工艺(DMOS工艺)，只需要8至9层掩膜制作工艺。因此，这种单裸片由于将开关器件和控制器一起制作，制作成本高。
发明内容
因此本发明的目的在于解决现有技术的上述技术问题，提出一种多裸片封装结构、芯片及方法。
根据本发明的实施例，提出了一种多裸片封装结构，包括：嵌入裸片，被埋在基板中；倒装裸片，被放置在基板的上方，通过导体与基板电连接；贴合裸片，被贴在倒装裸片上方，通过键合线与基板电连接。
根据本发明的实施例，还提出了一种多裸片封装芯片，包括：输入引脚，接收输入电压，该输入引脚电连接至其上形成有上端功率开关的第一裸片；开关引脚，电连接至第一裸片和其上形成有下端功率开关的第二裸片；接地引脚，电连接至第二裸片；控制引脚，接收控制信号，所述控制引脚电连接至其上形成有控制器的第三裸片；其中：第一裸片、第二裸片和第三裸片的其中一个裸片为嵌入裸片，被埋在基板中；另一个裸片为倒装裸片，被放置在基板上方；还有一个裸片为贴合裸片，被贴在倒装裸片的上方，并通过键合线与基板电连接。
根据本发明的实施例，还提出了一种多裸片封装的方法，包括：将嵌入裸片埋入基板，所述基板具有多层金属层；将倒装裸片放置在基板上方；将贴合裸片贴在倒装裸片上方；通过导体电连接嵌入裸片、倒装裸片和基板，通过键合线电连接贴合裸片和基板。
根据本发明各方面的上述多裸片封装结构，芯片及方法，降低了成本、减小了寄生阻抗。
附图说明
图1为根据本发明实施例的多裸片封装结构100的剖面结构示意图；
图2为根据本发明实施例的多裸片封装结构200的剖面结构示意图；
图3为根据本发明实施例的多裸片封装结构300的剖面结构示意图；
图4为根据本发明实施例的多裸片封装结构400的剖面结构示意图；
图5为根据本发明实施例的多裸片封装结构500的剖面结构示意图；
图6为根据本发明实施例的多裸片封装结构600的剖面结构示意图；
图7为根据本发明实施例的多裸片封装结构700的剖面结构示意图；
图8示意性示出了根据本发明实施例的降压变换电路800的电路结构示意图；
图9示意性示出了根据本发明实施例的多裸片封装的方法流程图900。
具体实施方式
下面将详细描述本发明的具体实施例，应当注意，这里描述的实施例只用于举例说明，并不用于限制本发明。在以下描述中，为了提供对本发明的透彻理解，阐述了大量特定细节。然而，对于本领域普通技术人员显而易见的是：不必采用这些特定细节来实行本发明。在其他实例中，为了避免混淆本发明，未具体描述公知的电路、材料或方法。
在整个说明书中，对“一个实施例”、“实施例”、“一个示例”或“示例”的提及意味着：结合该实施例或示例描述的特定特征、结构或特性被包含在本发明至少一个实施例中。因此，在整个说明书的各个地方出现的短语“在一个实施例中”、“在实施例中”、“一个示例”或“示例”不一定都指同一实施例或示例。此外，可以以任何适当的组合和/或子组合将特定的特征、结构或特性组合在一个或多个实施例或示例中。此外，本领域普通技术人员应当理解，在此提供的附图都是为了说明的目的，并且附图不一定是按比例绘制的。应当理解，当称元件“耦接到”或“连接到”另一元件时，它可以是直接耦接或耦接到另一元件或者可以存在中间元件。相反，当称元件“直接耦接到”或“直接连接到”另一元件时，不存在中间元件。相同的附图标记指示相同的元件。这里使用的术语“和/或”包括一个或多个相关列出的项目的任何和所有组合。
图1为根据本发明实施例的多裸片封装结构100的剖面结构示意图。在图1所示实施例中，所述多裸片封装结构100包括：嵌入裸片101，被埋在基板110中；倒装裸片102，被放置在基板110的上方，并通过导体111(如焊料凸块、通孔结构、和/或金属线)与基板110电连接；贴合裸片103，被贴在倒装裸片102上方(如通过贴合胶121)，并通过键合线130与基板110电连接。
在本发明一个实施例中，所述嵌入裸片101包括其上形成有接触点(如焊料凸块)的有源面11T。该有源面通常也被称为上表面或顶面，与有源面相反的另一面通常被称为底面。
在本发明的实施例中，“倒装裸片”是指裸片的接触区通过焊料凸块直接与引线框架或基板连接的任意裸片；“基板”是指封装级别的材料制成的载板，应用于类似印制电路板PCB，包括多个金属层；“焊料凸块”是指用来直接电耦接两个接触区的球状或柱状金属小块(如铜柱)，该金属小块多以焊料填充；“贴合裸片”是指裸片通过封装级别的粘贴材料(如贴合胶121)被固定在封装结构的其他部分上。
在本发明一个实施例中，通过在裸片和基板上打过孔、并使用金属材料例如铜来填充过孔，以在裸片之间、裸片与基板之间、及裸片与外部接触之间形成金属线连接。
在本发明一个实施例中，所述嵌入裸片101的有源面11T可以朝下(朝向基板110，如图1所示)，也可以朝上(朝向倒装裸片102，如图2所示)。如图1所示，当嵌入裸片101的有源面11T朝下时，嵌入裸片101的有源面通过导体(如过孔结构)与基板110电连接。如图2所示，当嵌入裸片101的有源面11T朝上时，嵌入裸片101的有源面通过导体(如过孔结构和焊料凸块)112与倒装裸片102及基板110电连接。
在本发明一个实施例中，嵌入裸片101、倒装裸片102和贴合裸片103通过基板110的不同金属层引出，作为多裸片封装结构的外部引脚。
在本发明一个实施例中，导体112通过金属线和过孔结构，经由基板110的下表面被引出，以作为嵌入裸片101的输入输出端子。
在本发明一个实施例中，多裸片封装结构100还包括：塑封材料120，用以包封基板110的上方(如上表面)和下方(如下表面)，以保护倒装裸片102和贴合裸片103。在本发明一个实施例中，塑封材料120包括绝缘材料，如环氧树脂。
在本发明一个实施例中，嵌入裸片101的部分边缘与倒装裸片102的部分边缘在垂直方向(即如图1所示的Z方向)有交叠，使嵌入裸片101和倒装裸片102之间的导体有最小的垂直距离和更小的寄生阻抗。但是本领域技术人员应当意识到，在本发明的其他实施例中，嵌入裸片101与倒装裸片102、贴合裸片103在垂直方向也可以没有交叠，如图3所示实施例的多裸片封装结构300。
图3所示多裸片封装结构300与图1所示多裸片封装结构100相似，与图1所示多裸片封装结构100不同的是，在图3实施例中，嵌入裸片101与倒装裸片102在垂直方向没有交叠，嵌入裸片101与倒装裸片102之间的导体112包括焊料凸块11(垂直方向，与倒装裸片102接触的部分导体)、金属线12(平面方向)和过孔结构(或焊料凸块)13(垂直方向，与嵌入裸片101接触的部分导体)。图3所示多裸片封装结构300的其他部分与图1所示多裸片封装结构100相似，为叙述简明，这里不再详述。
也就是说，在本发明一部分实施例中，导体包括焊料凸块和过孔结构(如图2所示实施例中嵌入裸片101与倒装裸片102之间的导体)。在本发明另一部分实施例中，导体包括焊料凸块、过孔结构和金属线(如图3所示实施例中嵌入裸片101与倒装裸片102之间的导体)。在本发明其他实施例中，导体还可以包括焊料凸块和通孔结构/穿孔结构(如图1、2、3所示实施例中倒装裸片与基板之间的导体)。
在本发明一个实施例中，垂直方向为与裸片平面(如嵌入裸片101的有源面)垂直的方向。
前述根据本发明多个实施例的多裸片封装结构包括一个嵌入裸片、一个倒装裸片和一个贴合裸片。但是本领域技术人员应当意识到，本发明的多裸片封装结构可以包括一个或多个嵌入裸片、一个或多个倒装裸片和一个或多个贴合裸片，及其各种组合。如图4～图7实施例所示的多裸片封装结构400、500、600和700。这些实施例示出了多裸片封装结构包括两个嵌入裸片和/或两个倒装裸片和/或两个贴合裸片的组合，但是并未穷举其他组合，本领域技术人员应当意识到，在其他实施例中，多裸片封装结构可以包括任意个所需的嵌入裸片与任意个所需的贴合裸片、及任意个所需的倒装裸片的组合，且嵌入裸片的部分边缘与倒装裸片的部分边缘在垂直方向可以有交叠，也可以没有交叠。
在本发明一个实施例中，嵌入裸片101、倒装裸片102和贴合裸片103分别包括功率变换电路的功率开关器件和相应的控制器，如用于功率变换电路的主功率开关、从功率开关及其相应的控制器。例如，嵌入裸片101和倒装裸片102包括功率开关器件、贴合裸片103包括控制器；或嵌入裸片101包括控制器、倒装裸片102和贴合裸片103包括功率开关器件；或倒装裸片102包括控制器、嵌入裸片101和贴合裸片103包括功率开关器件。但是，本领域技术人员应当意识到，在本发明的其他实施例中，嵌入裸片101、倒装裸片102以及贴合裸片103可以包括其他电路和器件。
图8示意性示出了根据本发明实施例的降压变换电路800的电路结构示意图。在图8所示实施例中，所述降压变换电路800包括：多裸片封装芯片800C，该多裸片封装芯片800C具有：输入引脚Vin，接收输入电压，该输入引脚Vin电连接至其上形成有上端功率开关的第一裸片801；开关引脚SW，电连接至第一裸片801和其上形成有下端功率开关的第二裸片802；接地引脚GND，电连接至第二裸片802；控制引脚PWM，接收控制信号(如由前级电路输入)，所述控制引脚PWM电连接至其上形成有控制器的第三裸片803；其中：第一裸片801、第二裸片802和第三裸片803的其中一个裸片为嵌入裸片，被埋在基板中；另一个裸片为倒装裸片，被放置在基板上方；还有一个裸片为贴合裸片，被贴在倒装裸片的上方，并通过键合线与基板电连接。
在本发明一个实施例中，上端功率开关和下端功率开关由形成在第三裸片803上的控制器控制。
继续参考图8，第一裸片801具有电连接至输入引脚Vin的第一端子1、电连接至开关引脚SW的第二端子2以及电连接至第三裸片803的控制端子。第二裸片802包括电连接至开关引脚SW的第一端子3、电连接至接地引脚GND的第二端子4、以及电连接至第三裸片803的控制端子。第三裸片803包括电连接至控制引脚PWM的输入端子7、电连接至第一裸片801控制端子的第一输出端子5、以及电连接至第二裸片802控制端子的第二输出端子6。
在本发明一个实施例中，降压变换电路800进一步包括：电感和电容，电连接至多裸片封装芯片800C的开关引脚SW。
前述根据本发明多个实施例的多裸片封装结构为小尺寸封装提供了更紧凑的解决方案，带来了更好的性能。不同于传统技术，前述根据本发明多个实施例的多裸片封装结构可以采用不同的工艺来制作不同裸片(如倒装裸片用一种工艺、嵌入芯片用另一种工艺)，并将这些裸片封装在一起：一部分裸片(如嵌入裸片)被埋在基板里，另一部分裸片(如倒装裸片)被放置在基板上方、并通过导体(如焊料凸块)与基板电连接，还有部分裸片(如贴合裸片)被贴在倒装裸片上方、并通过键合线与基板电连接。因此，总成本被降低。此外，嵌入裸片与倒装裸片在垂直于裸片平面的方向有交叠，使得封装尺寸更小，这进一步节省了费用并减小了寄生阻抗。
图9示意性示出了根据本发明实施例的多裸片封装的方法流程图900。如图9所示，所述多裸片封装方法包括：
步骤901，将嵌入裸片埋入基板，所述基板具有多层金属层。
步骤902，将倒装裸片放置在基板上方。
步骤903，将贴合裸片贴在倒装裸片上方。
步骤904，通过导体电连接嵌入裸片、倒装裸片和基板，通过键合线电连接贴合裸片和基板。
在本发明一个实施例中，所述方法还包括：在基板底部预植焊球。
在本发明一个实施例中，所述方法还包括：用塑封材料包封基板的上方和底部，以保护倒装裸片、贴合裸片和焊球。
在本发明一个实施例中，所述方法还包括：将焊球从塑封材料包裹中研磨磨出或用激光烧出，并在露出的焊球区域再植焊球。
在本发明一个实施例中，所述嵌入裸片、倒装裸片和基板之间的导体包括焊料凸块或金属线。
在本发明一个实施例中，所述嵌入裸片、贴合裸片、倒装裸片通过不同的金属层引出，作为多裸片封装的外部引脚。
在本发明一个实施例中，所述嵌入裸片的部分边缘与倒装裸片的部分边缘在垂直方向有交叠。
虽然已参照几个典型实施例描述了本发明，但应当理解，所用的术语是说明和示例性、而非限制性的术语。由于本发明能够以多种形式具体实施而不脱离发明的精神或实质，所以应当理解，上述实施例不限于任何前述的细节，而应在随附权利要求所限定的精神和范围内广泛地解释，因此落入权利要求或其等效范围内的全部变化和改型都应为随附权利要求所涵盖。

Claims (10)

1.一种多裸片封装结构，包括：
嵌入裸片，被埋在基板中；
倒装裸片，被放置在基板的上方，通过导体与基板电连接；
贴合裸片，被贴在倒装裸片上方，通过键合线与基板电连接。
2.如权利要求1所述的多裸片封装结构，其中所述嵌入裸片、倒装裸片和贴合裸片通过基板的不同金属层引出，作为多裸片封装结构的外部引脚。
3.如权利要求1所述的多裸片封装结构，其中所述嵌入裸片的部分边缘与倒装裸片的部分边缘在垂直方向有交叠。
4.如权利要求1所述的多裸片封装结构，其中嵌入裸片具有有源面，该有源面朝向倒装裸片，并通过导体与基板、倒装裸片电连接。
5.如权利要求4所述的多裸片封装结构，其中所述电连接嵌入裸片与倒装裸片之间的导体包括焊料凸块、过孔结构和金属线。
6.一种多裸片封装芯片，包括：
输入引脚，接收输入电压，该输入引脚电连接至其上形成有上端功率开关的第一裸片；
开关引脚，电连接至第一裸片和其上形成有下端功率开关的第二裸片；
接地引脚，电连接至第二裸片；
控制引脚，接收控制信号，所述控制引脚电连接至其上形成有控制器的第三裸片；其中：
第一裸片、第二裸片和第三裸片的其中一个裸片为嵌入裸片，被埋在基板中；
另一个裸片为倒装裸片，被放置在基板上方；
还有一个裸片为贴合裸片，被贴在倒装裸片的上方，并通过键合线与基板电连接。
7.如权利要求6所述的多裸片封装芯片，其中所述嵌入裸片的部分边缘与倒装裸片的部分边缘在垂直方向有交叠。
8.一种多裸片封装的方法，包括：
将嵌入裸片埋入基板，所述基板具有多层金属层；
将倒装裸片放置在基板上方；
将贴合裸片贴在倒装裸片上方；
通过导体电连接嵌入裸片、倒装裸片和基板，通过键合线电连接贴合裸片和基板。
9.如权利要求8所述的多裸片封装的方法，其中所述嵌入裸片的部分边缘与倒装裸片的部分边缘在垂直方向有交叠。
10.如权利要求8所述的多裸片封装的方法，其中所述嵌入裸片、贴合裸片、倒装裸片通过不同的金属层引出，作为多裸片封装的外部引脚。
CN202011610872.1A 2020-12-30 2020-12-30 多裸片封装结构、芯片及方法 Pending CN112713126A (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN202011610872.1A CN112713126A (zh) 2020-12-30 2020-12-30 多裸片封装结构、芯片及方法
US17/545,229 US12002787B2 (en) 2020-12-30 2021-12-08 Multi-die package structure and multi-die co-packing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202011610872.1A CN112713126A (zh) 2020-12-30 2020-12-30 多裸片封装结构、芯片及方法

Publications (1)

Publication Number Publication Date
CN112713126A true CN112713126A (zh) 2021-04-27

Family

ID=75547223

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202011610872.1A Pending CN112713126A (zh) 2020-12-30 2020-12-30 多裸片封装结构、芯片及方法

Country Status (2)

Country Link
US (1) US12002787B2 (zh)
CN (1) CN112713126A (zh)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050211465A1 (en) * 2004-03-29 2005-09-29 Shinko Electric Industries Co., Ltd. Electronic parts packaging structure and method of manufacturing the same
CN102709282A (zh) * 2011-04-28 2012-10-03 成都芯源系统有限公司 多芯片封装结构、变换器模块及封装方法
CN104576517A (zh) * 2013-10-29 2015-04-29 新科金朋有限公司 平衡有虚设铜图案的嵌入pcb单元表面的半导体器件和方法
US20190279925A1 (en) * 2018-03-08 2019-09-12 Phoenix Pioneer Technology Co., Ltd. Semiconductor package structure and method of making the same

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7944048B2 (en) 2006-08-09 2011-05-17 Monolithic Power Systems, Inc. Chip scale package for power devices and method for making the same
US20100123215A1 (en) * 2008-11-20 2010-05-20 Qualcomm Incorporated Capacitor Die Design for Small Form Factors
US8891246B2 (en) * 2010-03-17 2014-11-18 Intel Corporation System-in-package using embedded-die coreless substrates, and processes of forming same
US8461669B2 (en) 2010-09-20 2013-06-11 Monolithic Power Systems, Inc. Integrated power converter package with die stacking
US8361899B2 (en) 2010-12-16 2013-01-29 Monolithic Power Systems, Inc. Microelectronic flip chip packages with solder wetting pads and associated methods of manufacturing
US8928305B2 (en) 2013-03-15 2015-01-06 Monolithic Power Systems, Inc. Reference compensation module and switching regulator circuit comprising the same
CN103151926B (zh) 2013-04-08 2015-12-09 成都芯源系统有限公司 负载调整补偿电路及开关型电压转换电路
CN103312200B (zh) 2013-06-28 2016-08-10 成都芯源系统有限公司 功率变换器、限流单元、控制电路及相关控制方法
KR102420125B1 (ko) * 2015-12-10 2022-07-13 삼성전자주식회사 반도체 패키지 및 이의 제조방법
KR102556052B1 (ko) 2015-12-23 2023-07-14 삼성전자주식회사 시스템 모듈과 이를 포함하는 모바일 컴퓨팅 장치
US11018124B2 (en) 2018-08-31 2021-05-25 Intel Corporation Embedded memory device and method for embedding memory device in a substrate
US11320883B2 (en) 2018-09-28 2022-05-03 Intel Corporation Multi-die stacks with power management
US11183487B2 (en) 2018-12-26 2021-11-23 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
CN112670253B (zh) 2020-12-23 2023-02-10 成都芯源系统有限公司 多裸片封装结构、芯片及方法
CN112736043B (zh) 2020-12-30 2022-09-06 成都芯源系统有限公司 多裸片封装模块及方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050211465A1 (en) * 2004-03-29 2005-09-29 Shinko Electric Industries Co., Ltd. Electronic parts packaging structure and method of manufacturing the same
CN102709282A (zh) * 2011-04-28 2012-10-03 成都芯源系统有限公司 多芯片封装结构、变换器模块及封装方法
CN104576517A (zh) * 2013-10-29 2015-04-29 新科金朋有限公司 平衡有虚设铜图案的嵌入pcb单元表面的半导体器件和方法
US20190279925A1 (en) * 2018-03-08 2019-09-12 Phoenix Pioneer Technology Co., Ltd. Semiconductor package structure and method of making the same

Also Published As

Publication number Publication date
US20220208731A1 (en) 2022-06-30
US12002787B2 (en) 2024-06-04

Similar Documents

Publication Publication Date Title
US6492726B1 (en) Chip scale packaging with multi-layer flip chip arrangement and ball grid array interconnection
CN112670253B (zh) 多裸片封装结构、芯片及方法
US6620648B2 (en) Multi-chip module with extension
US8951847B2 (en) Package leadframe for dual side assembly
EP3217429B1 (en) Semiconductor package assembly
KR100963471B1 (ko) 로직 및 메모리 집적 회로의 패키징 방법, 패키징된 집적회로 및 시스템
US20080157302A1 (en) Stacked-package quad flat null lead package
CN101971332A (zh) 包括嵌入倒装芯片的半导体管芯封装
US20090310322A1 (en) Semiconductor Package
CN102646663B (zh) 半导体封装件
US11257739B2 (en) Semiconductor package with integrated passive electrical component
US20180308788A1 (en) Semiconductor device with through-mold via
US10497678B2 (en) Semiconductor package assembly with passive device
US20040188818A1 (en) Multi-chips module package
KR100621547B1 (ko) 멀티칩 패키지
CN112736043B (zh) 多裸片封装模块及方法
US7888781B2 (en) Micro-layered lead frame semiconductor packages
CN114709204A (zh) 多裸片封装结构、芯片及方法
US9721928B1 (en) Integrated circuit package having two substrates
CN112713126A (zh) 多裸片封装结构、芯片及方法
US10937754B1 (en) Semiconductor package and manufacturing method thereof
US20110147910A1 (en) Method for stacking die in thin, small-outline package
KR100351922B1 (ko) 반도체 패키지 및 그의 제조 방법
KR20040059741A (ko) 반도체용 멀티 칩 모듈의 패키징 방법
CN112447690B (zh) 天线置顶的半导体封装结构

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20210427

WD01 Invention patent application deemed withdrawn after publication