TWI642157B - 半導體封裝件及其形成方法 - Google Patents

半導體封裝件及其形成方法 Download PDF

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Publication number
TWI642157B
TWI642157B TW106121285A TW106121285A TWI642157B TW I642157 B TWI642157 B TW I642157B TW 106121285 A TW106121285 A TW 106121285A TW 106121285 A TW106121285 A TW 106121285A TW I642157 B TWI642157 B TW I642157B
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Taiwan
Prior art keywords
pads
dielectric layer
forming
layer
die
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TW106121285A
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TW201814858A (zh
Inventor
吳集錫
葉德強
陳憲偉
陳潔
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台灣積體電路製造股份有限公司
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Abstract

一實施例係一種包含以下步驟之方法：在一第一晶圓中形成一第一被動裝置；在該第一晶圓之一第一側上方形成一第一介電層；在該第一介電層中形成第一複數個接墊；平坦化該第一介電層及該第一複數個接墊以使該第一介電層及該第一複數個接墊之頂表面彼此齊平；將一第一裝置晶粒混合接合至該第一介電層及該第一複數個接墊之至少一些者；及將該第一裝置晶粒囊封在一第一囊封物中。

Description

半導體封裝件及其形成方法
本發明實施例係有關半導體封裝件及其形成方法。
半導體業已歸因於各種電子組件(例如，電晶體、二極體、電阻器、電容器等等)之整合密度之不斷改良而經歷快速發展。在極大程度上，整合密度之改良起因於最小構件大小之反覆減小，此允許更多組件整合至一給定區域中。隨著對收縮電子裝置之需求增長，出現對半導體晶粒之更小且更具創造性封裝技術之一需求。此等封裝系統之一實例係堆疊封裝件(PoP)技術。在PoP裝置中，一頂部半導體封裝件堆疊於一底部半導體封裝件之頂部上以提供高位準之整合及組件密度。PoP技術大體上能夠產生具有增強功能性及一印刷電路板(PCB)上之小佔用面積之半導體裝置。
根據本發明一實施例，一種方法，其包括：在一第一晶圓中形成一第一被動裝置；在該第一晶圓之一第一側上方形成一第一介電層；在該第一介電層中形成第一複數個接墊；平坦化該第一介電層及該第一複數個接墊以使該第一介電層及該第一複數個接墊之頂表面彼此齊平；將一第一裝置晶粒混合接合至該第一介電層及該第一複數個接墊之至少一些者；及將該第一裝置晶粒囊封在一第一囊封物中。 根據本發明一實施例，一種方法，其包括：形成一第一封裝件，其包括：在一第一晶圓中形成一被動裝置及一貫穿通路；在該第一晶圓之一第一側上方形成一第一重佈結構，該第一重佈結構包括一第一介電層中之第一複數個接墊，該第一複數個接墊之頂表面與該第一介電層之一頂表面實質上共面；在該第一複數個接墊之一者上形成一第一電連接器；將一第一裝置晶粒接合至該第一重佈結構，該第一裝置晶粒之一介電層經接合至該第一介電層，且該第一裝置晶粒中之金屬墊透過金屬至金屬接合而接合至該第一複數個接墊；及將該第一裝置晶粒囊封在一第一模塑料中。 根據本發明一實施例，一種結構，其包括：一第一基板，其包括一第一被動裝置及一第一貫穿通路，該第一被動裝置嵌入該第一基板中，該第一貫穿通路延伸穿過該第一基板；一第一重佈結構，其在該第一基板上之一第一側上，該第一重佈結構包括：複數個金屬化圖案，其等包括第一複數個接墊；及第一複數個介電層，其中該複數個金屬化圖案定位在該第一複數個介電層中，且該第一複數個介電層包括一第一介電層，其中該第一介電層之一第一表面實質上與該第一複數個接墊之第一表面共面；及一裝置晶粒，其包括：第二複數個接墊，其等透過金屬至金屬接合而接合至該第一複數個接墊；及第二複數個介電層，其等包括一第二介電層，其中該第二介電層具有實質上與該第二複數個接墊之第二表面共面之一第二表面，其中該第一介電層透過介電質至介電質接合而接合至該第二介電層。
下列揭露提供用於實施本揭露之不同構件之許多不同實施例或實例。在下文描述組件及配置之特定實例以簡化本揭露。當然，此等僅為實例且不旨在為限制性。舉例而言，在下列描述中之一第一構件形成在一第二構件上方或上可包含其中該第一構件及該第二構件經形成直接接觸之實施例，且亦可包含其中額外構件可形成在該第一構件與該第二構件之間使得該第一構件及該第二構件可不直接接觸之實施例。另外，本揭露可在各種實例中重複元件符號及/或字母。此重複係出於簡單及清晰之目的且本身並不指示各種實施例及/或所論述組態之間的一關係。 此外，為便於描述，可在本文中使用諸如「在……下方」、「在……下」、「下」、「在……上」、「上」及類似物之空間相對術語以描述一個元件或特徵與另一(若干)元件或特徵之關係(如在圖中圖解說明)。空間相對術語旨在涵蓋除在圖中描繪之定向以外的在使用或操作中之裝置之不同定向。設備可經另外定向(旋轉90度或按其他定向)且因此可同樣解釋在本文中使用之空間相對描述符。 可在一特定內容脈絡(即，一封裝結構及形成包含實現更多功能性及可靠性之一整合扇出設計之封裝結構之方法)中論述本文中論述之實施例。封裝結構可包含混合接合至一晶圓結構之一晶片/晶粒，其中晶圓結構包含一或多個整合被動裝置(IPD)。形成封裝結構之一些所揭示方法包含方法之最佳化，其並不需要多達其他方法之載體基板。此外，混合接合製程允許晶片/晶粒與晶圓之間的接合不包含一銲料材料且因此可增大封裝結構之可靠性及良率。 此外，本揭露之教示可應用於包含一整合晶片/晶粒及/或整合被動裝置之任何封裝結構。其他實施例預期其他應用，諸如一般技術者在閱讀本揭露之後將容易明白之不同封裝類型或不同組態。應注意，本文中論述之實施例可不必圖解說明可存在於一結構中之每一組件或構件。舉例而言，諸如在組件之一者之論述足以傳達實施例之態樣時，可自一圖省略多個組件。此外，本文中論述之方法實施例可被論述為按一特定順序執行；然而，可按任何邏輯順序執行其他方法實施例。 圖1至圖13圖解說明根據一些實施例之用於形成一封裝結構之一製程期間之中間步驟之剖面視圖。在圖1中，圖解說明一晶圓20，其包含一基板22、貫穿通路24及被動裝置26。基板22可為一半導體基板，諸如一塊體基板、一絕緣體上半導體(SOI)基板或類似物，其等可經摻雜(例如，具有p型或n型摻雜劑)或未摻雜。基板22可為一晶圓，諸如一矽晶圓。一般言之，一SOI基板包括形成在一絕緣體層上之一半導體材料之一層。絕緣體層可為(例如)一埋入式氧化物(BOX)層、氧化矽層或類似物。在一基板(通常，一矽基板或玻璃基板)上提供絕緣體層。亦可使用其他基板，諸如多層基板或梯度基板。在一些實施例中，基板22之半導體材料可包含：矽；鍺；一化合物半導體，其包含碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦；一合金半導體，其包含SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP；或其等之組合。 在一些實施例中，除被動裝置26以外，基板22亦可包含主動裝置(未展示)。主動裝置可包括廣泛多種主動裝置，諸如電晶體及類似物，其等可用於產生設計之所要結構及功能零件。可使用任何合適方法在基板22內或基板22上形成主動裝置。 舉例而言，可藉由將開口蝕刻至基板22中且接著將一導電材料沉積至開口中而形成晶圓20之貫穿通路24。可在一相同製程中同時形成或在分開製程中形成用於貫穿通路24之此等開口。可使用一合適光微影遮罩及蝕刻製程形成至基板22中之開口。舉例而言，可在基板22上方形成且圖案化一光阻劑，且利用一或多個蝕刻製程(例如，一濕式蝕刻製程或一亁式蝕刻製程)以移除其中期望貫穿通路24之基板22之該等部分。 一旦已形成用於貫穿通路24之開口，便可使用(例如)襯層(諸如擴散阻障層、一黏著層或類似物)及一導電材料填充用於貫穿通路24之開口。襯層可包含鈦、氮化鈦、鉭、氮化鉭或類似物。可使用一化學氣相沉積(CVD)製程(諸如一電漿輔助CVD (PECVD))形成襯層。然而，可使用其他替代製程，諸如濺鍍或金屬有機化學氣相沉積(MOCVD)。 貫穿通路24之導電材料可包括一或多個導電材料、銅、銅合金、銀、金、鎢、鋁、鎳、其他導電金屬或類似物。舉例而言，可藉由沉積一晶種層(未展示)且使用電鍍、無電式電鍍或類似物將導電材料沉積至晶種層上，填充且過度填充用於貫穿通路24之開口而形成導電材料。一旦已填充用於貫穿通路24之開口，便可透過諸如光學機械拋光(CMP)之一研磨製程移除用於貫穿通路24之開路外部之過量襯層及過量導電材料，但是可使用任何合適移除製程。如一般技術者將認知，用於形成貫穿通路24之上文描述製程僅為形成貫穿通路24之一個方法，且其他方法亦完全旨在包含於實施例之範疇內。在此處理點及在一隨後處理點，貫穿通路24可不延伸穿過基板22，基板可經薄化以曝露穿過基板22之貫穿通路24 (見圖11)。 被動裝置26可被稱為整合被動裝置(IPD) 26。在一些實施例中，可藉由與貫穿通路24相同之製程在相同時間形成IPD 26。IPD 26可包括廣泛多種被動裝置，諸如電容器、電阻器、電感器、類似物或其等之一組合。 可使用任何合適方法在第一基板101內或第一基板101上形成IPD 26。舉例而言，可藉由首先將溝槽形成至基板22中而形成一深溝槽電容器。可藉由任何合適光微影遮罩及蝕刻製程形成溝槽。舉例而言，可在基板22上方形成且圖案化一光阻劑，且可利用一或多個蝕刻製程(例如，一亁蝕刻製程)以移除其中期望深溝槽電容器之基板22之該等部分。可藉由諸如透過一沉積製程或另一製程將一第一導電電極材料形成至一溝槽中而形成一第一電容器電極。第一導電電極材料可為一導電材料，諸如摻雜矽、多晶矽、銅、鎢、鋁或銅合金或另一導電材料。可在溝槽內之第一導電電極材料上方形成一介電層。介電層可包括高介電係數材料、氧化物、氮化物或類似物或其等之組合或多個層且使用諸如一CVD製程之任何合適沉積製程而形成。可在溝槽中介電層上方形成一第二導電電極材料以諸如透過一沉積製程或另一製程形成一第二電容器電極。第二導電電極材料可為一導電材料，諸如摻雜矽、多晶矽、銅、鎢、鋁或銅合金或另一導電材料。如一般技術者將認知，用於形成深溝槽電容器之上文描述製程僅為形成深溝槽電容器之一個方法，且其他方法亦完全旨在包含於實施例之範疇內。 在圖2及圖3中，在晶圓20、貫穿通路24及IPD 26上方形成一前側重佈結構28。前側重佈結構28包含介電層32及38、金屬化圖案30及接墊36。在一些實施例中，重佈結構28之形成開始於在晶圓20上方形成金屬化圖案30，接著形成介電層32及更多金屬化圖案30。在其他實施例中，首先在晶圓20上方形成一介電層32，接著形成金屬化圖案30及更多介電層32。在一些實施例中，一些金屬化圖案30可接觸貫穿通路24。在一些實施例中，一些金屬化圖案30可接觸IPD 26之部分。 作為形成金屬化圖案30之一實例，在晶圓20上方形成一晶種層(未展示)。在一些實施例中，晶種層係一金屬層，其可為一單層或包括由不同材料形成之複數個子層之一複合層。在一些實施例中，晶種層包括鈦層及鈦層上方之銅層。舉例而言，可使用PVD或類似物形成晶種層。接著，在晶種層上形成且圖案化一光阻劑。光阻劑可藉由旋轉塗佈或類似物形成且可曝露至光以供圖案化。光阻劑之圖案對應於金屬化圖案30。圖案化形成穿過光阻劑之開口以曝露晶種層。在光阻劑之開口中且在晶種層之曝露部分上形成一導電材料。可藉由諸如電鍍或無電式電鍍之鍍覆或類似物形成導電材料。導電材料可包括一金屬，如銅、鈦、鎢、鋁或類似物。接著，移除光阻劑及其上未形成導電材料之晶種層之部分。可藉由一可接受灰化或剝離製程(諸如使用氧電漿或類似物)移除光阻劑。一旦移除光阻劑，便移除晶種層之曝露部分(諸如藉由使用一可接受蝕刻製程，諸如藉由濕蝕刻或乾蝕刻)。晶種層之其餘部分及導電材料形成金屬化圖案30。 介電層32之一者係金屬化圖案30。在一些實施例中，介電層32及38由一聚合物形成，其可為一光敏材料，諸如可使用一微影遮罩圖案化之聚苯並㗁唑(PBO)、聚酰亞胺、苯並環丁烯(BCB)或類似物。在其他實施例中，介電層32及38由以下形成：氮化物，諸如氮化矽；氧化物，諸如氧化矽、磷酸玻璃(PSG)、硼矽玻璃(BSG)、硼摻雜磷矽玻璃(BPSG)；或類似物。可藉由旋轉塗佈、層壓、CVD、類似物或其等之一組合形成介電層32。 接著，圖案化介電層32。圖案化形成開口以曝露下伏金屬化圖案之部分。圖案化可藉由一可接受製程進行，諸如藉由在介電層132係一光敏材料時將介電層132曝露至光或藉由使用例如一非等向性蝕刻來蝕刻。若介電層32係一光敏材料，則介電層32可在曝露之後顯影。 接著，可重複形成金屬化圖案30及介電層32以形成具有適當數目個層之重佈結構28。在形成適當數目個層30及32之後，包含接墊36之最頂部金屬化圖案36在層32及30上方形成且與至少一些金屬化圖案30電接觸。 作為形成包含接墊36之最頂部金屬化圖案36之一實例，在最頂層32上方形成一晶種層(未展示)。在一些實施例中，晶種層係一金屬層，其可為一單層或包括由不同材料形成之複數個子層之一複合層。在一些實施例中，晶種層包括鈦層及鈦層上方之銅層。舉例而言，可使用PVD或類似物形成晶種層。接著，在晶種層上形成且圖案化一光阻劑。光阻劑可藉由旋轉塗佈或類似物形成且可曝露至光以供圖案化。光阻劑之圖案對應於金屬化圖案36。圖案化形成穿過光阻劑之開口以曝露晶種層。在光阻劑之開口中且在晶種層之曝露部分上形成一導電材料。可藉由諸如電鍍或無電式電鍍之鍍覆或類似物形成導電材料。導電材料可包括一金屬，如銅、鈦、鎢、鋁或類似物。接著，移除光阻劑及其上未形成導電材料之晶種層之部分。可藉由一可接受灰化或剝離製程(諸如使用氧電漿或類似物)移除光阻劑。一旦移除光阻劑，便移除晶種層之曝露部分(諸如藉由使用一可接受蝕刻製程，諸如藉由濕蝕刻或乾蝕刻)。晶種層之其餘部分及導電材料形成包含接墊36之金屬化圖案36。一些金屬化圖案36將用於形成貫穿通路40 (見圖4)且不被視為接墊36。 在一些實施例中，形成最頂部介電層38以覆蓋接墊36。在此等實施例中，執行諸如一研磨或CMP之一平坦化步驟以移除最頂部介電層38之過量部分且提供接墊36與最頂部介電層38之共面表面。 在其他實施例中，在一雙鑲嵌製程中形成重佈結構28，雙鑲嵌製程包含：沉積介電層32及38 (其等可形成為單層或藉由一蝕刻停止層分開之兩個層)；在介電層中形成溝槽及通路開口以曝露金屬化圖案30之一些部分；及使用導電材料填充溝槽及通路開口以形成更多金屬化圖案30及/或接墊36。接著，執行一CMP以移除過量導電材料。因此，填充介電層32及38中之溝槽之導電材料之部分分別變為金屬化圖案30及接墊36，而填充通路開口之導電材料之部分變為通路。 在圖4中，在重佈結構28上方形成貫穿通路40。作為形成貫穿通路40之一實例，在重佈結構28 (例如，如圖解說明之介電層38及金屬化圖案36之曝露部分)上方形成一晶種層。在一些實施例中，晶種層係一金屬層，其可為一單層或包括由不同材料形成之複數個子層之一複合層。在一些實施例中，晶種層包括鈦層及鈦層上方之銅層。舉例而言，可使用PVD或類似物形成晶種層。在晶種層上形成且圖案化一光阻劑。光阻劑可藉由旋轉塗佈或類似物形成且可曝露至光以供圖案化。光阻劑之圖案對應於貫穿通路。圖案化形成穿過光阻劑之開口以曝露晶種層。在光阻劑之開口中且在晶種層之曝露部分上形成一導電材料。可藉由諸如電鍍或無電式電鍍之鍍覆或類似物形成導電材料。導電材料可包括一金屬，如銅、鈦、鎢、鋁或類似物。移除光阻劑及其上未形成導電材料之晶種層之部分。可藉由一可接受灰化或剝離製程(諸如使用氧電漿或類似物)移除光阻劑。一旦移除光阻劑，便移除晶種層之曝露部分(諸如藉由使用一可接受蝕刻製程，諸如藉由濕蝕刻或乾蝕刻)。晶種層之其餘部分及導電材料形成貫穿通路40。 在圖5中，將積體電路晶粒42接合至重佈結構28之介電層38及接墊36。積體電路晶粒42可為邏輯晶粒(例如，中央處理單元、微控制器等等)、記憶體晶粒(例如，動態隨機存取記憶體(DRAM)晶粒、靜態隨機存取記憶體(SRAM)晶粒等等)、功率管理晶粒(例如，功率管理積體電路(PMIC)晶粒)、射頻(RF)晶粒、感測器晶粒、微機電系統(MEMS)晶粒、訊號處理晶粒(例如，數位訊號處理(DSP)晶粒)、前端晶粒(例如，類比前端(AFE)晶粒)、類似物或其等之一組合。又，在一些實施例中，積體電路晶粒42可為不同大小(例如，不同高度及/或表面積)，且在其他實施例中，積體電路晶粒42可為相同大小(例如，相同高度及/或表面積)。 在接合至重佈結構28之前，可根據可適用製造製程處理積體電路晶粒42以在積體電路晶粒42中形成積體電路。舉例而言，積體電路晶粒42各包含一半導體基板43 (諸如摻雜或未摻雜矽)或一絕緣體上半導體(SOI)基板之一主動層。半導體基板43可包含其他半導體材料，諸如鍺；一化合物半導體，其包含碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦；一合金半導體，其包含SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP；或其等之組合。亦可使用其他基板，諸如多層基板或梯度基板。諸如電晶體、二極體、電容器、電阻器等等之裝置可在半導體基板43中及/或上形成且可藉由由(例如)半導體基板43上之一或多個介電層中之金屬化圖案形成之互連結構44互連以形成一積體電路。 積體電路晶粒42進一步包括墊(未展示)，諸如互連結構44上之鋁墊，製成至該墊之外部連接。墊在可被稱為積體電路晶粒42之各自主動側上。諸如導電柱(例如，包括諸如銅之一金屬)之晶粒連接器46 (可被稱為接墊46)經機械且電耦合至各自墊。舉例而言，可藉由鍍覆或類似物形成晶粒連接器46。晶粒連接器46電耦合積體電路晶粒42之各自積體電路。積體電路晶粒42可經單粒化(諸如藉由鋸切或切割)且藉由使用(例如)一取置工具放置至介電層108上。 一介電材料48在積體電路晶粒42之主動側上，諸如在晶粒連接器46上。介電材料48橫向囊封晶粒連接器46，且介電材料48與各自積體電路晶粒42橫向相連。介電材料48可為：一聚合物，諸如PBO、聚醯亞胺、BCB或類似物；氮化物，諸如氮化矽或類似物；氧化物，諸如氧化矽、PSG、BSG、BPSG或類似物；類似物或其等之一組合且可藉由(例如)旋轉塗佈、層壓、CVD或類似物而形成。 透過混合接合將積體電路晶粒42接合至介電層38及接墊36。為達成混合接合，首先藉由抵靠介電層38及接墊36輕微按壓積體電路晶粒42而將積體電路晶粒42預接合至介電層38及接墊36。儘管圖解說明四個積體電路晶粒42，但可在晶圓級執行混合接合，其中相同於圖解說明之積體電路晶粒42之複數個積體電路晶粒經預接合且配置成列及行。 在預接合所有積體電路晶粒42之後，執行一退火以導致接墊36及晶粒接墊46中之金屬相互擴散。根據本揭露之一些實施例，介電層38及48之一者或兩者包括一聚合物。因此，退火溫度降低至低於約250°C，以便避免聚合物之損壞。舉例而言，退火溫度(在存在聚合物之情況下)可在約200°C與約250°C之間的範圍中。退火時間可在約2小時與3小時之間。當兩個介電層38及48皆由諸如氧化物或氮氧化物之無機介電材料形成時，退火溫度可更高，其低於約400°C。舉例而言，退火溫度(在不存在聚合物之情況下)可在約300°C與約400°C之間的範圍中，且退火時間可在約1.5小時與約2.5小時之間的範圍中。 透過混合接合，透過由金屬相互擴散引起之直接金屬接合將接墊36及46接合至彼此。接墊36及46可具有可區別介面。介電層38亦接合至介電層48 且在其等之間形成接合。舉例而言，介電層38及48之一者中之原子(諸如氧原子)與介電層38及48之另一者中之原子(諸如氫原子)形成化學或共價鍵(諸如O-H鍵)。介電層38與48之間的所得接合係介電質至介電質接合，其可為根據各種實施例之無機至聚合物、聚合物至聚合物或無機至無機接合。此外，兩個積體電路晶粒42之表面介電層48可彼此不同(例如，一個介電層係一聚合物層且另一介電層係一無機層)，且因此兩種類型之無機至聚合物、聚合物至聚合物及無機至無機接合可同時存在於相同封裝件中。 在圖6及圖7中，在各種組件上形成一囊封物58。囊封物58可為一模塑料、環氧樹脂或類似物且可藉由壓縮成型、轉移成型或類似物來施加。囊封物58之頂表面高於貫穿通路40之頂端及積體電路晶粒42之背側表面。使囊封物58固化。根據其他實施例，囊封物58可由包含氧化物(諸如氧化矽或氮氧化矽)或氮化物(諸如氮化矽)之一無機介電材料形成。根據此等實施例之囊封物58之形成方法可包含CVD。 在圖8中，執行諸如一CMP步驟或一研磨步驟之一平坦化以薄化囊封物58直至曝露貫穿通路40 (若存在)。貫穿通路40及囊封物58之頂表面在平坦化製程之後共面。在一些實施例中，舉例而言，若貫穿通路40已透過囊封物58曝露，則可省略平坦化製程。儘管未展示，但在一些實施例中，平坦化製程可曝露積體電路晶粒42之背側表面。 在圖9中，形成一背側重佈結構60。如將在圖9中圖解說明，背側重佈結構60包含一或多個介電層62及金屬化圖案64。在囊封物58及貫穿通路40上沉積一第一介電層62。在一些實施例中，介電層62由一聚合物形成，其可為一光敏材料，諸如可使用一微影遮罩圖案化之PBO、聚酰亞胺、BCB或類似物。在其他實施例中，介電層62由以下形成：氮化物，諸如氮化矽；氧化物，諸如氧化矽、PSG、BSG、BPSG；或類似物。可藉由旋轉塗佈、層壓、CVD、類似物或其等之一組合形成介電層62。 接著，圖案化第一介電層62。圖案化形成開口以曝露貫穿通路40之部分。圖案化可藉由一可接受製程進行，諸如藉由在介電層62係一光敏材料時將介電層62曝露至光或藉由使用例如一非等向性蝕刻來蝕刻。若介電層62係一光敏材料，則介電層62可在曝露之後顯影。 接著，在第一介電層62上形成具有通路之金屬化圖案64。作為形成金屬化圖案64之一實例，在第一介電層62上方且在穿過第一介電層62之開口中形成一晶種層(未展示)。在一些實施例中，晶種層係一金屬層，其可為一單層或包括由不同材料形成之複數個子層之一複合層。在一些實施例中，晶種層包括鈦層及鈦層上方之銅層。舉例而言，可使用PVD或類似物形成晶種層。接著，在晶種層上形成且圖案化一光阻劑。光阻劑可藉由旋轉塗佈或類似物形成且可曝露至光以供圖案化。光阻劑之圖案對應於金屬化圖案64。圖案化形成穿過光阻劑之開口以曝露晶種層。在光阻劑之開口中且在晶種層之曝露部分上形成一導電材料。可藉由諸如電鍍或無電式電鍍之鍍覆或類似物形成導電材料。導電材料可包括一金屬，如銅、鈦、鎢、鋁或類似物。接著，移除光阻劑及其上未形成導電材料之晶種層之部分。可藉由一可接受灰化或剝離製程(諸如使用氧電漿或類似物)移除光阻劑。一旦移除光阻劑，便移除晶種層之曝露部分(諸如藉由使用一可接受蝕刻製程，諸如藉由濕蝕刻或乾蝕刻)。晶種層之其餘部分及導電材料形成金屬化圖案64及通路。通路在穿過第一介電層62之開口中形成至(例如)貫穿通路40。 接著，在金屬化圖案64及第一介電層62上沉積一第二介電層62。在一些實施例中，第二介電層62由一聚合物形成，其可為一光敏材料，諸如可使用一微影遮罩圖案化之PBO、聚酰亞胺、BCB或類似物。在其他實施例中，第二介電層62由以下形成：氮化物，諸如氮化矽；氧化物，諸如氧化矽、PSG、BSG、BPSG；或類似物。可藉由旋轉塗佈、層壓、CVD、類似物或其等之一組合形成第二介電層62。 接著，圖案化第二介電層62。圖案化形成開口以曝露金屬化圖案64之部分。圖案化可藉由一可接受製程進行，諸如藉由在介電層140係一光敏材料時將介電層140曝露至光或藉由使用(例如)一非等向性蝕刻來蝕刻。若第二介電層62係一光敏材料，則第二介電層62可在曝露之後顯影。 背側重佈結構60經展示為一實例。可在背側重佈結構60中形成更多或更少介電層及金屬化圖案。若待形成較少介電層及金屬化圖案，則可省略上文論述之步驟及製程。若待形成更多介電層及金屬化圖案，則可重複上文論述之步驟及製程。一般技術者將容易地理解將省略或重複哪些步驟及製程。 在圖9中圖解說明之結構可被稱為一或多個第一封裝件100，在一些實施例中，其等可在一隨後處理時間經單粒化。 在圖10中，將一或多個第二封裝件110接合至圖9之一或多個第一封裝件100。第二封裝件110之各者包含一基板70及耦合至基板70之一或多個晶粒74。基板70可由諸如矽、鍺、鑽石或類似物之一半導體材料製成。在一些實施例中，亦可使用化合物材料，諸如矽鍺、碳化矽、砷化鎵、砷化銦、磷化銦、碳化矽鍺、磷化鎵砷、磷化鎵銦、此等之組合及類似物。另外，基板70可為一絕緣體上矽(SOI)基板。一般言之，一SOI基板包含一半導體材料之一層，諸如磊晶矽、鍺、矽鍺、SOI、絕緣體上矽鍺(SGOI)或其等之組合。在一項替代實施例中，基板70係基於一絕緣核心，諸如一玻璃纖維加強樹脂核心。一個例示性核心材料係諸如FR4之玻璃纖維樹脂。用於核心材料之替代品包含雙馬來酰亞胺三嗪(BT)樹脂或替代性地其他印刷電路板(PCB)材料或膜。諸如Ajinomoto堆積膜(ABF)之堆積膜或其他層壓材料可用於基板70。 基板70可包含主動裝置及被動裝置(未展示)。如一般技術者將認識到，諸如電晶體、電容器、電阻器、此等之組合及類似物之廣泛多種裝置可用於產生封裝設計之結構及功能要求。可使用任何合適方法形成裝置。 基板70亦可包含金屬化層72及貫穿通路(未展示)。金屬化層72可在主動裝置及被動裝置上方形成且經設計以連接各種裝置以形成功能電路。金屬化層可由介電材料(例如，一低介電係數材料)與導電材料(例如，銅) (具有使導電材料層互連之通路)之交替層形成且可透過任何合適製程(諸如沉積、鑲嵌、雙鑲嵌或類似物)而形成。在一些實施例中，基板70實質上不具有主動裝置及被動裝置。 基板70在基板70之一第一側上可具有接墊(未展示)以耦合至晶粒74且在基板70之一第二側(基板70之第二側與第一側相對)上具有接墊71以耦合至導電連接器78。在一些實施例中，藉由將凹槽(未展示)形成至基板70之第一側及第二側上之介電層(未展示)中而形成接墊。可形成凹槽以允許接墊嵌入至介電層中。在其他實施例中，由於可在介電層上形成接墊，故省略凹槽。在一些實施例中，接墊包含由銅、鈦、鎳、金、鈀、類似物或其等之一組合製成之一薄晶種層(未展示)。可在薄晶種層上方沉積接墊之導電材料。可藉由一電化學鍍覆製程、一無電式電鍍製程、CVD、ALD、PVD、類似物或其等之一組合形成導電材料。在一實施例中，接墊303及304之導電材料係銅、鎢、鋁、銀、金、類似物或其等之一組合。 在一實施例中，接墊係包含三個導電材料層(諸如鈦層、銅層及鎳層)之UBM。然而，一般技術者將認知，存在適用於UBM之形成之材料及層之許多合適配置，諸如鉻/鉻銅合金/銅/金之一配置、鈦/鈦鎢/銅之一配置或銅/鎳/金之一配置。可用於UBM之任何合適材料或材料層完全旨在包含於當前申請案之範疇內。在一些實施例中，貫穿通路延伸穿過基板70且將基板70之第一側上之至少一個接墊耦合至基板之第二側上之至少一個接墊71。 可藉由導線接合或導電凸塊將晶粒74耦合至基板70。在一實施例中，晶粒74係堆疊記憶體晶粒。舉例而言，堆疊記憶體晶粒74可包含低功率(LP)雙資料速率(DDR)記憶體模組，諸如LPDDR1、LPDDR2、LPDDR3、LPDDR4或類似記憶體模組。 在一些實施例中，可藉由一模塑料76囊封晶粒74及導線接合(若存在)。舉例而言，可使用壓縮成型使模塑料76在晶粒74上成型。在一些實施例中，模塑料76係一模塑料、一聚合物、一環氧樹脂、氧化矽填充物材料、類似物或其等之一組合。可執行一固化步驟以使模塑料76固化，其中固化可為一熱固化、一UV固化、類似物或其等之一組合。 在一些實施例中，將晶粒74及導線接合(若存在)埋入模塑料76中，且在模塑料76之固化之後，執行諸如一研磨之一平坦化步驟以移除模塑料76之過量部分且提供用於第二封裝件110之一實質上平坦表面。 在形成第二封裝件110之後，藉由導電連接器78、接墊71及金屬化圖案64將第二封裝件110接合至第一封裝件100。 導電連接器78可為BGA連接器、焊球、金屬柱、受控塌陷晶片連接(C4)凸塊、微凸塊、無電鎳-無電鈀-沉浸金技術(ENEPIG)形成之凸塊或類似物。導電連接器78可包含一導電材料，諸如銲料、銅、鋁、金、鎳、銀、鈀、錫、類似物或其等之一組合。在一些實施例中，藉由首先透過諸如蒸鍍、電鍍、印刷、銲料轉印、植球或類似物之此等常用方法形成一銲料層而形成導電連接器78。一旦已在結構上形成一銲料層，便可執行一回銲，以便將材料塑形為所要凸塊形狀。在另一實施例中，導電連接器78係藉由一濺鍍、印刷、電鍍、無電式電鍍、CVD或類似物形成之金屬柱(諸如一銅柱)。金屬柱可不具有銲料且具有實質上垂直側壁。在一些實施例中，在金屬柱連接器78之頂部上形成一金屬罩蓋層(未展示)。金屬罩蓋層可包含鎳、錫、錫鉛、金、銀、鈀、銦、鎳鈀金、鎳金、類似物或其等之一組合且可藉由一鍍覆製程形成。 在一些實施例中，在接合導電連接器78之前，導電連接器78經塗佈有一助焊劑(未展示)，諸如一免清潔助焊劑。可將導電連接器78浸泡於助焊劑中或可將助焊劑噴射至導電連接器78上。在另一實施例中，可將助焊劑施加至金屬化圖案64之表面。 在一些實施例中，在使用在第二封裝件110附接至第一封裝件100之後剩餘之環氧樹脂助焊劑之至少一些環氧樹脂部分回銲導電連接器78之前，導電連接器78可在其上形成有一環氧樹脂助焊劑(未展示)。此剩餘環氧樹脂部分可充當一底膠填充以減小應力且保護源自回銲導電連接器78之接頭。在一些實施例中，一底膠填充80可形成在第二封裝件110與第一封裝件100之間且圍繞導電連接器78。可在附接第二封裝件110之後藉由一毛細流動製程形成底膠填充或可在附接第二封裝件110之前藉由一合適沉積方法形成底膠填充。 第二封裝件110與第一封裝件100之間的接合可為一銲料接合或一直接金屬至金屬(諸如一銅至銅或錫至錫)接合。在一實施例中，藉由一回銲製程將第二封裝件110接合至第一封裝件100。在此回銲製程期間，導電連接器78與接墊71及金屬化圖案64接觸以將第二封裝件110實體地且電耦合至第一封裝件100。在接合製程之後，一IMC (未展示)可形成在金屬化圖案64與導電連接器78之介面處形成且亦形成在導電連接器78與接墊71之間的介面處。 在圖11中，包含一或多個第一封裝件100及一或多個第二封裝件110之結構經翻轉且放置在一膠帶82上。此外，晶圓20可經受一研磨製程以曝露貫穿通路24。貫穿通路24及晶圓20之表面在研磨製程之後共面。在一些實施例中，舉例而言，若貫穿通路24已透過晶圓20曝露，則可省略研磨。 在曝露貫穿通路24之後，在貫穿通路24上方形成墊84及導電連接器86。在貫穿通路24之曝露表面上形成墊84。墊84用於耦合至導電連接器86且可被稱為凸塊下冶金(UBM) 84。作為形成墊84之一實例，在晶圓20之表面上方形成一晶種層(未展示)。在一些實施例中，晶種層係一金屬層，其可為一單層或包括由不同材料形成之複數個子層之一複合層。在一些實施例中，晶種層包括鈦層及鈦層上方之銅層。舉例而言，可使用PVD或類似物形成晶種層。接著，在晶種層上形成且圖案化一光阻劑。光阻劑可藉由旋轉塗佈或類似物形成且可曝露至光以供圖案化。光阻劑之圖案對應於墊84。圖案化形成穿過光阻劑之開口以曝露晶種層。在光阻劑之開口中且在晶種層之曝露部分上形成一導電材料。可藉由諸如電鍍或無電式電鍍之鍍覆或類似物形成導電材料。導電材料可包括一金屬，如銅、鈦、鎢、鋁或類似物。接著，移除光阻劑及其上未形成導電材料之晶種層之部分。可藉由一可接受灰化或剝離製程(諸如使用氧電漿或類似物)移除光阻劑。一旦移除光阻劑，便移除晶種層之曝露部分(諸如藉由使用一可接受蝕刻製程，諸如藉由濕蝕刻或乾蝕刻)。晶種層之剩餘部分及導電材料形成墊84。在實施例中，在不同地形成墊84之情況下，可利用更多光阻劑及圖案化步驟。 在UBM 84上形成導電連接器86。導電連接器86可為BGA連接器、焊球、金屬柱、C4凸塊、微凸塊、ENEPIG形成之凸塊或類似物。導電連接器86可包含一導電材料，諸如銲料、銅、鋁、金、鎳、銀、鈀、錫、類似物或其等之一組合。在一些實施例中，藉由首先透過諸如蒸鍍、電鍍、印刷、銲料轉印、植球或類似物之此等常用方法形成一銲料層而形成導電連接器86。一旦已在結構上形成一銲料層，便可執行一回銲，以便將材料塑形為所要凸塊形狀。在另一實施例中，導電連接器86係藉由一濺鍍、印刷、電鍍、無電式電鍍、CVD或類似物形成之金屬柱(諸如一銅柱)。金屬柱可不具有銲料且具有實質上垂直側壁。在一些實施例中，在金屬柱連接器86之頂部上形成一金屬罩蓋層(未展示)。金屬罩蓋層可包含鎳、錫、錫鉛、金、銀、鈀、銦、鎳鈀金、鎳金、類似物或其等之一組合且可藉由一鍍覆製程形成。 在圖12中，包含一或多個第一封裝件100及一或多個第二封裝件110之結構經翻轉且放置在一膠帶88上。此外，藉由沿著(例如)第二封裝件110與第一封裝件100之間的切割道區域鋸切90而執行單粒化製程。 圖13圖解說明一所得單粒化封裝件，其包含一第一封裝件100及一第二封裝件110。此外，可將包含封裝件100及110之封裝件安裝至一基板112。基板112可被稱為一封裝基板112。使用導電連接器86將封裝件100安裝至封裝基板112。 封裝基板112可由諸如矽、鍺、鑽石或類似物之一半導體材料製成。替代性地，亦可使用化合物材料，諸如矽鍺、碳化矽、砷化鎵、砷化銦、磷化銦、碳化矽鍺、磷化鎵砷、磷化鎵銦、此等之組合及類似物。另外，封裝基板112可為一SOI基板。一般言之，一SOI基板包含一半導體材料層，諸如磊晶矽、鍺、矽鍺、SOI、SGOI或其等之組合。在一項替代實施例中，封裝基板112係基於一絕緣核心，諸如一玻璃纖維加強樹脂核心。一個例示性核心材料係諸如FR4之玻璃纖維樹脂。用於核心材料之替代品包含雙馬來酰亞胺三嗪BT樹脂或替代性地其他PCB材料或膜。諸如ABF之堆積膜或其他層壓材料可用於封裝基板112。 封裝基板112可包含主動裝置及被動裝置(未展示)。如一般技術者將認知，諸如電晶體、電容器、電阻器、此等之組合及類似物之廣泛多種裝置可用於產生半導體封裝件設計之結構及功能要求。可使用任何合適方法形成裝置。 封裝基板112亦可包含金屬化層及通路以及金屬化層及通路上方之接墊(未展示)。金屬化層可形成在主動裝置及被動裝置上方且經設計以連接各種裝置以形成功能電路。金屬化層可由介電材料(例如，低k介電係數材料)與導電材料(例如，銅) (具有使導電材料層互連之通路)之交替層形成且可透過任何合適製程(諸如沉積、鑲嵌、雙鑲嵌或類似物)而形成。在一些實施例中，封裝基板112實質上不具有主動裝置及被動裝置。 在一些實施例中，導電連接器86可經回銲以將封裝件100及110附接至基板112。導電連接器86將基板112 (包含基板112中之金屬化層)電及/或實體耦合至第一封裝件100。 在使用在封裝件110及100附接至基板112之後剩餘之環氧樹脂助焊劑之至少一些環氧樹脂部分回銲導電連接器86之前，導電連接器86可在其上形成有一環氧樹脂助焊劑(未展示)。此剩餘環氧樹脂部分可充當一底膠填充以減小應力且保護源自回銲導電連接器86之接頭。在一些實施例中，一底膠填充(未展示)可形成在第一封裝件100與基板112之間且圍繞導電連接器86。可在附接封裝件110及100之後藉由一毛細流動製程形成底膠填充或可在附接封裝件110及100之前藉由一合適沉積方法形成底膠填充。 圖14圖解說明根據一些實施例之包含穿過一晶圓之開口之一封裝結構之一剖面視圖。此實施例類似於圖1至圖13之先前實施例，惟在此實施例中，晶圓20具有經形成穿過其之開口(其中代替貫穿通路24在開口中形成電連接器114)。類似於先前描述之實施例之細節之關於此實施例之細節將不在本文中重複。 在圖14中，晶圓20可具有經形成穿過其之開口以允許導電連接器86電耦合至前側重佈結構28。舉例而言，可藉由使用雷射鑽孔、蝕刻或類似物使開口形成穿過晶圓20。可恰在形成導電連接器86之前形成開口(例如，見先前實施例之圖11)或可在製程中更早地形成開口。 當結構類似於在圖11中展示般在一膠帶上翻轉時，可在穿過晶圓20之開口中形成電連接器114。作為形成電連接器114之一實例，在晶圓20上方且在開口中形成一晶種層(未展示)。在一些實施例中，晶種層係一金屬層，其可為一單層或包括由不同材料形成之複數個子層之一複合層。在一些實施例中，晶種層包括鈦層及鈦層上方之銅層。舉例而言，可使用PVD或類似物形成晶種層。接著，在晶種層上形成且圖案化一光阻劑。光阻劑可藉由旋轉塗佈或類似物形成且可曝露至光以供圖案化。光阻劑之圖案對應於電連接器114。圖案化形成穿過光阻劑之開口以曝露晶種層。在光阻劑之開口中且在晶種層之曝露部分上形成一導電材料。可藉由諸如電鍍或無電式電鍍之鍍覆或類似物形成導電材料。導電材料可包括一金屬，如銅、鈦、鎢、鋁或類似物。接著，移除光阻劑及其上未形成導電材料之晶種層之部分。可藉由一可接受灰化或剝離製程(諸如使用氧電漿或類似物)移除光阻劑。一旦移除光阻劑，便移除晶種層之曝露部分(諸如藉由使用一可接受蝕刻製程，諸如藉由濕蝕刻或乾蝕刻)。晶種層之剩餘部分及導電材料形成電連接器114。 在形成電連接器114之後，可在電連接器114上形成導電連接器86。在一些實施例中，導電連接器86與電連接器114之間存在UBM。 圖15圖解說明根據一些實施例之包含一單一積體電路晶粒42之一封裝結構之一剖面視圖。此實施例類似於圖1至圖13之先前實施例，惟在此實施例中，封裝結構包含一單一積體電路晶粒42而非多個積體電路晶粒42。類似於先前描述之實施例之細節之關於此實施例之細節將不在本文中重複。 圖16至圖23圖解說明根據一些實施例之用於形成一封裝結構之一製程期間之中間步驟之剖面視圖。此實施例類似於圖15之先前實施例，惟在此實施例中，第二封裝件110已用一整合扇出(InFO)封裝結構160替代。類似於先前描述之實施例之細節之關於此實施例之細節將不在本文中重複。 圖16至圖23圖解說明在圖15之第二封裝件160上方形成第一封裝件130之中間步驟之剖面視圖。在此等圖中，僅圖解說明一個第一封裝件130，但可在多個第二封裝件160上方同時形成多個第一封裝件130且接著結構可經單粒化以形成多個封裝結構。圖16圖解說明重佈結構60中之開口以曝露金屬化圖案64之部分。 在圖17中，形成貫穿通路136。作為形成貫穿通路136之一實例，在重佈結構60上方且在開口中形成一晶種層。在一些實施例中，晶種層係一金屬層，其可為一單層或包括由不同材料形成之複數個子層之一複合層。在一些實施例中，晶種層包括鈦層及鈦層上方之銅層。舉例而言，可使用PVD或類似物形成晶種層。在晶種層上形成且圖案化一光阻劑。光阻劑可藉由旋轉塗佈或類似物形成且可曝露至光以供圖案化。光阻劑之圖案對應於貫穿通路。圖案化形成穿過光阻劑之開口以曝露晶種層。在光阻劑之開口中且在晶種層之曝露部分上形成一導電材料。可藉由諸如電鍍或無電式電鍍之鍍覆或類似物形成導電材料。導電材料可包括一金屬，如銅、鈦、鎢、鋁或類似物。移除光阻劑及其上未形成導電材料之晶種層之部分。可藉由一可接受灰化或剝離製程(諸如使用氧電漿或類似物)移除光阻劑。一旦移除光阻劑，便移除晶種層之曝露部分(諸如藉由使用一可接受蝕刻製程，諸如藉由濕蝕刻或乾蝕刻)。晶種層之剩餘部分及導電材料形成貫穿通路136。 在圖18中，藉由一黏著劑(未展示)將積體電路晶粒138附接至重佈結構60。如在圖18中圖解說明，附接兩個積體電路晶粒138，且在其他實施例中，可針對各封裝結構附接更多或更少積體電路晶粒138。積體電路晶粒138可為邏輯晶粒(例如，中央處理單元、微控制器等等)、記憶體晶粒(例如，DRAM晶粒、SRAM晶粒等等)、功率管理晶粒(例如，PMIC晶粒)、RF晶粒、感測器晶粒、MEMS晶粒、訊號處理晶粒(例如，DSP晶粒)、前端晶粒(例如，AFE晶粒)、類似物或其等之一組合。又，在一些實施例中，積體電路晶粒138可為不同大小(例如，不同高度及/或表面積)，且在其他實施例中，積體電路晶粒138可為相同大小(例如，相同高度及/或表面積)。 在黏著之前，可根據可適用製造製程處理積體電路晶粒138以在積體電路晶粒138中形成積體電路。舉例而言，積體電路晶粒138各包含一半導體基板139 (諸如摻雜或未摻雜矽)或一絕緣體上半導體(SOI)基板之一主動層。半導體基板139可包含其他半導體材料，諸如鍺；一化合物半導體，其包含碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦；一合金半導體，其包含SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP；或其等之組合。亦可使用其他基板，諸如多層基板或梯度基板。諸如電晶體、二極體、電容器、電阻器等等之裝置可在半導體基板139中及/或上形成且可藉由由(例如)半導體基板139上之一或多個介電層中之金屬化圖案形成之互連結構120互連以形成一積體電路。 積體電路晶粒138進一步包括墊，諸如鋁墊，製成至該墊之外部連接。墊在可被稱為積體電路晶粒138之各自主動側上。諸如導電柱(例如，包括諸如銅之一金屬)之晶粒連接器142經機械且電耦合至各自墊。舉例而言，可藉由鍍覆或類似物形成晶粒連接器142。晶粒連接器142電耦合積體電路晶粒138之各自積體電路。 一介電材料144在積體電路晶粒138之主動側上，諸如在晶粒連接器142上。介電材料144橫向囊封晶粒連接器142，且介電材料144與各自積體電路晶粒138橫向相連。介電材料144可為：一聚合物，諸如PBO、聚醯亞胺、BCB或類似物；氮化物，諸如氮化矽或類似物；氧化物，諸如氧化矽、PSG、BSG、BPSG或類似物；類似物或其等之一組合且可藉由(例如)旋轉塗佈、層壓、CVD或類似物而形成。 黏著層(未展示)可在積體電路晶粒138之背側上且將積體電路晶粒138黏著至第一封裝件130。黏著劑可為任何合適黏著劑、環氧樹脂、晶粒附接薄膜(DAF)或類似物。可將黏著劑施加至積體電路晶粒138之一背側(諸如至各自半導體晶圓之一背側)或可施加在第一封裝件130之表面上方。積體電路晶粒138可經單粒化(諸如藉由鋸切或切割)且使用(例如)一取置工具藉由黏著劑黏著至第一封裝件130。 在圖19中，在各種組件上形成一囊封物146。囊封物146可為一模塑料、環氧樹脂或類似物且可藉由壓縮成型、轉移成型或類似物來施加。 在圖20中，在固化之後，囊封物146可經受一研磨製程以曝露貫穿通路136及晶粒連接器142。貫穿通路136、晶粒連接器142及囊封物146之頂表面在研磨製程之後共面。在一些實施例中，舉例而言，若已曝露貫穿通路136及晶粒連接器142，則可省略研磨。 在圖21中，形成一前側重佈結構148。如在圖21中圖解說明，前側重佈結構148包含介電層152及耦合至貫穿通路136及晶粒連接器142之金屬化圖案150。可類似於上文描述之重佈結構60般形成重佈結構148且不在本文中重複描述。在形成重佈結構148之後，形成第二封裝件160。 前側重佈結構148經展示為一實例。可在前側重佈結構148中形成更多或更少介電層及金屬化圖案。若待形成較少介電層及金屬化圖案，則可省略上文論述之步驟及製程。若待形成更多介電層及金屬化圖案，則可重複上文論述之步驟及製程。一般技術者將容易地理解將省略或重複哪些步驟及製程。 在圖22中，包含一或多個第一封裝件130及一或多個第二封裝件160之結構經翻轉且放置在一膠帶162上。此外，晶圓20可經受一研磨製程以曝露貫穿通路24。貫穿通路24及晶圓20之表面在研磨製程之後共面。在一些實施例中，舉例而言，若貫穿通路24已透過晶圓20曝露，則可省略研磨。在曝露貫穿通路24之後，在貫穿通路24上方形成墊(未展示)及導電連接器86。 在一些實施例中，包含一或多個第一封裝件130及一或多個第二封裝件160之結構經翻轉且放置在一膠帶82上以進行一單粒化製程。 圖23圖解說明一所得單粒化封裝件，其包含一第一封裝件130及一第二封裝件160。此外，可將包含封裝件130及160之封裝件安裝至一基板112。基板112可被稱為一封裝基板112。使用導電連接器86將封裝件130安裝至封裝基板112。 本文中論述之實施例可達成優勢。特定言之，所揭示實施例包含實現更多功能性及可靠性之一整合扇出設計。封裝結構可包含混合接合至一晶圓結構之一晶片/晶粒，其中晶圓結構包含一或多個整合被動裝置(IPD)。形成封裝結構之一些所揭示方法包含方法之最佳化，其並不需要多達其他方法之載體基板(或在一些情況中，無載體基板)。此外，混合接合製程允許晶片/晶粒與晶圓之間的接合不包含一銲料材料且因此可增大封裝結構之可靠性及良率。 一實施例係一種包含以下步驟之方法：在一第一晶圓中形成一第一被動裝置；在該第一晶圓之一第一側上方形成一第一介電層；在該第一介電層中形成第一複數個接墊；平坦化該第一介電層及該第一複數個接墊以使第一介電層及該第一複數個接墊之頂表面彼此齊平；將一第一裝置晶粒混合接合至該第一介電層及該第一複數個接墊之至少一些者；及將該第一裝置晶粒囊封在一第一囊封物中。 另一實施例係一種包含形成一第一封裝件之方法，其包含：在一第一晶圓中形成一被動裝置及一貫穿通路；在該第一晶圓之一第一側上方形成一第一重佈結構，該第一重佈結構包含一第一介電層中之第一複數個接墊，該第一複數個接墊之頂表面實質上與該第一介電層之一頂表面共面；在該第一複數個接墊之一者上形成一第一電連接器；將一第一裝置晶粒接合至該第一重佈結構，將該第一裝置晶粒之一介電層接合至該第一介電層，且透過金屬至金屬接合將該第一裝置晶粒中之金屬墊接合至該第一複數個接墊；及將該第一裝置晶粒囊封在一第一模塑料中。 一進一步實施例係一種包含以下各者之結構：一第一晶圓，其包含一第一被動裝置及一第一貫穿通路，該第一被動裝置嵌入該第一晶圓中，該第一貫穿通路延伸穿過該第一晶圓；一第一重佈結構，其在該第一晶圓上之一第一側上，該第一重佈結構包含包括第一複數個接墊之複數個金屬化圖案及第一複數個介電層，其中該複數個金屬化圖案定位在該第一複數個介電層中，且該第一複數個介電層包括一第一介電層，其中該第一介電層之一第一表面實質上與該第一複數個接墊之第一表面共面；及一裝置晶粒，其包含透過金屬至金屬接合而接合至該第一複數個接墊之第二複數個接墊及包含一第二介電層之第二複數個介電層，其中該第二介電層具有實質上與該第二複數個接墊之第二表面共面之一第二表面，其中該第一介電層透過介電質至介電質接合而接合至該第二介電層。 前述內容概括若干實施例之特徵，使得熟習此項技術者可更好理解本揭露之態樣。熟習此項技術者應瞭解，其等可容易地使用本揭露作為設計或修改用於執行相同目的之其他製程及結構及/或達成本文中介紹之實施例之相同優勢之一基礎。熟習此項技術者亦應認識到，此等等效構造未脫離本揭露之精神及範疇，且其等可在不脫離本揭露之精神及範疇之情況下在本文中作出各種改變、替代及更改。
20‧‧‧晶圓
22‧‧‧基板
24‧‧‧貫穿通路
26‧‧‧被動裝置/整合被動裝置(IPD)
28‧‧‧重佈結構
30‧‧‧金屬化圖案
32‧‧‧介電層
36‧‧‧接墊
38‧‧‧介電層
40‧‧‧貫穿通路
42‧‧‧積體電路晶粒
43‧‧‧半導體基板
44‧‧‧互連結構
46‧‧‧晶粒連接器/晶粒接墊
48‧‧‧介電材料
58‧‧‧囊封物
60‧‧‧背側重佈結構
62‧‧‧介電層
64‧‧‧金屬化圖案
70‧‧‧基板
71‧‧‧接墊
72‧‧‧金屬化層
74‧‧‧晶粒
76‧‧‧模塑料
78‧‧‧導電連接器
80‧‧‧底膠填充
82‧‧‧膠帶
84‧‧‧墊
86‧‧‧導電連接器
88‧‧‧膠帶
90‧‧‧鋸切
100‧‧‧第一封裝件
110‧‧‧第二封裝件
112‧‧‧基板
114‧‧‧電連接器
120‧‧‧互連結構
130‧‧‧第一封裝件
136‧‧‧貫穿通路
138‧‧‧積體電路晶粒
139‧‧‧半導體基板
140‧‧‧介電層
142‧‧‧晶粒連接器
144‧‧‧介電材料
146‧‧‧囊封物
148‧‧‧重佈結構
150‧‧‧金屬化圖案
152‧‧‧介電層
160‧‧‧第二封裝件
162‧‧‧膠帶
當結合隨附圖式閱讀時自下列實施方式更好理解本揭露之態樣。應強調，根據業界中之標準實踐，各種構件不按比例繪製。實際上，為清晰論述，各種構件之尺寸可任意增大或減小。 圖1至圖13圖解說明根據一些實施例之用於形成一封裝結構之一製程期間之中間步驟之剖面視圖。 圖14圖解說明根據一些實施例之包含穿過一晶圓之開口之一封裝結構之一剖面視圖。 圖15圖解說明根據一些實施例之包含一單一積體電路晶粒之一封裝結構之一剖面視圖。 圖16至圖23圖解說明根據一些實施例之用於形成一封裝結構之一製程期間之中間步驟之剖面視圖。

Claims (10)

  1. 一種半導體封裝件的形成方法，其包括：在一第一晶圓中形成一第一被動裝置；在該第一晶圓之一第一側上方形成一第一介電層；在該第一介電層中形成第一複數個接墊；平坦化該第一介電層及該第一複數個接墊以使該第一介電層及該第一複數個接墊之頂表面彼此齊平；將一第一裝置晶粒混合接合至該第一介電層及該第一複數個接墊之至少一些者；及將該第一裝置晶粒囊封在一第一囊封物中。
  2. 如請求項1之形成方法，其進一步包括：在該第一複數個接墊之一者上形成一第一貫穿通路，該第一貫穿通路經囊封在該第一囊封物中。
  3. 如請求項2之形成方法，其中在該第一複數個接墊之一者上形成該第一貫穿通路包括：在該囊封之後，在該第一複數個接墊之該一者上鍍覆該貫穿通路。
  4. 如請求項2之形成方法，其進一步包括：在該第一裝置晶粒、該第一貫穿通路及該第一囊封物上方形成一第二介電層；在該第二介電層中形成第二複數個接墊，該第二複數個接墊之至少一者電耦合至該第一貫穿通路；將一封裝結構接合至該第二複數個接墊；在該第二介電層中形成第一複數個接墊，該第一複數個接墊之至少一者電耦合至該第一貫穿通路；在該第一複數個接墊之一者上形成一第三貫穿通路；在該第二介電層上方黏著一第二裝置晶粒；將該第二裝置晶粒及該第三貫穿通路囊封在一第二囊封物中；在該第二裝置晶粒、該第三貫穿通路及該第二囊封物上方形成一第三介電層；及在該第三介電層中形成一第一金屬化圖案，該第一金屬化圖案電耦合至該第三貫穿通路及該第二裝置晶粒。
  5. 如請求項1之形成方法，其進一步包括：形成自該第一側延伸至該第一晶圓中之一第二貫穿通路。
  6. 一種半導體封裝件的形成方法，其包括：形成一第一封裝件，其包括：在一第一晶圓中形成一被動裝置及一貫穿通路；在該第一晶圓之一第一側上方形成一第一重佈結構，該第一重佈結構包括一第一介電層中之第一複數個接墊，該第一複數個接墊之頂表面與該第一介電層之一頂表面實質上共面；在該第一複數個接墊之一者上形成一第一電連接器；將一第一裝置晶粒接合至該第一重佈結構，該第一裝置晶粒之一介電層經接合至該第一介電層，且該第一裝置晶粒中之金屬墊透過金屬至金屬接合而接合至該第一複數個接墊；及將該第一裝置晶粒囊封在一第一模塑料中。
  7. 如請求項6之形成方法，其進一步包括：在該第一裝置晶粒、該第一模塑料及該第一電連接器上方形成一第二重佈結構，該第二重佈結構包括一第二介電層中之第二複數個接墊；及使用一第一組導電連接器將一第二封裝件接合至該第一封裝件。
  8. 如請求項6之形成方法，其進一步包括：在該第一裝置晶粒、該第一模塑料及該第一電連接器上方形成一第二重佈結構，該第二重佈結構包括一第二介電層中之金屬化圖案；在該等金屬化圖案之一者上形成一第二電連接器；將一第二裝置晶粒黏著至該第二重佈結構；及將該第二裝置晶粒及該第二電連接器囊封在一第二模塑料中。
  9. 如請求項8之形成方法，其進一步包括：在該第二裝置晶粒、該第二模塑料及該第二電連接器上方形成一第三重佈結構，該第三重佈結構包括一第三介電層中之金屬化圖案，該等金屬化圖案電耦合至該第二電連接器及該第二裝置晶粒。
  10. 一種半導體封裝件的結構，其包括：一第一基板，其包括一第一被動裝置及一第一貫穿通路，該第一被動裝置嵌入該第一基板中，該第一貫穿通路延伸穿過該第一基板；一第一重佈結構，其在該第一基板上之一第一側上，該第一重佈結構包括：複數個金屬化圖案，其等包括第一複數個接墊；及第一複數個介電層，其中該複數個金屬化圖案定位在該第一複數個介電層中，且該第一複數個介電層包括一第一介電層，其中該第一介電層之一第一表面實質上與該第一複數個接墊之第一表面共面；及一裝置晶粒，其包括：第二複數個接墊，其等透過金屬至金屬接合而接合至該第一複數個接墊；及第二複數個介電層，其等包括一第二介電層，其中該第二介電層具有實質上與該第二複數個接墊之第二表面共面之一第二表面，其中該第一介電層透過介電質至介電質接合而接合至該第二介電層。
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Families Citing this family (49)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102566996B1 (ko) * 2016-09-09 2023-08-14 삼성전자주식회사 FOWLP 형태의 반도체 패키지 및 이를 가지는 PoP 형태의 반도체 패키지
US9768133B1 (en) * 2016-09-22 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method of forming the same
US10784247B2 (en) * 2017-11-15 2020-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Process control for package formation
DE102018124695A1 (de) * 2017-11-15 2019-05-16 Taiwan Semiconductor Manufacturing Co., Ltd. Integrieren von Passivvorrichtungen in Package-Strukturen
US10770364B2 (en) 2018-04-12 2020-09-08 Xilinx, Inc. Chip scale package (CSP) including shim die
US10361122B1 (en) * 2018-04-20 2019-07-23 Taiwan Semiconductor Manufacturing Company, Ltd. Processes for reducing leakage and improving adhesion
US10811404B2 (en) * 2018-05-31 2020-10-20 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of manufacturing the same
TWI659515B (zh) * 2018-07-26 2019-05-11 欣興電子股份有限公司 封裝結構及其製造方法
US11296044B2 (en) 2018-08-29 2022-04-05 Invensas Bonding Technologies, Inc. Bond enhancement structure in microelectronics for trapping contaminants during direct-bonding processes
KR102536269B1 (ko) 2018-09-14 2023-05-25 삼성전자주식회사 반도체 패키지 및 그 제조 방법
KR102538181B1 (ko) 2018-10-24 2023-06-01 삼성전자주식회사 반도체 패키지
KR102583127B1 (ko) 2018-10-30 2023-09-26 삼성전자주식회사 다이스택 구조물과 이를 구비하는 반도체 패키지
US11211334B2 (en) * 2018-11-18 2021-12-28 iCometrue Company Ltd. Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip
US10867929B2 (en) 2018-12-05 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structures and methods of forming the same
CN109485010A (zh) * 2018-12-06 2019-03-19 中芯长电半导体（江阴）有限公司 Mems封装结构、晶圆级mems封装结构及其制备方法
CN113228234A (zh) * 2019-03-04 2021-08-06 桑迪士克科技有限责任公司 具有包括支撑管芯的接合结构的三维器件及其制备方法
US11024702B2 (en) * 2019-03-04 2021-06-01 Cyntec Co., Ltd. Stacked electronic structure
KR102596759B1 (ko) 2019-03-18 2023-11-02 삼성전자주식회사 반도체 패키지
US11139249B2 (en) 2019-04-01 2021-10-05 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods of forming the same
US10818640B1 (en) 2019-04-02 2020-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Die stacks and methods forming same
KR102584960B1 (ko) * 2019-04-12 2023-10-05 삼성전기주식회사 반도체 패키지
US11562982B2 (en) * 2019-04-29 2023-01-24 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit packages and methods of forming the same
US10950519B2 (en) * 2019-05-31 2021-03-16 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
DE102019125790B4 (de) * 2019-05-31 2022-04-21 Taiwan Semiconductor Manufacturing Co., Ltd. Integriertes schaltkreis-package und verfahren
US11024605B2 (en) 2019-05-31 2021-06-01 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US11296053B2 (en) 2019-06-26 2022-04-05 Invensas Bonding Technologies, Inc. Direct bonded stack structures for increased reliability and improved yield in microelectronics
US11862587B2 (en) 2019-07-25 2024-01-02 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method of manufacturing the same
US11837575B2 (en) * 2019-08-26 2023-12-05 Taiwan Semiconductor Manufacturing Company, Ltd. Bonding passive devices on active device dies to form 3D packages
US11264343B2 (en) * 2019-08-30 2022-03-01 Taiwan Semiconductor Manufacturing Co., Ltd. Bond pad structure for semiconductor device and method of forming same
US11018113B2 (en) * 2019-10-17 2021-05-25 Taiwan Semiconductor Manufacturing Company, Ltd. Memory module, semiconductor package including the same, and manufacturing method thereof
US11282816B2 (en) 2020-01-17 2022-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Memory packages and methods of forming same
US11502024B2 (en) 2020-01-21 2022-11-15 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
US11211362B2 (en) * 2020-03-20 2021-12-28 Taiwan Semiconductor Manufacturing Company, Ltd. 3D trench capacitor for integrated passive devices
CN113725088B (zh) * 2020-03-27 2024-02-27 矽磐微电子(重庆)有限公司 芯片封装结构的制作方法
US11495472B2 (en) * 2020-04-16 2022-11-08 Taiwan Semiconductor Manufacturing Co., Ltd. Semicondutor packages and methods of forming same
DE102020128855A1 (de) * 2020-05-21 2021-11-25 Taiwan Semiconductor Manufacturing Co., Ltd. Chiplets-3d-soic-systemintegrations- und herstellungsverfahren
US11532524B2 (en) * 2020-07-27 2022-12-20 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit test method and structure thereof
US11670614B2 (en) * 2020-10-02 2023-06-06 Qualcomm Incorporated Integrated circuit assembly with hybrid bonding
CN114388487A (zh) * 2020-10-16 2022-04-22 虹晶科技股份有限公司 封装结构及该封装结构的制备方法
US11784172B2 (en) 2021-02-12 2023-10-10 Taiwan Semiconductor Manufacturing Hsinchu, Co., Ltd. Deep partition power delivery with deep trench capacitor
US11961809B2 (en) * 2021-02-26 2024-04-16 Taiwan Semiconductor Manufacturing Co., Ltd. Antenna apparatus and method
TWI775352B (zh) * 2021-03-19 2022-08-21 力晶積成電子製造股份有限公司 半導體封裝及其製造方法
US12021064B2 (en) * 2021-05-03 2024-06-25 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices and methods of manufacture
US11855057B2 (en) * 2021-07-08 2023-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of forming the same
US20230060520A1 (en) * 2021-08-27 2023-03-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and semiconductor device
KR20230059653A (ko) * 2021-10-26 2023-05-03 에스케이하이닉스 주식회사 반도체 장치 제조 방법
US20230207522A1 (en) * 2021-12-24 2023-06-29 Intel Corporation Reconstituted wafer-to-wafer hybrid bonding interconnect architecture with known good dies
CN114975415A (zh) * 2022-04-29 2022-08-30 盛合晶微半导体(江阴)有限公司 扇出堆叠型半导体封装结构及其封装方法
CN114823592B (zh) 2022-06-30 2022-11-11 之江实验室 一种晶上系统结构及其制备方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050253241A1 (en) * 2003-03-18 2005-11-17 Hall Frank L Semiconductor device assemblies including an encapsulant located over intermediate conductive elements and filling a space between a semiconductor die and a carrier of the assembly
TW200709360A (en) * 2005-06-30 2007-03-01 Fairchild Semiconductor Semiconductor die package and method for making the same
US8822268B1 (en) * 2013-07-17 2014-09-02 Freescale Semiconductor, Inc. Redistributed chip packages containing multiple components and methods for the fabrication thereof
TW201440186A (zh) * 2013-01-29 2014-10-16 Apple Inc 堆疊式晶圓雙倍資料率封裝

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SG130055A1 (en) 2005-08-19 2007-03-20 Micron Technology Inc Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices
US8975729B2 (en) * 2012-01-13 2015-03-10 Qualcomm Incorporated Integrating through substrate vias into middle-of-line layers of integrated circuits
US9252076B2 (en) 2013-08-07 2016-02-02 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
CN104576417B (zh) * 2013-10-23 2017-12-01 中芯国际集成电路制造(上海)有限公司 封装结构和封装方法
US9412662B2 (en) * 2014-01-28 2016-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and approach to prevent thin wafer crack
CN104009014B (zh) * 2014-04-26 2017-04-12 华进半导体封装先导技术研发中心有限公司 集成无源器件晶圆级封装三维堆叠结构及制作方法
US9543170B2 (en) 2014-08-22 2017-01-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of forming the same
US9633974B2 (en) * 2015-03-04 2017-04-25 Apple Inc. System in package fan out stacking architecture and process flow
US9659907B2 (en) * 2015-04-07 2017-05-23 Apple Inc. Double side mounting memory integration in thin low warpage fanout package
US9768133B1 (en) * 2016-09-22 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method of forming the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050253241A1 (en) * 2003-03-18 2005-11-17 Hall Frank L Semiconductor device assemblies including an encapsulant located over intermediate conductive elements and filling a space between a semiconductor die and a carrier of the assembly
TW200709360A (en) * 2005-06-30 2007-03-01 Fairchild Semiconductor Semiconductor die package and method for making the same
TW201440186A (zh) * 2013-01-29 2014-10-16 Apple Inc 堆疊式晶圓雙倍資料率封裝
US8822268B1 (en) * 2013-07-17 2014-09-02 Freescale Semiconductor, Inc. Redistributed chip packages containing multiple components and methods for the fabrication thereof

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