TWI775352B - 半導體封裝及其製造方法 - Google Patents

半導體封裝及其製造方法 Download PDF

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TWI775352B
TWI775352B TW110109889A TW110109889A TWI775352B TW I775352 B TWI775352 B TW I775352B TW 110109889 A TW110109889 A TW 110109889A TW 110109889 A TW110109889 A TW 110109889A TW I775352 B TWI775352 B TW I775352B
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Taiwan
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semiconductor package
disposed
pads
redistribution layer
stack structure
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TW110109889A
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English (en)
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TW202238906A (zh
Inventor
梁義忠
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力晶積成電子製造股份有限公司
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Priority to TW110109889A priority Critical patent/TWI775352B/zh
Priority to US17/319,119 priority patent/US11545469B2/en
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Publication of TWI775352B publication Critical patent/TWI775352B/zh
Publication of TW202238906A publication Critical patent/TW202238906A/zh

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Abstract

一種半導體封裝，包括晶片堆疊結構、重佈線層結構與多個導電插塞。晶片堆疊結構包括堆疊的多個晶片。每個晶片包括接墊。多個晶片上的多個接墊位在晶片堆疊結構的同一側。重佈線層結構設置在晶片堆疊結構的第一側壁上，且鄰近於接墊。導電插塞貫穿重佈線層結構。導電插塞連接至對應的接墊。

Description

半導體封裝及其製造方法
本發明是有關於一種半導體封裝及其製造方法，且特別是有關於一種具有晶片堆疊結構的半導體封裝及其製造方法。
在目前的晶片堆疊封裝(chip stacking package)的製程中，為了便於進行晶片之間的電性連接，會對每個晶片的基底進行薄化製程(thinning process)，因此常會在每個晶片的基底中產生裂痕(crack)，而導致良率降低。此外，在目前的晶片堆疊封裝中，會使用貫穿晶片的基底的矽穿孔(through-silicon via，TSV)來進行晶片之間的電性連接。然而，用以形成上述矽穿孔的蝕刻製程也可能會在晶片的基底中產生裂痕，而導致良率降低。因此，目前的晶片堆疊封裝具有製程複雜且良率低的問題。
本發明提供一種半導體封裝及其製造方法，其可降低製程複雜度並提升良率。
本發明提出一種半導體封裝，包括晶片堆疊結構、重佈線層(redistribution layer，RDL)結構與多個導電插塞。晶片堆疊結構包括堆疊的多個晶片。每個晶片包括接墊。多個晶片上的多個接墊位在晶片堆疊結構的同一側。重佈線層結構設置在晶片堆疊結構的第一側壁上，且鄰近於接墊。導電插塞貫穿重佈線層結構。導電插塞連接至對應的接墊。
依照本發明的一實施例所述，在上述半導體封裝中，重佈線層結構的延伸方向可平行於多個晶片的堆疊方向。
依照本發明的一實施例所述，在上述半導體封裝中，每個晶片可包括多個接墊。同一個晶片上的多個接墊可位在同一個晶片的同一側。
依照本發明的一實施例所述，在上述半導體封裝中，每個晶片更可包括基底與半導體元件。基底可具有相對的第一面與第二面。接墊設置在第一面上。半導體元件設置在第一面上，且電性連接至接墊。
依照本發明的一實施例所述，在上述半導體封裝中，每個晶片更可包括介電層與內連線結構。介電層設置在第一面上，且覆蓋半導體元件。內連線結構設置在介電層中。半導體元件與接墊可藉由內連線結構而彼此電性連接。
依照本發明的一實施例所述，在上述半導體封裝中，每個晶片更可包括封環(seal ring)。封環可環繞半導體元件與接墊。導電插塞可貫穿封環。
依照本發明的一實施例所述，在上述半導體封裝中，重佈線層結構的延伸方向可垂直於第一面。導電插塞的延伸方向可平行於第一面。
依照本發明的一實施例所述，在上述半導體封裝中，晶片堆疊結構更可包括黏著劑。黏著劑設置在相鄰兩個晶片之間。
依照本發明的一實施例所述，在上述半導體封裝中，重佈線層結構可包括基底與重佈線層。基底設置在晶片堆疊結構的第一側壁上。重佈線層設置在基底上，且位在基底的遠離晶片堆疊結構的一側。重佈線層可包括介電層與重佈線路(redistribution circuit)。介電層設置在基底上。重佈線路設置在介電層中，且可電性連接至導電插塞。
依照本發明的一實施例所述，在上述半導體封裝中，重佈線層結構更可包括偵錯電路(error detecting circuit)。偵錯電路設置在介電層中，且電性連接至重佈線路。
依照本發明的一實施例所述，在上述半導體封裝中，更包括黏著劑。黏著劑設置在重佈線層結構與晶片堆疊結構的第一側壁之間。
依照本發明的一實施例所述，在上述半導體封裝中，更可包括載板。載板設置在晶片堆疊結構的第二側壁上。第二側壁可相對於第一側壁。
依照本發明的一實施例所述，在上述半導體封裝中，更可包括黏著劑。黏著劑設置在載板與晶片堆疊結構的第二側壁之間。
依照本發明的一實施例所述，在上述半導體封裝中，更可包括包封體(encapsulant)。包封體圍繞晶片堆疊結構。
本發明提出一種半導體封裝的製造方法，包括以下步驟。提供晶片堆疊結構。晶片堆疊結構具有相對的第一側壁與第二側壁。晶片堆疊結構包括堆疊的多個晶片。每個晶片包括接墊。多個晶片上的多個接墊位在晶片堆疊結構的同一側。將晶片堆疊結構的第二側壁放置在載板上。將重佈線層結構放置在晶片堆疊結構的第一側壁上。重佈線層結構鄰近於接墊。形成貫穿重佈線層結構的多個導電插塞。導電插塞連接至對應的接墊。
依照本發明的一實施例所述，在上述半導體封裝的製造方法中，晶片堆疊結構更可包括黏著劑。黏著劑設置在相鄰兩個晶片之間。
依照本發明的一實施例所述，在上述半導體封裝的製造方法中，更包括以下步驟。提供黏著劑至晶片堆疊結構的第二側壁與載板之間。
依照本發明的一實施例所述，在上述半導體封裝的製造方法中，更包括以下步驟。提供黏著劑至重佈線層結構與晶片堆疊結構的第一側壁之間。
依照本發明的一實施例所述，在上述半導體封裝的製造方法中，更包括以下步驟。形成圍繞晶片堆疊結構的包封體。
依照本發明的一實施例所述，在上述半導體封裝的製造方法中，導電插塞的形成方法可包括以下步驟。在重佈線層結構與晶片中形成開口。開口貫穿重佈線層結構，且暴露出對應的接墊。在重佈線層結構上形成填入開口的導體層。移除開口外部的導體層。
基於上述，在本發明所提出的半導體封裝及其製造方法中，多個晶片上的多個接墊位在晶片堆疊結構的同一側，重佈線層結構設置在晶片堆疊結構的第一側壁上且鄰近於接墊，且導電插塞貫穿重佈線層結構且連接至對應的接墊。因此，可藉由導電插塞與重佈線層結構進行晶片之間的電性連接。此外，在本發明所提出的半導體封裝及其製造方法中，由於可藉由導電插塞與重佈線層結構進行晶片之間的電性連接，因此可以不對每個晶片的基底進行薄化製程，進而可防止在晶片的基底中產生裂痕。另外，在本發明所提出的半導體封裝及其製造方法中，由於可藉由導電插塞與重佈線層結構進行晶片之間的電性連接，因此無須形成穿過晶片的基底且用於進行晶片之間的電性連接的導電插塞，藉此可防止在晶片的基底中產生裂痕。因此，本發明所提出的半導體封裝及其製造方法可降低製程複雜度並提升良率。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
圖1A至圖1E為本發明一實施例的半導體封裝的製造流程剖面圖。圖2為圖1A中的晶片的立體示意圖。在圖1A中，簡化圖2中的部分構件(如，內連線結構112)，以清楚地描述圖1A中的構件之間的配置關係。
請參照圖1A與圖2，提供晶片堆疊結構100。晶片堆疊結構100具有相對的側壁SW1與側壁SW2。晶片堆疊結構100包括堆疊的多個晶片102。每個晶片102包括接墊104。多個晶片102上的多個接墊104位在晶片堆疊結構100的同一側。在一些實施例中，每個晶片102可包括多個接墊104。同一個晶片102上的多個接墊104可位在同一個晶片102的同一側。
此外，每個晶片102更可包括基底106、半導體元件108、介電層110、內連線結構112與封環114中的至少一者。基底106可具有相對的面S1與面S2。基底106可為半導體基底，如矽基底。接墊104設置在面S1上。接墊104的材料例如是金屬(如，銅、鋁或鎢)等導電材料。半導體元件108設置在面S1上，且電性連接至接墊104。半導體元件108可包括主動元件、被動元件或其組合。介電層110設置在面S1上，且覆蓋半導體元件108。此外，接墊104可設置在介電層110中。在一些實施例中，介電層110可為多層結構。介電層110的材料例如是氧化矽、氮化矽、氮氧化矽或其組合。內連線結構112設置在介電層110中。半導體元件108與接墊104可藉由內連線結構112而彼此電性連接。內連線結構112的材料例如是金屬(如，銅、鋁、鎢或其組合)等導電材料。封環114可環繞半導體元件108與接墊104。封環114可設置在介電層110中。在將晶圓(未示出)切割成晶片102時，封環114可用以防止在晶片102中產生裂痕。
此外，晶片堆疊結構100更可包括黏著劑116。黏著劑116設置在相鄰兩個晶片102之間。黏著劑116可用以將相鄰兩個晶片102進行結合。在一些實施例中，晶片堆疊結構100的形成方法可包括以下步驟。首先，將晶圓(未示出)切割成多個晶片102，再利用黏著劑116將多個晶片102進行結合，而形成包括堆疊的多個晶片102的晶片堆疊結構100。在另一些實施例中，晶片堆疊結構100的形成方法可包括以下步驟。首先，利用黏著劑116將多個晶圓(未示出)進行結合，再對結合後的多個晶圓進行切割，而形成包括堆疊的多個晶片102的晶片堆疊結構100。
請參照圖1B，將晶片堆疊結構100的側壁SW2放置在載板118上。載板118可以用承載晶片堆疊結構100，以利於進行後續製程。載板118可為半導體基板，如矽基板。此外，可提供黏著劑120至晶片堆疊結構100的側壁SW2與載板118之間，以將晶片堆疊結構100與載板118進行結合。
另外，將重佈線層結構122放置在晶片堆疊結構100的側壁SW1上。重佈線層結構122鄰近於接墊104。重佈線層結構122的延伸方向D1可垂直於面S1。此外，重佈線層結構122的延伸方向D1可平行於多個晶片102的堆疊方向D2。
重佈線層結構122可包括基底124與重佈線層126。基底124設置在晶片堆疊結構100的側壁SW1上。基底124可為半導體基底，如矽基底。重佈線層126設置在基底124上，且位在基底124的遠離晶片堆疊結構100的一側。重佈線層126可包括介電層128與重佈線路130。介電層128設置在基底124上。在一些實施例中，介電層128可為多層結構。介電層128的材料例如是氧化矽、氮化矽、氮氧化矽或其組合。重佈線路130設置在介電層128中。重佈線路130的材料例如是金屬(如，銅、鋁、鎢或其組合)等導電材料。
此外，重佈線層結構122更可包括偵錯電路132。偵錯電路132設置在介電層128中，且電性連接至重佈線路130。在一些實施例中，在晶片堆疊結構100中的某個晶片102損壞時，偵錯電路132可以偵測出是哪一個晶片102損壞，藉此可將損壞的晶片102進行替換。另外，可提供黏著劑134至重佈線層結構122與晶片堆疊結構100的側壁SW1之間，以將重佈線層結構122與晶片堆疊結構100進行結合。
另一方面，可形成為圍繞晶片堆疊結構100的包封體136。包封體136可覆蓋晶片堆疊結構100的頂面TS與底面BS。此外，包封體136更可圍繞重佈線層結構122。包封體136的材料可為模製化合物(molding compound)，如聚醯亞胺等。
請參照圖1C，可在重佈線層結構122與晶片102中形成開口OP。開口OP貫穿重佈線層結構122，且暴露出對應的接墊104。開口OP的形成方法可藉由微影製程與蝕刻製程對重佈線層結構122與晶片102進行圖案化。舉例來說，可使用封環114作為蝕刻終止層來移除部分重佈線層結構122、黏著劑134與部分介電層110，再藉由後續的蝕刻製程來移除部分封環114與部分介電層110，而形成暴露出接墊104的開口OP。
請參照圖1D，可在重佈線層結構122上形成填入開口OP的導體層138。此外，重佈線層結構122更可形成在導體層138上。導體層138的材料例如是銅、鋁或鎢等金屬。導體層138的形成方法例如是電鍍法、物理氣相沉積法或化學氣相沉積法。
請參照圖1E，可移除開口OP外部的導體層138，藉此可形成貫穿重佈線層結構122的多個導電插塞138a。導電插塞138a連接至對應的接墊104。在一些實施例中，導電插塞138a可直接連接至對應的接墊104。導電插塞138a可貫穿封環114。重佈線路130可電性連接至導電插塞138a。在一些實施例中，導電插塞138a可為矽穿孔(TSV)。開口OP外部的導體層138的移除方法例如是化學機械研磨法。
此外，導電插塞138a的延伸方向D3可平行於面S1。另外，導電插塞138a的延伸方向D3可垂直於重佈線層結構122的延伸方向D1。
另外，在形成導電插塞138a之後，可依據產品需求來決定是否移除載板118。在本實施例中，是以保留載板118為例，但本發明並不以此為限。
以下，藉由圖1E來說明本實施例的半導體封裝10。此外，雖然半導體封裝10的形成方法是以上述方法為例進行說明，但本發明並不以此為限。
請參照圖1E，半導體封裝10包括晶片堆疊結構100、重佈線層結構122與多個導電插塞138a。晶片堆疊結構100包括堆疊的多個晶片102。每個晶片102包括接墊104。多個晶片102上的多個接墊104位在晶片堆疊結構100的同一側。在一些實施例中，每個晶片102可包括多個接墊104。同一個晶片102上的多個接墊104可位在同一個晶片102的同一側。此外，每個晶片102更可包括基底106、半導體元件108、介電層110、內連線結構112與封環114中的至少一者。基底106可具有相對的面S1與面S2。接墊104設置在面S1上。半導體元件108設置在面S1上，且電性連接至接墊104。介電層110設置在面S1上，且覆蓋半導體元件108。內連線結構112設置在介電層110中。半導體元件108與接墊104可藉由內連線結構112而彼此電性連接。封環114可環繞半導體元件108與接墊104。另外，晶片堆疊結構100更可包括黏著劑116。黏著劑116設置在相鄰兩個晶片102之間。
重佈線層結構122設置在晶片堆疊結構100的側壁SW1上，且鄰近於接墊104。重佈線層結構122可包括基底124與重佈線層126。基底124設置在晶片堆疊結構100的側壁SW1上。重佈線層126設置在基底124上，且位在基底124的遠離晶片堆疊結構100的一側。重佈線層126可包括介電層128與重佈線路130。介電層128設置在基底124上。重佈線路130設置在介電層128中。此外，重佈線層結構122更可包括偵錯電路132。偵錯電路132設置在介電層128中，且電性連接至重佈線路130。
導電插塞138a貫穿重佈線層結構122。導電插塞138a連接至對應的接墊104。此外，導電插塞138a可貫穿封環114。重佈線路130可電性連接至導電插塞138a。
另外，半導體封裝10更可包括載板118、黏著劑120、黏著劑134與包封體136中的至少一者。載板118設置在晶片堆疊結構100的側壁SW2上。側壁SW2可相對於側壁SW1。黏著劑120設置在載板118與晶片堆疊結構100的側壁SW2之間。黏著劑134設置在重佈線層結構122與晶片堆疊結構100的側壁SW1之間。包封體136圍繞晶片堆疊結構100，且更可環繞重佈線層結構122。
此外，半導體封裝10的各構件的材料、詳細配置方式、形成方法與功效已於上述實施例進行詳盡地說明，於此不再重複說明。
基於上述實施例可知，在上述半導體封裝10及其製造方法中，多個晶片102上的多個接墊104位在晶片堆疊結構100的同一側，重佈線層結構122設置在晶片堆疊結構100的側壁SW1上且鄰近於接墊104，且導電插塞138a貫穿重佈線層結構122且連接至對應的接墊104。因此，可藉由導電插塞138a與重佈線層結構122進行晶片102之間的電性連接。此外，在上述半導體封裝10及其製造方法中，由於可藉由導電插塞138a與重佈線層結構122進行晶片102之間的電性連接，因此可以不對每個晶片102的基底106進行薄化製程，進而可防止在晶片102的基底106中產生裂痕。另外，在上述半導體封裝10及其製造方法中，由於可藉由導電插塞138a與重佈線層結構122進行晶片102之間的電性連接，因此無須形成穿過晶片102的基底106且用於進行晶片102之間的電性連接的導電插塞，藉此可防止在晶片102的基底106中產生裂痕。因此，上述半導體封裝10及其製造方法可降低製程複雜度並提升良率。
綜上所述，在上述實施例的半導體封裝及其製造方法中，將重佈線層結構設置在晶片堆疊結構的一側且鄰近於接墊，且利用導電插塞將晶片的接墊電性連接至重佈線層結構。因此，可藉由導電插塞與重佈線層結構進行晶片之間的電性連接，藉此可降低製程複雜度並提升良率。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
100:晶片堆疊結構 102:晶片 104:接墊 106, 124:基底 108:半導體元件 110, 128:介電層 112:內連線結構 114:封環 116, 120, 134:黏著劑 118:載板 122:重佈線層結構 126:重佈線層 130:重佈線路 132:偵錯電路 136:包封體 138:導體層 138a:導電插塞 BS:底面 D1, D3:延伸方向 D2:堆疊方向 OP:開口 S1, S2:面 SW1, SW2:側壁 TS:頂面
圖1A至圖1E為本發明一實施例的半導體封裝的製造流程剖面圖。 圖2為圖1A中的晶片的立體示意圖。
100:晶片堆疊結構
102:晶片
104:接墊
106,124:基底
108:半導體元件
110,128:介電層
112:內連線結構
114:封環
116,120,134:黏著劑
118:載板
122:重佈線層結構
126:重佈線層
130:重佈線路
132:偵錯電路
136:包封體
138a:導電插塞
BS:底面
D1,D3:延伸方向
D2:堆疊方向
OP:開口
S1,S2:面
SW1,SW2:側壁
TS:頂面

Claims (18)

  1. 一種半導體封裝，包括：晶片堆疊結構，包括堆疊的多個晶片，其中每個所述晶片包括接墊，且多個所述晶片上的多個所述接墊位在所述晶片堆疊結構的同一側；重佈線層結構，設置在所述晶片堆疊結構的第一側壁上，且鄰近於多個所述接墊；以及多個導電插塞，貫穿所述重佈線層結構，其中所述導電插塞連接至對應的所述接墊，其中每個所述晶片更包括：第一基底，具有相對的第一面與第二面，其中所述接墊設置在所述第一面上；半導體元件，設置在所述第一面上，且電性連接至所述接墊；第一介電層，設置在所述第一面上，且覆蓋所述半導體元件；以及內連線結構，設置在所述第一介電層中，其中所述半導體元件與所述接墊藉由所述內連線結構而彼此電性連接。
  2. 如請求項1所述的半導體封裝，其中所述重佈線層結構的延伸方向平行於多個所述晶片的堆疊方向。
  3. 如請求項1所述的半導體封裝，其中每個所述晶片包括多個所述接墊，且同一個所述晶片上的多個所述接墊位在同一個所述晶片的同一側。
  4. 如請求項1所述的半導體封裝，其中每個所述晶片更包括：封環，環繞所述半導體元件與所述接墊，其中所述導電插塞貫穿所述封環。
  5. 如請求項1所述的半導體封裝，其中所述重佈線層結構的延伸方向垂直於所述第一面，且所述導電插塞的延伸方向平行於所述第一面。
  6. 如請求項1所述的半導體封裝，其中所述晶片堆疊結構更包括：黏著劑，設置在相鄰兩個所述晶片之間。
  7. 如請求項1所述的半導體封裝，其中所述重佈線層結構包括：第二基底，設置在所述晶片堆疊結構的所述第一側壁上；以及重佈線層，設置在所述第二基底上，且位在所述第二基底的遠離所述晶片堆疊結構的一側，其中所述重佈線層包括：第二介電層，設置在所述第二基底上；以及重佈線路，設置在所述第二介電層中，且電性連接至所述導電插塞。
  8. 如請求項7所述的半導體封裝，其中所述重佈線層結構更包括：偵錯電路，設置在所述第二介電層中，且電性連接至所述重佈線路。
  9. 如請求項1所述的半導體封裝，更包括：黏著劑，設置在所述重佈線層結構與所述晶片堆疊結構的所述第一側壁之間。
  10. 如請求項1所述的半導體封裝，更包括：載板，設置在所述晶片堆疊結構的第二側壁上，其中所述第二側壁相對於所述第一側壁。
  11. 如請求項10所述的半導體封裝，更包括：黏著劑，設置在所述載板與所述晶片堆疊結構的所述第二側壁之間。
  12. 如請求項1所述的半導體封裝，更包括：包封體，圍繞所述晶片堆疊結構。
  13. 一種半導體封裝的製造方法，包括：提供晶片堆疊結構，其中所述晶片堆疊結構具有相對的第一側壁與第二側壁，且包括堆疊的多個晶片，每個所述晶片包括接墊，且多個所述晶片上的多個所述接墊位在所述晶片堆疊結構的同一側；將所述晶片堆疊結構的所述第二側壁放置在載板上；將重佈線層結構放置在所述晶片堆疊結構的所述第一側壁 上，其中所述重佈線層結構鄰近於多個所述接墊；以及形成貫穿所述重佈線層結構的多個導電插塞，其中所述導電插塞連接至對應的所述接墊，其中每個所述晶片更包括：基底，具有相對的第一面與第二面，其中所述接墊設置在所述第一面上；半導體元件，設置在所述第一面上，且電性連接至所述接墊；介電層，設置在所述第一面上，且覆蓋所述半導體元件；以及內連線結構，設置在所述介電層中，其中所述半導體元件與所述接墊藉由所述內連線結構而彼此電性連接。
  14. 如請求項13所述的半導體封裝的製造方法，其中所述晶片堆疊結構更包括：黏著劑，設置在相鄰兩個所述晶片之間。
  15. 如請求項13所述的半導體封裝的製造方法，更包括：提供黏著劑至所述晶片堆疊結構的所述第二側壁與所述載板之間。
  16. 如請求項13所述的半導體封裝的製造方法，更包括：提供黏著劑至所述重佈線層結構與所述晶片堆疊結構的所述第一側壁之間。
  17. 如請求項13所述的半導體封裝的製造方法，更包括： 形成圍繞所述晶片堆疊結構的包封體。
  18. 如請求項13所述的半導體封裝的製造方法，其中多個所述導電插塞的形成方法包括：在所述重佈線層結構與多個所述晶片中形成多個開口，其中所述開口貫穿所述重佈線層結構，且暴露出對應的所述接墊；以及在所述重佈線層結構上形成填入多個所述開口的導體層；以及移除多個所述開口外部的所述導體層。
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