CN108074872B - 封装件结构及其形成方法 - Google Patents

封装件结构及其形成方法 Download PDF

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Publication number
CN108074872B
CN108074872B CN201711105990.5A CN201711105990A CN108074872B CN 108074872 B CN108074872 B CN 108074872B CN 201711105990 A CN201711105990 A CN 201711105990A CN 108074872 B CN108074872 B CN 108074872B
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die
forming
package structure
memory
dummy
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CN108074872A (zh
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余振华
胡宪斌
林俊成
卢思维
候上勇
魏文信
施应庆
吴集锡
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一个实施例是一种方法，所述方法包括：使用第一电连接器将第一管芯附接到第一组件的第一侧，使用第二电连接器将第二管芯的第一侧附接到第一组件的第一侧，将伪管芯附接到第一组件的划线区域中的第一组件的第一侧，将覆盖结构粘附到第二管芯的第二侧，并且分割第一组件和伪管芯以形成封装件结构。本发明的实施例还涉及封装件结构及其形成方法。

Description

封装件结构及其形成方法
技术领域
本发明的实施例涉及封装件结构及其形成方法。
背景技术
由于集成电路(IC)的发展，由于各种电子组件(即，晶体管、二极管、电阻器、电容器等)的集成密度方面的不断改善，半导体工业已经经历了持续快速的增长。在大多数情况下，集成密度方面的这些改进来自于最小部件尺寸的重复减小，这允许将更多的组件集成到给定区域中。
这些集成改进本质上基本是二维(2D)的，因为由集成组件所占据的面积基本上是在半导体晶圆的表面上。集成电路的增加的密度和面积的相应减小通常超过将集成电路芯片直接接合到衬底上的能力。已经使用中介层(interposer)将球接触面积从芯片的接触面积再分布到中介层的更大面积。此外，中介层允许包括多个芯片的三维(3D)封装。其他封装件也已经被开发出来，以纳入3D方面。
发明内容
本发明的实施例提供了一种形成封装件结构的方法，包括：使用第一电连接器将第一管芯附接到第一组件的第一侧；使用第二电连接器将第二管芯的第一侧附接到所述第一组件的第一侧；将伪管芯附接到所述第一组件的划线区域中的所述第一组件的第一侧；将覆盖结构粘附到所述第二管芯的第二侧；以及分割所述第一组件和所述伪管芯以形成封装件结构。
本发明的另一实施例提供了一种形成封装件结构的方法，包括：使用第一电连接器将第一管芯接合到第一结构的第一侧；使用第二电连接器将存储器管芯接合到所述第一结构的第一侧，所述存储器管芯与所述第一管芯相邻；将第二管芯附接到所述存储器管芯的背面，所述第二管芯的厚度大于所述存储器管芯的厚度；以及分割所述第一结构以形成封装件结构。
本发明的又一实施例提供了一种封装件结构，包括：中介层的第一侧，接合到封装件衬底；第一管芯和第二管芯的有源侧，接合到所述中介层的第二侧，所述第二侧与所述第一侧相对；伪管芯，附接到所述中介层的第二侧，所述伪管芯与所述第一管芯或所述第二管芯中的至少一个相邻；以及覆盖结构，粘附到所述第二管芯的背面。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳地理解本发明的各个方面。应该注意，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增大或减小。
图1至图15是根据一些实施例的形成封装件结构的示例性过程中的截面图和平面图。
图16示出了根据一些实施例的封装件结构的截面图。
图17示出了根据一些实施例的封装件结构的截面图。
图18示出了根据一些实施例的封装件结构的截面图。
图19和图20示出了根据一些实施例的封装件结构的截面图。
图21示出了根据一些实施例的封装件结构的截面图。
具体实施方式
以下公开内容提供了用于本发明的不同部件的许多不同实施例或实例。下面描述了组件和布置的特定实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件以直接接触的方式形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为了便于描述，在此可以使用诸如“在…下方”、“在…之下”、“下部”、“在…之上”、“上部”等空间相对术语以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，并且在此使用的空间相对描述符可以同样地作出相应的解释。
本文讨论的实施例可以在特定的上下文中讨论，即包括邻近有源管芯的伪管芯结构的封装件结构，以减少封装件结构的翘曲。封装件结构的翘曲的这种减少使得能够通过降低有源管芯和中介层之间的冷接头的可能性来实现更可靠的封装件结构。在一些实施例中，伪管芯在划线区域中，并且覆盖结构覆盖一些有源管芯，而其它有源管芯未被覆盖结构所覆盖。伪管芯可以允许更多地控制密封剂的比例，并且因此可以减小源自热膨胀系数(CTE)失配的应力和翘曲。在一些实施例中，当划线区域中的伪管芯和/或覆盖结构为封装件结构提供足够的支撑和保护时，可以省略密封剂。在一些实施例中，有源管芯是一个或多个管芯(逻辑管芯堆叠件和/或存储器管芯堆叠件)的堆叠件，其中管芯堆叠件的最顶部的管芯比管芯堆叠件的其它管芯更厚。在这些实施例中，可以省略划线区域中的伪管芯和密封剂，因为管芯堆叠件的较厚的顶部管芯为封装件结构提供了足够的支撑和保护。
将参照特定的上下文来描述实施例，即使用衬底上晶圆上芯片(CoWoS)处理的管芯-中介层-衬底堆叠的封装件。然而，其它实施例也可以应用于其它封装件，例如管芯-管芯-衬底堆叠的封装件，以及其它处理。本文讨论的实施例是为了提供能够制作或使用本公开的主题的实例，并且本领域普通技术人员将容易地理解可以在保持在不同实施例的预期范围内的修改。以下附图中的类似参考标号和字符指的是类似的组件。尽管方法实施例可以被讨论为以特定顺序实施，但是可以以任何逻辑顺序来实施其他方法实施例。
图1一般性地示出了一个或多个管芯68的形成。衬底60在处理期间包括一个或多个管芯68。在一个实施例中的衬底60是晶圆，并且可以包括块状半导体衬底、绝缘体上半导体(SOI)衬底、多层半导体衬底等。衬底60的半导体材料可以是硅、锗、化合物半导体，该化合物半导体包括硅锗、碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟；合金半导体，该合金半导体包括SiGe、GaAsP、AlInAs、AlGaAs，GaInAs、GaInP和/或GaInAsP；或上述的组合。也可以使用其它衬底，例如多层衬底或梯度衬底。衬底60可以是掺杂的或未掺杂的。诸如晶体管、电容器、电阻器、二极管等的器件可以形成在衬底60的有源表面62中和/或衬底60的有源表面62上。
在有源表面62上形成包括一个或多个介电层和相应的金属化图案的互连结构64。介电层中的金属化图案可以例如通过使用通孔和/或迹线在器件之间路由电信号，并且还可以包含各种电气器件，例如电容器、电阻器、电感器等。各种器件和金属化图案可以互连以实施一个或多个功能。该功能可以包括存储器结构、处理结构、传感器、放大器、配电、输入/输出电路等。此外，诸如导电柱(例如，包括诸如铜的金属)的管芯连接器66形成在互连结构64中和/或互连结构64上，以提供到电路和器件的外部电连接。在一些实施例中，管芯连接器66从互连结构64突出，以形成当将管芯68接合到其他结构时要使用的柱结构。本领域普通技术人员将理解，为了说明的目的，提供了上述实例。可以根据适用于给定的应用而使用其他电路。
更具体地，可以在互连结构64中形成金属间介电(IMD)层。例如，IMD层可以由诸如磷硅玻璃(PSG)、硼磷硅玻璃(BPSG)、氟硅酸盐玻璃(FSG)、SiOxCy、旋涂式玻璃、旋涂式聚合物、硅碳材料、上述的化合物，上述的复合材料、上述的组合等的低K介电材料，通过本领域已知的任何合适的方法(诸如旋涂、化学气相沉积(CVD)、等离子体增强CVD(PECVD)、高密度等离子体化学气相沉积(HDP-CVD)等)形成。可以在IMD层中形成金属化图案，例如通过使用光刻技术在IMD层上沉积并图案化光刻胶材料以暴露将成为金属化图案的IMD层的部分。可以使用诸如各向异性干蚀刻工艺的蚀刻工艺来在IMD层中产生对应于IMD层的暴露部分的凹槽和/或开口。凹槽和/或开口可以用扩散阻挡层作内衬并填充有导电材料。扩散阻挡层可以包括通过原子层沉积(ALD)等沉积的TaN、Ta、TiN、Ti、CoW等的一层或多层，并且导电材料可以包括通过CVD、物理气相沉积(PVD)等沉积的铜、铝、钨、银及上述的组合等。可以例如通过使用化学机械抛光(CMP)来去除IMD层上的任何过量的扩散阻挡层和/或导电材料。
在图2中，包括互连结构64的衬底60被分割成单独的管芯68。通常，管芯68包含相同的电路，例如器件和金属化图案，尽管管芯可以具有不同的电路。所述分割可以是锯切、划切等。
管芯68可以是逻辑管芯(例如，中央处理单元、图形处理单元、芯片上系统、微控制器等)、存储器管芯(例如，动态随机存取存储器(DRAM)管芯、静态随机存取存储器(SRAM)管芯等)、电源管理管芯(例如，电源管理集成电路(PMIC)管芯)、射频(RF)管芯、传感器管芯、微电子机械系统(MEMS)管芯、信号处理管芯(例如，数字信号处理(DSP)管芯)、前端管芯(例如，模拟前端(AFE)管芯)等或上述的组合。此外，在一些实施例中，管芯68可以是不同的尺寸(例如，不同的高度和/或表面积)，并且在其他实施例中，管芯68可以是相同的尺寸(例如，相同的高度和/或表面积)。
图3示出了一个或多个组件96的第一侧的形成。如图14所示，一个或多个组件96可以从衬底70形成。组件96可以是中介层或另一个管芯。衬底70可以是晶圆。衬底70可以包括块状半导体衬底、SOI衬底、多层半导体衬底等。衬底70的半导体材料可以是硅、锗、化合物半导体，该化合物半导体包括硅锗、碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟；合金半导体，该合金半导体包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP；或上述的组合。也可以使用其它衬底，例如多层衬底或梯度衬底。衬底70可以是掺杂的或未掺杂的。诸如晶体管、电容器、电阻器、二极管等的器件可以形成在衬底70的第一表面(也可以称为有源表面)72中和/或衬底70的第一表面72上，其也可以称为衬底70的有源表面。在组件96是中介层的实施例中，组件96中通常不包括有源器件，尽管中介层可以包括形成在第一表面72中和/或第一表面72上和/或再分布结构76中的无源器件。
通孔(TV)74形成为从衬底70的第一表面72延伸到衬底70中。当衬底70是硅衬底时，TV 74有时还被称为衬底通孔或硅通孔。例如，TV 74可以通过蚀刻、研磨、激光技术，上述的组合和/或类似方式在衬底70中形成凹槽来形成。例如通过使用氧化技术，可以在凹槽中形成薄的介电材料。诸如通过CVD、ALD、PVD、热氧化、它们组合和/或类似方式，薄的阻挡层可以共形沉积在衬底70的前侧上方和开口中。阻挡层可以包括氮化物或氮氧化物，诸如氮化钛、氮氧化钛、氮化钽、氮氧化钽、氮化钨、它们的组合和/或类似物。导电材料可以沉积在薄的阻挡层上方和开口中。导电材料可以通过电化学镀工艺、CVD、ALD、PVD、上述的组合和/或类似方式形成。导电材料的实例是铜、钨、铝、银、金、上述的组合和/或类似物。例如，通过CMP从衬底70的前侧去除过量的导电材料和阻挡层。因此，TV 74可以包括导电材料和导电材料与衬底70之间的薄的阻挡层。
再分布结构76形成在衬底70的第一表面72上方，并且用于将集成电路器件(如果存在的话)和/或TV 74电连接在一起和/或与外部器件电连接。再分布结构76可以包括一个或多个介电层和介电层中的相应的金属化图案。金属化图案可以包括用于将任何器件和/或TV 74互连在一起和/或与外部器件互连的通孔和/或迹线。金属化图案有时称为再分布线(RDL)。介电层可以包括氧化硅、氮化硅、碳化硅、氮氧化硅、低K介电材料，例如PSG、BPSG、FSG、SiOxCy、旋涂式玻璃、旋涂式聚合物、硅碳材料、上述的化合物、上述的复合材料、上述的组合等。介电层可以通过本领域已知的任何合适的方法沉积，诸如旋涂、CVD、PECVD、HDP-CVD等。可以在介电层中形成金属化图案，例如，通过使用光刻技术在介电层上沉积并图案化光刻胶材料以暴露将成为金属化图案的介电层的部分。可以使用诸如各向异性干蚀刻工艺的蚀刻工艺来在介电层中产生与介电层的暴露部分相对应的凹槽和/或开口。凹槽和/或开口可以用扩散阻挡层作内衬并填充有导电材料。扩散阻挡层可以包括通过ALD等沉积的TaN、Ta、TiN、Ti、CoW等的一层或多层，并且导电材料可以包括通过CVD、PVD等沉积的铜、铝、钨、银及上述的组合等。可以例如通过使用CMP来去除介电层上的任何过量的扩散阻挡层和/或导电材料。
电连接器77/78形成在导电焊盘上的再分布结构76的顶表面处。在一些实施例中，导电焊盘包括凸块下金属(UBM)。在所示实施例中，焊盘形成在再分布结构76的介电层的开口中。在另一个实施例中，焊盘(UBM)可以延伸穿过再分布结构76的介电层的开口，并且还延伸跨越再分布结构76的顶表面。作为形成焊盘的实例，至少在再分布结构76的介电层中的开口中形成晶种层(未示出)。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包含钛层和钛层上方的铜层。例如，晶种层可以使用PVD等形成。然后在晶种层上形成并图案化光刻胶。光刻胶可以通过旋涂等形成，并且可以暴露于用于图案化的光。光刻胶的图案对应于焊盘。图案化形成穿过光刻胶的开口以暴露晶种层。导电材料形成在光刻胶的开口中和晶种层的暴露部分上。导电材料可以通过镀敷形成，例如电镀或化学镀等。导电材料可以包括金属，如铜、钛、钨、铝等。然后，除去光刻胶和晶种层的其上未形成导电材料的部分。可以通过可接受的灰化或剥离工艺(例如使用氧等离子体等)去除光刻胶。一旦去除了光刻胶，就可以例如通过使用可接受的蚀刻工艺(例如通过湿蚀刻或干蚀刻)来去除晶种层的暴露部分。晶种层的剩余部分和导电材料形成焊盘。在焊盘不同地形成的实施例中，可以使用更多的光刻胶和图案化步骤。
在一些实施例中，电连接器77/78包括具有金属覆盖层78的金属柱77，金属覆盖层78可以是金属柱77上方的焊帽78。包括柱77和覆盖层78的电连接器77/78有时称为微凸块77/78。在一些实施例中，金属柱77包括诸如铜、铝、金、镍、钯等或上述的组合的导电材料，并且可以通过溅射、印刷、电镀、化学镀、CVD等形成。金属柱77可以是无焊料的并且具有基本垂直的侧壁。在一些实施例中，金属覆盖层78形成在金属柱77的顶部上。金属覆盖层78可以包括镍、锡、锡铅、金、铜、银、钯、铟、镍-钯-金、镍-金等或上述的组合，并且可以通过镀敷工艺形成。
在另一个实施例中，电连接器77/78不包括金属柱，并且是焊球和/或凸块，例如可控塌陷芯片连接(C4)、化学镀镍浸金(ENIG)、化学镀镍化学镀钯浸金(ENEPIG)技术形成的凸块等。在本实施例中，凸块电连接器77/78可以包括诸如焊料、铜、铝、金、镍、银、钯、锡等或上述的组合的导电材料。在该实施例中，电连接器77/78首先通过由诸如蒸发、电镀、印刷、焊料转移、球放置等这样的常用方法形成焊料层来形成。一旦已经在结构上形成了焊料层，则可以实施回流以便将材料成形为期望的凸块形状。
在图4中，管芯68和管芯88附接到组件96的第一侧，例如，通过电连接器77/78和金属柱79倒装芯片接合在管芯上以形成导电接头91。金属柱79可以类似于金属柱77，并且这里不再重复描述。例如，管芯68和管芯88可以使用拾取和放置工具放置在电连接器77/78上。在一些实施例中，金属覆盖层78形成在金属柱77(如图3所示)、管芯68和管芯88的金属柱79、或两者上。
管芯88可以通过如上文参考管芯68所述的类似的处理来形成。在一些实施例中，管芯88包括一个或多个存储器管芯，例如存储器管芯(例如，DRAM管芯、SRAM管芯、高带宽存储器(HBM)管芯、混合存储器数据集(HMC)管芯等)的堆叠件。在存储器管芯的堆叠件的实施例中，管芯88可以包括存储器管芯和存储器控制器，例如具有存储器控制器的四个或八个存储器管芯的堆叠件。此外，在一些实施例中，管芯88可以是不同的尺寸(例如，不同的高度和/或表面积)，并且在其他实施例中，管芯88可以是相同的尺寸(例如，相同的高度和/或表面积)。
管芯88包括主体80、互连结构84和管芯连接器86。管芯88的主体80可以包括任何数量的管芯、衬底、晶体管、有源器件、无源器件等。在一个实施例中，主体80可以包括块状半导体衬底、绝缘体上半导体(SOI)衬底、多层半导体衬底等。主体80的半导体材料可以是硅、锗、化合物半导体，该化合物半导体包括硅锗、碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟；合金半导体，该合金半导体包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP；或上述的组合。也可以使用其它衬底，例如多层衬底或梯度衬底。主体80可以是掺杂的或未掺杂的。诸如晶体管、电容器、电阻器、二极管等的器件可以形成在有源表面中和/或有源表面上。
在有源表面上形成包括一个或多个介电层和相应的金属化图案的互连结构84。介电层中的金属化图案可以例如通过使用通孔和/或迹线在器件之间路由电信号，并且还可以包含各种电气器件，例如电容器、电阻器、电感器等。各种器件和金属化图案可以互连以实施一个或多个功能。该功能可以包括存储器结构、处理结构、传感器、放大器、配电、输入/输出电路等。此外，诸如导电柱(例如，包括诸如铜的金属)的管芯连接器86形成在互连结构84中和/或互连结构84上，以提供到电路和器件的外部电连接。在一些实施例中，管芯连接器86从互连结构84突出，以形成当将管芯88接合到其它结构时要使用的柱结构。本领域普通技术人员将理解，为了说明的目的，提供了上述实例。可以根据适用于给定的应用而使用其他电路。
更具体地，可以在互连结构84中形成IMD层。例如，IMD层可以由诸如PSG、BPSG、FSG、SiOxCy、旋涂式玻璃、旋涂式聚合物、硅碳材料、上述的化合物、上述的复合材料、上述的组合等的低K介电材料，通过本领域已知的任何合适的方法(诸如旋涂、CVD、PECVD、HDP-CVD等)形成。可以在IMD层中形成金属化图案，例如，通过使用光刻技术在IMD层上沉积并图案化光刻胶材料以暴露将成为金属化图案的IMD层的部分。可以使用诸如各向异性干蚀刻工艺的蚀刻工艺来在IMD层中产生与IMD层的暴露部分相对应的凹槽和/或开口。凹槽和/或开口可以用扩散阻挡层作内衬并填充有导电材料。扩散阻挡层可以包括通过ALD等沉积的氮化钽、钽、氮化钛、钛、钴钨等或上述组合的一层或多层。金属化图案的导电材料可以包括通过CVD、PVD等沉积的铜、铝、钨、银和上述的组合等。可以例如通过使用CMP来去除IMD层上的任何过量的扩散阻挡层和/或导电材料。
在管芯连接器66和管芯连接器86分别从互连结构64和互连结构84突出的实施例中，金属柱79可以从管芯68和管芯88除去，因为突出的管芯连接器66和管芯连接器86可以用作用于金属覆盖层78的柱。
导电接头91将管芯68和管芯88中的电路分别通过互连结构64和互连结构84以及管芯连接器66和管芯连接器86电连接到组件96中的再分布结构76和TV 74。
在一些实施例中，在接合电连接器77/78之前，电连接器77/78涂覆有焊剂(未示出)，例如免清洁焊剂。电连接器77/78可以浸入焊剂中，或者焊剂可以喷射到电连接器77/78之上。在另一个实施例中，焊剂可以施加到电连接器79/78。在一些实施例中，电连接器77/78和79/78可以在它们被回流之前具有形成在其上的环氧树脂焊剂(未示出)，其中在管芯68和管芯88附接到组件96之后保留了环氧树脂焊剂的至少一些环氧树脂部分。该保留的环氧树脂部分可以用作底部填充物以减少应力并保护由回流电连接器77/78/79而产生的接头。
管芯68和管芯88与组件96之间的接合可以是焊接或直接金属对金属(例如铜对铜或锡对锡)接合。在一个实施例中，管芯68和管芯88通过回流工艺接合到组件96。在该回流工艺中，电连接器77/78/79分别与管芯连接器66和管芯连接器86接触，并且再分布结构76的焊盘将管芯68和管芯88物理连接和电连接到组件96。在接合工艺之后，可以在金属柱77和金属柱79以及金属覆盖层78的界面处形成IMC(未示出)。
在图4和随后的附图中，分别示出了用于形成第一封装件和第二封装件的第一封装区域90和第二封装区域92。划线区域94在相邻封装区域之间。如图4所示，在第一封装区域90和第二封装区域92中的每一个中附接有管芯68和多个管芯88。
在一些实施例中，管芯68是芯片上系统(SoC)或图形处理单元(GPU)，并且第二管芯是可被管芯68利用的存储器管芯。在一个实施例中，管芯88是堆叠的存储器管芯。例如，堆叠的存储器管芯88可以包括低功率(LP)双数据速率(DDR)存储器模块，诸如LPDDR1、LPDDR2、LPDDR3、LPDDR4等的存储器模块。
在图5中，将底部填充材料100分配到管芯68、管芯88、再分布结构76之间的间隙中并且围绕导电接头91。在图5和随后的附图中，每个导电接头91的示意图均示出为包括单个结构，但是如图4所示，每个导电接头91可以包括两个金属柱77和金属柱79，在金属柱77和金属柱79之间具有金属层78。底部填充材料100可以沿着管芯68和管芯88的侧壁向上延伸。底部填充材料100可以是任何可接受的材料，例如聚合物、环氧树脂、模制底部填充物等。底部填充材料100可以在管芯68和管芯88附接之后通过毛细流动过程形成，或者可以在管芯68和管芯88附接之前通过合适的沉积方法形成。
在图6A和图6B中，伪管芯106用附接结构104粘附在与管芯88相邻的划线区域94中。图6A和图6B示出了用于附接结构104的两个实施例。伪管芯106放置在划线区域94中可以帮助防止在第一封装区域90和第二封装区域92中的封装件的分割期间和之后的翘曲(参见图14)。伪管芯106可以有助于减少翘曲的一种方式是在实际的分割过程中对封装件提供支撑。如果存在密封剂，伪管芯106可以防止翘曲的另一种方式是减小组件96和随后形成的密封剂112(参见图8)之间的热膨胀系数(CTE)失配，因为伪管芯106具有与组件96类似的CTE，并且它们减少了封装件中所需的密封剂112的量。
伪管芯106通过附接结构104附接到组件96。在一些实施例中，附接结构104是将伪管芯106接合到组件的一个或多个微凸块。在一些实施例中，附接结构104是将伪管芯106粘附到组件96的粘合剂。伪管芯106可以由硅、介电材料等或上述的组合制成。在一些实施例中，伪管芯106实际上是作为伪管芯106再循环的有缺陷的有源管芯。在一些实施例中，伪管芯106是块状材料，并且不包括任何有源器件或无源器件。在一些实施例中，伪管芯106的顶表面与管芯68的背面齐平。
在图6A中，示出了微凸块附接结构104的实施例。在该实施例中，微凸块104形成在伪管芯106的底表面、组件96的顶表面或两者上。微凸块104可以与接合管芯68和管芯88的微凸块(例如电连接器77/78/79)同时形成。特别地，附接结构104的结构104A、104B和104C可以是分别与结构77、78和79相同，并且在这里不再重复描述这些结构。在示意图中微凸块104将伪管芯106接合到组件96的诸如再分布结构76。伪管芯106的微凸块104可以与管芯68和管芯88的电连接器77/78/79一起回流。例如，伪管芯106可以通过使用拾取和放置工具放置在微凸块104上。底部填充材料100可以在伪管芯106接合之前或之后固化。
在图6B中，示出了粘合剂附接结构104的实施例。在该实施例中，粘合剂104在伪管芯106的底表面上，并且在示意图中将伪管芯106粘附到组件96的诸如再分布结构76。粘合剂104可以是任何合适的粘合剂、环氧树脂、管芯附着膜(DAF)等。粘合剂104可以施加到伪管芯106的底表面，或者可以施加在再分布结构76的表面上方。例如，伪管芯106可以使用拾取和放置工具通过粘合剂104粘附到再分布结构76。底部填充材料100可以在伪管芯106粘附之前或之后固化。
在图7中，覆盖结构110粘附在管芯88的背面上。覆盖结构110显著减小了管芯88上的应力，并且可以在随后的处理期间保护管芯88。在一些实施例中，管芯88包括一个或多个存储器管芯的堆叠件，并且覆盖结构110比管芯88的一个或多个存储器管芯中的每一个更厚。在一些实施例中，覆盖结构110具有在垂直于衬底70的主表面的方向上的厚度，该厚度范围为从约50μm至约200μm，例如约100μm。
在一些实施例中，覆盖结构110的顶表面与管芯68的背面和伪管芯106的顶表面齐平。在一些实施例中，覆盖结构110用粘合剂108粘合。覆盖结构110可以由硅、介电材料等或上述的组合制成。覆盖结构110可以包括与伪管芯106相同的材料。在一些实施例中，覆盖结构110实际上是作为覆盖结构110再循环的有缺陷的有源管芯。在一些实施例中，覆盖结构110是块状材料，并且不包括任何有源器件或无源器件。粘合剂108在覆盖结构110的底表面上，并将覆盖结构110粘附到管芯88。粘合剂108可以是任何合适的粘合剂、环氧树脂、DAF等。例如，覆盖结构110可以使用拾取和放置工具通过粘合剂108粘附到管芯88。
在图8中，在各种组件上形成密封剂112。密封剂112可以是模塑料、环氧树脂等，并且可以通过压缩模塑、传递模塑等来施加。实施固化步骤以固化密封剂112，其中固化可以是热固化、紫外线(UV)固化等。在一些实施例中，将管芯68、伪管芯106和/或覆盖结构110埋在密封剂112中，并且在密封剂112的固化之后，可以实施诸如研磨的平面化步骤，以去除密封剂112的过量部分，其过量的部分在管芯68、伪管芯106和/或覆盖结构110的顶表面上方。因此，管芯68、伪管芯106和/或覆盖结构110的顶表面暴露并且与密封剂112的顶表面齐平。
图9至图12示出了组件96的第二侧的形成。在图9中，翻转图8的结构以准备形成组件96的第二侧。尽管未示出，结构可以放置在用于图9至图12的工艺的载体或支撑结构上。如图9所示，在该处理阶段，组件96的衬底70和再分布结构76的组合厚度T1在从约750μm至约800μm的范围内，例如约775μm。伪管芯106(包括附接结构104)的厚度T2在从约750μm至约800μm的范围内，例如约760μm。在一些实施例中，管芯68和管芯88(包括用于管芯88的导电接头91和覆盖结构110)中的一个或两个具有厚度T2。
在图10中，在衬底70的第二侧上实施薄化工艺，以将衬底70薄化到第二表面116，直到暴露TV 74。薄化工艺可以包括蚀刻工艺、研磨工艺等或上述的组合。在一些实施例中，在薄化工艺之后，组件96的衬底70和再分布结构76的组合厚度T3在从约20μm至约180μm范围内，例如约100μm。
在图11中，再分布结构形成在衬底70的第二表面116上，并且用于将TV 74电连接在一起和/或与外部器件电连接。再分布结构包括一个或多个介电层117和一个或多个介电层117中的金属化图案118。该金属化图案可以包括将TV 74互连在一起和/或与外部器件互连的通孔和/或迹线。金属化图案118有时称为再分布线(RDL)。介电层117可以包括氧化硅、氮化硅、碳化硅、氮氧化硅、低K介电材料，诸如PSG、BPSG、FSG、SiOxCy、旋涂式玻璃、旋涂式聚合物、硅碳材料、上述的化合物、上述的复合材料、上述的组合等。介电层117可以通过本领域已知的任何合适的方法沉积，诸如旋涂、CVD、PECVD、HDP-CVD等。例如，金属化图案118可以形成在介电层117中，例如，通过使用光刻技术在介电层117上沉积和图案化光刻胶材料以暴露将成为金属化图案118的介电层117的部分。可以使用诸如各向异性干蚀刻工艺的蚀刻工艺来在介电层117中产生与介电层117的暴露部分相对应的凹槽和/或开口。凹槽和/或开口可以用扩散阻挡层作内衬并填充有导电材料。扩散阻挡层可以包括通过ALD等沉积的TaN、Ta、TiN、Ti、CoW等的一层或多层，并且导电材料可以包括通过CVD、PVD等沉积的铜、铝、钨、银及上述的组合等。可以例如通过使用CMP来去除介电层上的任何过量的扩散阻挡层和/或导电材料。
在图12中，电连接器120也形成在金属化图案118上并且电连接到TV 74。电连接器120形成在金属化图案118上的再分布结构的顶表面处。在一些实施例中，金属化图案118包括UBM。在所示实施例中，焊盘形成在再分布结构的介电层117的开口中。在另一个实施例中，焊盘(UBM)可以延伸穿过再分布结构的介电层117的开口并且还延伸跨越再分布结构的顶表面。
作为形成焊盘的实例，至少在再分布结构的介电层117中的一个开口中形成晶种层(未示出)。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和钛层上方的铜层。例如，晶种层可以使用PVD等形成。然后在晶种层上形成并图案化光刻胶。光刻胶可以通过旋涂等形成，并且可以暴露于用于图案化的光。光刻胶的图案对应于焊盘。图案化形成穿过光刻胶的开口以暴露晶种层。导电材料形成在光刻胶的开口中和晶种层的暴露部分上。导电材料可以通过镀敷形成，例如电镀或化学镀等。导电材料可以包括金属，如铜、钛、钨、铝等。然后，除去光刻胶和晶种层的其上未形成导电材料的部分。可以通过可接受的灰化或剥离工艺(例如使用氧等离子体等)去除光刻胶。一旦去除了光刻胶，就可以例如通过使用可接受的蚀刻工艺(例如通过湿蚀刻或干蚀刻)来去除晶种层的暴露部分。晶种层的剩余部分和导电材料形成焊盘。在焊盘不同地形成的实施例中，可以使用更多的光刻胶和图案化步骤。
在一些实施例中，电连接器120是焊球和/或凸块，例如球栅阵列(BGA)球、C4微凸块、ENIG形成的凸块、ENEPIG形成的凸块等。电连接器120可以包括诸如焊料、铜、铝、金、镍、银、钯、锡等的导电材料或上述的组合。在一些实施例中，电连接器120首先通过由诸如蒸发、电镀、印刷、焊料转移、球放置等这样的常用方法形成焊料层来形成。一旦已经在结构上形成了焊料层，则可以实施回流以便将材料成形为期望的凸块形状。在另一个实施例中，电连接器120是通过溅射、印刷、电镀、化学镀、CVD等形成的金属柱(例如铜柱)。金属柱可以是无焊料的并且具有基本垂直的侧壁。在一些实施例中，金属覆盖层(未示出)形成在金属柱连接器120的顶部上。金属覆盖层可以包括镍、锡、锡铅、金、铜、银、钯、铟、镍-钯-金、镍-金等或上述的组合，并且可以通过镀敷工艺形成。
电连接器120可以用于接合到附加电组件，该附加电组件可以是半导体衬底、封装件衬底、印刷电路板(PCB)等(参见图15中的300)。
图13示出了图12中的封装件结构的平面图。图12是沿着图13中的线A-A的截面图。如图13所示，伪管芯106沿着围绕封装区域90和封装区域92中的每一个的划线区域94。
在一些实施例中，伪管芯106附接在划线区域94中，并且仅沿着第一方向(例如图13的垂直方向)的划线区域94延伸。在一些实施例中，封装件结构可以具有多于两个管芯88(例如，可以具有四个管芯88)，并且封装件结构可以具有插入在相同区域90和/或区域92的相邻管芯88之间的更多的伪管芯122。伪管芯122类似于伪管芯106，并且这里不再重复描述。
此外，在一些实施例中，伪管芯106附接在划线区域94中并且沿着第一方向和第二方向(例如图13的垂直方向和水平方向)的划线区域94延伸，并且也插入在相同区域90和/或区域92的相邻管芯88之间。
尽管图13示出了在分割之后以形成四个封装件结构的晶圆的四个区域，但是本公开不限于该数量的区域和封装件结构。在其他实施例中，本公开可以包括更多或更少的区域和封装件结构。
在图14中，沿着划线区域94在相邻区域90和区域92之间分割组件96和伪管芯106，以形成组件封装件200，此外，组件封装件200包括管芯68、组件96、管芯88、覆盖结构110和伪管芯106的部分106’。分割可以是通过锯切、划切等。如上所述，伪管芯106有助于减少在分割过程期间和之后引起的应力和翘曲。
在分割过程之后，伪管芯106的保留部分106’具有与组件封装件200的横向延伸区相邻的侧壁表面(例如参见图14和15)。
图15示出了组件封装件200在衬底300上的附接。电连接器120对准衬底300的接合焊盘并且与衬底300的接合焊盘相对放置。电连接器120可以被回流以在衬底300和组件96之间产生接合。衬底300可以包括封装件衬底，诸如其中包括内核的堆积衬底，包括多个层叠的电介质膜的层叠衬底、PCB等。衬底300可以包括与组件封装件相对的电连接器(未示出)，例如焊球，以允许衬底300贴装到另一器件。底部填充材料(未示出)可以分配在组件封装件200和衬底300之间并且围绕电连接器120。底部填充材料可以是任何可接受的材料，例如聚合物、环氧树脂、模制底部填充物等。
另外，一个或多个表面器件140可以连接到衬底300。表面器件140可以用于向组件封装件200或作为整体的封装件提供额外的功能或设计(programming)。在一个实施例中，表面器件140可以包括表面贴装器件(SMD)或集成无源器件(IPD)，IPD包括无源器件，例如电阻器、电感器、电容器、跨接线，这些的组合等，IPD被期望连接到组件封装件200或组件封装件200的其他部分，并与组件封装件200或组件封装件200的其他部分结合使用。根据各种实施例，表面器件140可以放置在衬底300的第一主表面、衬底300的相对主表面或者两者上。
图16示出了根据一些实施例的封装件结构的截面图。图16中的实施例类似于图1至图15中的实施例，除了图16不包括密封剂112。伪管芯106和覆盖结构110可以提供足够的应力减小和保护，使得可以省略密封剂。与前述实施例相同或相似的该实施例的细节在此不再重复。
图17示出了根据一些实施例的封装件结构的截面图。图17中的实施例类似于图1至图15中的实施例，除了图17包括整个封装件结构上方的覆盖结构132并且覆盖结构132粘附到管芯68、管芯88和伪管芯106。粘合剂130和覆盖结构132可以由与前述实施例中所述的粘合剂和覆盖结构类似的材料制成。与前述实施例相同或相似的该实施例的细节在此不再重复。
在图17中，覆盖结构132通过粘合剂130粘附到下面的组件。在一些实施例中，在密封剂112形成之后放置覆盖结构132。尽管未示出覆盖结构110可以包括在管芯88上，其中覆盖结构132覆盖在覆盖结构110和封装件的其它组件上。在一些实施例中，覆盖结构132是晶圆尺寸的，并且一个覆盖结构放置在晶圆的所有区域(例如，90、92等)上方，并且被分割以在每个封装件结构区域中形成单独的覆盖结构132。在其他实施例中，在分割之前，将单独的覆盖结构132放置在晶圆的每个区域(例如，90、92等)上方。
图18示出了根据一些实施例的封装件结构的截面图。图18中的实施例类似于图17中的实施例，除了图18不包括密封剂112。伪管芯106和覆盖结构132可以提供足够的应力减小和保护，使得可以省略密封剂。与前述实施例相同或相似的该实施例的细节在此不再重复。
图19示出了根据一些实施例的封装件结构的截面图。图19中的实施例类似于图1至图15中的实施例，除了图19中的封装件结构500包括管芯400A和管芯400B并且不包括伪管芯。与前述实施例相同或相似的该实施例的细节在此不再重复。
管芯400A可以是逻辑管芯(例如，中央处理单元、图形处理单元、芯片上系统、微控制器等)、电源管理管芯(例如，电源管理集成电路(PMIC)管芯)、射频(RF)管芯、传感器管芯、微电子机械系统(MEMS)管芯、信号处理管芯(例如数字信号处理(DSP)管芯)、前端管芯(例如模拟前端(AFE)管芯)或上述的组合。管芯400A可以包括一个或多个逻辑管芯。管芯400A可以放置并接合在组件96上，类似于上述的管芯68，并且在此不再重复描述。
管芯400B可以是存储器管芯，例如DRAM管芯、SRAM管芯、高带宽存储器(HBM)管芯、混合存储器数据集(HMC)管芯等)。例如，在一些实施例中，管芯400B可以包括存储器管芯和存储器控制器，例如具有存储器控制器的四个或八个存储器管芯的堆叠件。管芯400B可以放置并接合在组件96上，类似于上述的管芯88，并且在此不再重复描述。
根据一些实施例的示例性管芯400B在图20中更详细地示出。主体405可以包括多个堆叠的存储器管芯408和顶部管芯412。堆叠的存储器管芯408可以全部是相同的管芯，或存储器管芯408可以包括不同类型和/或结构的管芯。每个存储器管芯408通过连接器406连接到上面的存储器管芯408和/或下面的存储器管芯408。连接器406可以是微凸块或其它合适的连接器。存储器管芯408可以包括通孔410，通孔410将下面的连接器406连接到上面的连接器406。在一些实施例中，存储器管芯408各自的厚度T4在从约20μm至约100μm的范围内，例如约60μm。
在一些实施例中，主体405可以包括HBM(高带宽存储器)和/或HMC(高存储器数据集)模块，其可以包括连接到逻辑管芯402的一个或多个存储器管芯408。逻辑管芯402可以包括将互连区域(未示出)的导电部件连接到上面的连接器406和存储器管芯408的通孔404。在一些实施例中，逻辑管芯402可以是存储器控制器。互连区域(未示出)可以提供允许主体405的引出接触图案与导电接头91的图案不同的导电图案，允许在放置导电接头91时具有更大的灵活性。导电接头91可以设置在管芯400B的底侧上，并且可以用于将管芯400B物理连接和电连接到组件96。导电接头91可以通过互连区域电连接到逻辑管芯402和/或堆叠的存储器管芯408。可以使用与上述用于导电接头91的方法相同或相似的方法来形成导电接头91，并且这里不再重复描述。
除了顶部管芯412比存储器管芯408更厚之外，顶部管芯412可以是与存储器管芯408相似的管芯(在功能和电路上)。在一些实施例中，顶部管芯412是伪管芯，并且类似于上述覆盖结构110。在一些实施例中，顶部管芯412的厚度T5在从约50μm至约200μm范围内，例如约150μm。在一些实施例中，顶部管芯412具有大于约120μm的厚度T5。已经发现，具有厚度大于约120μm的顶部管芯412的管芯400B增加了封装件结构500的产量，而不需要前述实施例的伪管芯106以及覆盖结构110和覆盖结构132。
如图20所示，主体405可以封装在模制材料414中。模制材料414可以包括模塑料、模制底部填充物、环氧树脂或树脂。
尽管图20示出了具有存储器管芯的管芯400B，但是图19的逻辑管芯400A可具有具有较厚的顶部管芯412的类似的堆叠结构。
图21示出了根据一些实施例的封装件结构的截面图。图21中的实施例类似于图19和图20中的实施例，除了图21中的封装件结构不包括密封剂112。与前述实施例相同或相似的该实施例的细节在此不再重复。
封装件结构的公开实施例包括邻近有源管芯的伪管芯结构，以减少封装件结构的翘曲。封装件结构的翘曲的这种减少使得能够通过降低有源管芯和中介层之间的冷接头的可能性来实现更可靠的封装件结构，在一些实施例中，伪管芯在划线区域中，并且覆盖结构覆盖一些有源管芯，而其它有源管芯未被覆盖结构覆盖。伪管芯可以允许更多地控制密封剂的比例，并且因此可以减小源自热膨胀系数(CTE)失配的应力和翘曲。在一些实施例中，当划线区域中的伪管芯和/或覆盖结构为封装件结构提供足够的支撑和保护时，可以省略密封剂。在一些实施例中，有源管芯是一个或多个管芯的堆叠件(逻辑管芯堆叠件和/或存储器管芯堆叠件)，其中管芯堆叠件的最顶部的管芯比管芯堆叠件的其它管芯更厚。在这些实施例中，可以省略划线区域中的伪管芯和密封剂，因为芯片堆叠件的更厚的顶部管芯为封装件结构提供了足够的支撑和保护。
一个实施例是一种方法，所述方法包括：使用第一电连接器将第一管芯附接到第一组件的第一侧，使用第二电连接器将第二管芯的第一侧附接到所述第一组件的第一侧，将伪管芯附接到所述第一组件的划线区域中的所述第一组件的第一侧，将覆盖结构粘附到所述第二管芯的第二侧，并且分割所述第一组件和所述伪管芯以形成封装件结构。
实施方式可以包括以下特征中的一个或多个。所述方法中，所述第一组件是第三管芯。所述方法还包括：将所述封装件结构贴装到第二衬底，所述第一组件插入在所述第一管芯和所述第二管芯与所述第二衬底之间。分割方法包括锯切穿过所述第一组件和所述伪管芯以形成所述封装件结构。所述方法中，所述第一组件是包括再分布结构的块状衬底，所述第一管芯和所述第二管芯附接到所述再分布结构。所述方法中，所述第一管芯包括一个或多个逻辑管芯，所述第二管芯包括一个或多个存储器管芯。所述方法还包括：形成延伸穿过所述第一组件的通孔，所述第一管芯和所述第二管芯电连接到所述通孔；在所述第一组件的第二侧上形成第三电连接器，所述第二侧与所述第一侧相对，所述第三电连接器电连接到所述通孔；使用所述第三电连接器将所述封装件结构贴装到第二衬底；以及将表面贴装器件(SMD)接合到所述第二衬底。所述方法中，所述伪管芯和所述覆盖结构由硅制成。
一个实施例是一种方法，所述方法包括：使用第一电连接器将第一管芯接合到第一结构的第一侧；使用第二电连接器将存储器管芯接合到所述第一结构的第一侧，所述存储器管芯与所述第一管芯相邻；将第二管芯附接到所述存储器管芯的背面，所述第二管芯的厚度大于所述存储器管芯的厚度；并且分割所述第一结构以形成封装件结构。
实施方式可以包括以下特征中的一个或多个。所述方法中，所述第二管芯的厚度大于或等于120μm。将所述第二管芯附接到所述存储器管芯的背面的方法包括：将所述第二管芯接合到所述存储器管芯的背面，所述第二管芯是与所述存储器管芯电连接的存储器管芯。将所述第二管芯附接到所述存储器管芯的背面的方法包括：使用粘合剂层将所述第二管芯粘附到所述存储器管芯的背面，所述第二管芯由块状材料制成，并且不包括任何有源器件或无源器件。所述方法还包括：在所述第一结构的第一侧与所述第一管芯和所述存储器管芯之间形成底部填充物，并且所述底部填充物围绕所述第一电连接器和所述第二电连接器；并且用密封剂封装所述第一管芯和所述存储器管芯，所述密封剂邻接部分所述底部填充物。所述方法还包括：将多个伪管芯粘附到所述第一结构的划线区域中的所述第一结构的第一侧，其中分割所述第一结构以形成多个封装件结构包括分割所述多个伪管芯。所述方法还包括：在将所述第一管芯接合到第一结构的第一侧之前，在所述第一结构中形成通孔；在所述通孔上形成第一再分布结构，所述第一再分布结构是所述第一结构的第一侧，所述第一再分布结构电连接到所述通孔；使所述第一结构的第二侧变薄以暴露所述通孔的端部，所述第二侧与所述第一侧相对；在所述第一结构的第二侧上形成第二再分布结构，由此形成第一中介层，所述第二再分布结构电连接到所述通孔的暴露的端部；在所述第二再分布结构上形成第三电连接器，并且所述第三电连接器电连接到所述第二再分布结构；将所述第三电连接器接合到第一衬底；以及将表面贴装器件(SMD)接合到与所述第三电连接器中的一个相邻的所述第一衬底。
一个实施例是一种结构，所述结构包括：中介层的第一侧，接合到封装件衬底；第一管芯和第二管芯的有源侧，接合到所述中介层的第二侧，所述第二侧与所述第一侧相对；伪管芯，附接到所述中介层的第二侧，所述伪管芯与所述第一管芯或所述第二管芯中的至少一个相邻；以及覆盖结构，粘附到所述第二管芯的背面。
实施方式可以包括以下特征中的一个或多个。所述结构中，所述伪管芯由硅制成。所述结构中，所述第二管芯包括一个或多个存储器管芯，所述覆盖结构比所述一个或多个存储器管芯中的每一个都厚。所述结构中，所述覆盖结构进一步粘附到所述第一管芯的背面和所述伪管芯的顶表面。
以上论述了若干实施例的特征，使得本领域的技术人员可以更好地理解本发明的各个方面。本领域技术人员应该理解，他们可以很容易地使用本发明作为基础来设计或更改其他用于达到与本文所介绍实施例相同的目的和/或实现相同优点的工艺和结构。本领域技术人员也应该意识到，这些等效结构并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，可以进行多种变化、替换以及改变。

Claims (20)

1.一种形成封装件结构的方法，包括：
使用第一电连接器将第一管芯附接到第一组件的第一侧；
使用第二电连接器将第二管芯的第一侧附接到所述第一组件的第一侧，所述第二管芯的顶面低于所述第一管芯的顶面；
将伪管芯附接到所述第一组件的划线区域中的所述第一组件的第一侧；
将覆盖结构粘附到所述第二管芯的第二侧；以及
分割穿过所述第一组件和所述伪管芯以形成封装件结构。
2.根据权利要求1所述的形成封装件结构的方法，其中，所述第一组件是第三管芯。
3.根据权利要求1所述的形成封装件结构的方法，还包括：
将所述封装件结构贴装到第二衬底，所述第一组件插入在所述第一管芯和所述第二管芯与所述第二衬底之间。
4.根据权利要求1所述的形成封装件结构的方法，其中，所述分割包括锯切穿过所述第一组件和所述伪管芯以形成所述封装件结构。
5.根据权利要求1所述的形成封装件结构的方法，其中，所述第一组件是包括再分布结构的块状衬底，所述第一管芯和所述第二管芯附接到所述再分布结构。
6.根据权利要求1所述的形成封装件结构的方法，其中，所述第一管芯包括一个或多个逻辑管芯，并且其中，所述第二管芯包括一个或多个存储器管芯。
7.根据权利要求1所述的形成封装件结构的方法，还包括：
形成延伸穿过所述第一组件的通孔，所述第一管芯和所述第二管芯电连接到所述通孔；
在所述第一组件的第二侧上形成第三电连接器，所述第二侧与所述第一侧相对，所述第三电连接器电连接到所述通孔；
使用所述第三电连接器将所述封装件结构贴装到第二衬底；以及
将表面贴装器件(SMD)接合到所述第二衬底。
8.根据权利要求1所述的形成封装件结构的方法，所述伪管芯和所述覆盖结构由硅制成。
9.一种形成封装件结构的方法，包括：
使用第一电连接器将第一管芯接合到第一结构的第一侧；
使用第二电连接器将存储器管芯接合到所述第一结构的第一侧，所述存储器管芯与所述第一管芯相邻，所述存储器管芯的顶面低于所述第一管芯的顶面；
将第二管芯附接到所述存储器管芯的背面，所述第二管芯的厚度大于所述存储器管芯的厚度；以及
分割穿过所述第一结构以形成封装件结构。
10.根据权利要求9所述的形成封装件结构的方法，其中，所述第二管芯的厚度大于或等于120μm。
11.根据权利要求9所述的形成封装件结构的方法，其中，将所述第二管芯附接到所述存储器管芯的背面包括将所述第二管芯接合到所述存储器管芯的背面，所述第二管芯是与所述存储器管芯电连接的存储器管芯。
12.根据权利要求9所述的形成封装件结构的方法，其中，将所述第二管芯附接到所述存储器管芯的背面包括使用粘合剂层将所述第二管芯粘附到所述存储器管芯的背面，所述第二管芯由块状材料制成，并且不包括任何有源器件或无源器件。
13.根据权利要求9所述的形成封装件结构的方法，还包括：
在所述第一结构的第一侧与所述第一管芯和所述存储器管芯之间形成底部填充物，并且所述底部填充物围绕所述第一电连接器和所述第二电连接器；以及
使用密封剂封装所述第一管芯和所述存储器管芯，所述密封剂邻接部分所述底部填充物。
14.根据权利要求9所述的形成封装件结构的方法，还包括：
将多个伪管芯粘附到所述第一结构的划线区域中的所述第一结构的第一侧，其中，分割所述第一结构以形成所述封装件结构包括分割所述多个伪管芯。
15.根据权利要求9所述的形成封装件结构的方法，还包括：
在将所述第一管芯接合到第一结构的第一侧之前，在所述第一结构中形成通孔；
在所述通孔上形成第一再分布结构，所述第一再分布结构是所述第一结构的第一侧，所述第一再分布结构电连接到所述通孔；
使所述第一结构的第二侧变薄以暴露所述通孔的端部，所述第二侧与所述第一侧相对；
在所述第一结构的第二侧上形成第二再分布结构，由此形成第一中介层，所述第二再分布结构电连接到所述通孔的暴露的端部；
在所述第二再分布结构上形成第三电连接器，并且所述第三电连接器电连接到所述第二再分布结构；
将所述第三电连接器接合到第一衬底；以及
将表面贴装器件(SMD)接合到与所述第三电连接器中的一个相邻的所述第一衬底。
16.根据权利要求9所述的形成封装件结构的方法，其中，所述第一管芯包括一个或多个逻辑管芯。
17.一种封装件结构，包括：
中介层的第一侧，接合到封装件衬底；
第一管芯和第二管芯的有源侧，接合到所述中介层的第二侧，所述第二侧与所述第一侧相对，所述第二管芯的顶面低于所述第一管芯的顶面；
伪管芯，附接到所述中介层的第二侧，所述伪管芯与所述第一管芯或所述第二管芯中的至少一个相邻；以及
覆盖结构，粘附到所述第二管芯的背面。
18.根据权利要求17所述的封装件结构，其中，所述伪管芯由硅制成。
19.根据权利要求17所述的封装件结构，其中，所述第二管芯包括一个或多个存储器管芯，所述覆盖结构比所述一个或多个存储器管芯中的每一个更厚。
20.根据权利要求17所述的封装件结构，其中，所述覆盖结构进一步粘附到所述第一管芯的背面和所述伪管芯的顶表面。
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