TWI670778B - 封裝結構及其形成方法 - Google Patents

封裝結構及其形成方法 Download PDF

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TWI670778B
TWI670778B TW106135867A TW106135867A TWI670778B TW I670778 B TWI670778 B TW I670778B TW 106135867 A TW106135867 A TW 106135867A TW 106135867 A TW106135867 A TW 106135867A TW I670778 B TWI670778 B TW I670778B
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Taiwan
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die
component
memory
substrate
electrical connector
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TW106135867A
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TW201834086A (zh
Inventor
余振華
胡憲斌
林俊成
盧思維
侯上勇
魏文信
施應慶
吳集錫
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台灣積體電路製造股份有限公司
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Abstract

實施例是一種封裝結構的形成方法，所述方法包括：使 用第一電性連接件將第一晶粒貼合至第一組件的第一側；使用第二電性連接件將第二晶粒的第一側貼合至所述第一組件的所述第一側；將虛擬晶粒在所述第一組件的切割道區中貼合至所述第一組件的所述第一側；將蓋體結構黏著至所述第二晶粒的第二側；以及將所述第一組件及所述虛擬晶粒單體化，以形成封裝結構。

Description

封裝結構及其形成方法
本發明實施例是有關於一種封裝結構及其形成方法。
由於積體電路(integrated circuit，IC)的發展，半導體行業已因各種電子組件(即，電晶體、二極體、電阻器、電容器等)積體密度的持續提升而經歷持續快速成長。在很大程度上，積體密度的該些提升源自於最小特徵尺寸(minimum feature size)的重複減小，此使得能夠將更多的組件整合於給定的區域中。
由於積體組件所佔據的面積主要位於半導體晶圓的表面上，故該些積體度提升本質上是從二維(two-dimensional，2D)層面來看。積體電路的密度增大及對應的面積減小已普遍使得無法將積體電路晶片直接結合至基底上。已使用插入體(interposer)來將球接觸區域自晶片的區域重新分配至更大的插入體區域。此外，插入體已使得能夠達成包括多個晶片的三維(three-dimensional，3D)封裝。亦已開發出包含三維外觀的其他封裝。
本發明實施例的封裝結構的形成方法包括：使用第一電性連接件將第一晶粒貼合至第一組件的第一側；使用第二電性連接件將第二晶粒的第一側貼合至第一組件的第一側；將虛擬晶粒在第一組件的切割道區中貼合至所述第一組件的第一側；將蓋體結構黏著至第二晶粒的第二側；以及將第一組件及虛擬晶粒單體化，以形成封裝結構。
本發明實施例的封裝結構的形成方法包括：使用第一電性連接件將第一晶粒結合至第一結構的第一側；使用第二電性連接件將記憶體晶粒結合至第一結構的第一側，所述記憶體晶粒鄰近第一晶粒；將第二晶粒貼合至記憶體晶粒的背面側，所述第二晶粒具有較所述記憶體晶粒的厚度大的厚度；以及將第一結構單體化以形成封裝結構。
本發明實施例的封裝結構包括：插入體的第一側，結合至封裝基底；第一晶粒的主動側及第二晶粒的主動側，結合至插入體的第二側，所述第二側與第一側相對；虛擬晶粒，貼合至插入體的第二側，所述虛擬晶粒鄰近第一晶粒或第二晶粒中的至少一者；以及蓋體結構，黏著至第二晶粒的背面側。
60、70、300‧‧‧基底
62‧‧‧主動表面
64、84‧‧‧內連線結構
66、86‧‧‧晶粒連接件
68、400B‧‧‧晶粒
72‧‧‧第一表面
74、404、410‧‧‧穿孔
76‧‧‧重佈線結構
77‧‧‧電性連接件
78‧‧‧電性連接件
79‧‧‧電性連接件
80‧‧‧主體
88‧‧‧晶粒
90‧‧‧區
91‧‧‧導電接頭
92‧‧‧區
94‧‧‧切割道區
96‧‧‧組件
100‧‧‧底部填充膠材料
104‧‧‧貼合結構
104A、104B、104C‧‧‧結構
106、122‧‧‧虛擬晶粒
106’‧‧‧部分
108、130‧‧‧黏著劑
110、132‧‧‧蓋體結構
112‧‧‧包封體
116‧‧‧第二表面
117‧‧‧介電層
118‧‧‧金屬化圖案
120‧‧‧電性連接件
140‧‧‧表面元件
200‧‧‧組件封裝
400A‧‧‧晶粒
402‧‧‧邏輯晶粒
405‧‧‧主體
406‧‧‧連接件
408‧‧‧記憶體晶粒
412‧‧‧頂部晶粒
414‧‧‧模塑材料
500‧‧‧封裝結構
A-A‧‧‧線
T1、T3‧‧‧組合厚度
T2、T4、T5‧‧‧厚度
結合附圖閱讀以下詳細說明，會最佳地理解本發明的各個態樣。應注意，根據本領域中的標準慣例，各種特徵並非按比例繪製。事實上，為論述清晰起見，可任意增大或減小各種特徵的尺寸。
圖1至圖15是根據一些實施例的在形成封裝結構的示例性製程中的剖視圖及平面圖。
圖16說明根據一些實施例的封裝結構的剖視圖。
圖17說明根據一些實施例的封裝結構的剖視圖。
圖18說明根據一些實施例的封裝結構的剖視圖。
圖19及圖20說明根據一些實施例的封裝結構的剖視圖。
圖21說明根據一些實施例的封裝結構的剖視圖。
以下揭露內容提供用於實作本發明的不同特徵的諸多不同的實施例或實例。以下闡述組件及排列的具體實例以簡化本揭露內容。當然，該些僅為實例且不旨在進行限制。舉例而言，以下說明中將第一特徵形成於第二特徵「之上」或第二特徵「上」可包括其中第一特徵及第二特徵被形成為直接接觸的實施例，且亦可包括其中第一特徵與第二特徵之間可形成有附加特徵、進而使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。另外，本發明可能在各種實例中重複使用參考編號及/或字母。此種重複使用是出於簡潔及清晰的目的，而非自身表示所論述的各種實施例及/或配置之間的關係。
此外，為易於說明，本文中可能使用例如「位於...之下(beneath)」、「下面(below)」、「下部的(lower)」、「上方(above)」、「上部的(upper)」等空間相對性用語來闡述圖中所示一個部件或特徵與另一(其他)部件或特徵的關係。所述空間相對性用語旨 在除圖中所繪示的定向外亦囊括元件在使用或操作中的不同定向。裝置可具有其他定向(旋轉90度或處於其他定向)且本文中所使用的空間相對性描述語可同樣相應地進行解釋。
可在一種封裝結構的特定上下文中論述本文中所論述的實施例，所述封裝結構在鄰近主動晶粒之處包括虛擬晶粒結構以減少封裝結構的翹曲(warpage)。封裝結構的翹曲的此種減少能夠使得藉由降低主動晶粒與插入體之間存在冷接頭(cold joint)的可能性而達成更可靠的封裝結構。在一些實施例中，虛擬晶粒位於切割道區(scribe line region)中且蓋體結構(cover structure)覆蓋主動晶粒中的一些，而其他主動晶粒則不被蓋體結構覆蓋。虛擬晶粒可使得能夠更大程度地控制包封體的比率且因此可減少因熱膨脹係數(coefficient of thermal expansion，CTE)不匹配而造成的應力及翹曲。在一些實施例中，可省略包封體，乃因切割道區中的虛擬晶粒及/或蓋體結構為封裝結構提供充分的支撐及保護。在一些實施例中，主動晶粒是一或多個晶粒的堆疊(邏輯晶粒堆疊及/或記憶體晶粒堆疊)，所述晶粒堆疊的最頂部晶粒厚於所述晶粒堆疊的其他晶粒。在該些實施例中，可省略切割道區中的虛擬晶粒以及包封體，乃因晶粒堆疊的較厚的頂部晶粒為封裝結構提供充分的支撐及保護。
將參照一種晶粒-插入體-基底(Die-Interposer-Substrate)堆疊封裝的特定上下文來闡述各實施例，所述晶粒-插入體-基底(Die-Interposer-Substrate)堆疊封裝利用了晶圓-基底-晶片 (Chip-on-Wafer-on-Substrate，CoWoS)加工。然而，其他實施例亦可應用於其他封裝(例如，晶粒-晶粒-基底(Die-Die-Substrate)堆疊封裝)及其他加工中。本文中所論述的實施例是為了提供實例以便能夠製成或使用本發明的主題，且此項技術中具有通常知識者將易於理解，可在保持處於不同實施例的預期範圍內的同時作出潤飾。以下各圖中的相同參考編號及符號指代相同組件。儘管方法實施例可被論述成以特定次序執行；然而其他方法實施例可以任何邏輯次序執行。
圖1大體說明形成一或多個晶粒。在加工期間，基底60包括一或多個晶粒68(參照圖2的晶粒68)。在實施例中，基底60為晶圓且可包括塊狀半導體基底、絕緣層上半導體(semiconductor-on-insulator，SOI)基底、多層式半導體基底等。基底60的半導體材料可為：矽；鍺；化合物半導體，包括矽鍺、碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦；合金半導體，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP；或者其組合。亦可使用例如多層式基底或梯度基底(gradient substrate)等其他基底。基底60可為經摻雜的或未經摻雜的。可在基底60的主動表面62中及/或在基底60的主動表面62上形成例如電晶體、電容器、電阻器、二極體等元件。
在主動表面62上形成包括一或多個介電層及相應金屬化圖案的內連線結構64。介電層中的金屬化圖案可例如使用通孔及/或跡線在各元件之間對電性訊號進行路由(route)，且亦可含有例 如電容器、電阻器、電感器等各種電性元件。可對所述各種元件及金屬化圖案進行內連以執行一或多個功能。所述功能可包括記憶體結構(memory structure)、處理結構(processing structure)、感測器(sensor)、放大器(amplifier)、功率分佈(power distribution)、輸入/輸出電路系統(input/output circuitry)等。另外，在內連線結構64中及/或在內連線結構64上形成例如導電柱(例如，包含例如銅等金屬)等晶粒連接件66，以提供與電路系統及元件的外部電性連接。在一些實施例中，晶粒連接件66自內連線結構64突出以形成柱結構，在將晶粒68結合至其他結構時將利用所述柱結構。此項技術中具有通常知識者將知，提供以上實例僅是用於說明目的。可使用適合於給定應用的其他電路系統。
更具體而言，可在內連線結構64中形成金屬間介電質(inter-metallization dielectric，IMD)層。可藉由例如旋轉(spinning)、化學氣相沉積(chemical vapor deposition，CVD)、電漿增強型化學氣相沉積(plasma-enhanced CVD，PECVD)、高密度電漿化學氣相沉積(high-density plasma chemical vapor deposition，HDP-CVD)等此項技術中所習知的任何適宜的方法以例如以下材料來形成金屬間介電質層：低介電常數介電材料(low-K dielectric material)，例如磷矽酸鹽玻璃(phosphosilicate glass，PSG)、硼磷矽酸鹽玻璃(borophosphosilicate glass，BPSG)、氟矽酸鹽玻璃(fluorosilicate glass，FSG)、SiOxCy、旋塗玻璃(Spin-On-Glass)、旋塗聚合物(Spin-On-Polymer)、矽碳材料、 其化合物、其複合物、其組合等。可例如藉由以下方式在金屬間介電質層中形成金屬化圖案：使用微影技術(photolithography technique)在所述金屬間介電質層上沉積光阻材料並將所述光阻材料圖案化以暴露出所述金屬間介電質層的將變成所述金屬化圖案的一些部分。可使用例如非等向性乾蝕刻製程(anisotropic dry etch process)等蝕刻製程在金屬間介電質層中形成與所述金屬間介電質層的被暴露出的部分對應的凹陷部及/或開口。可將凹陷部及/或開口與擴散障壁層(diffusion barrier layer)對齊並使用導電材料填充所述凹陷部及/或開口。擴散障壁層可包括藉由原子層沉積(atomic layer deposition，ALD)等而沉積的TaN、Ta、TiN、Ti、CoW等的一或多個層，且導電材料可包括藉由化學氣相沉積、物理氣相沉積(physical vapor deposition，PVD)等而沉積的銅、鋁、鎢、銀及其組合等。可例如使用化學機械研磨(chemical mechanical polish，CMP)等來移除位於金屬間介電質層上的任何過量的擴散障壁層及/或導電材料。
在圖2中，將包括內連線結構64的基底60單體化成各別的晶粒68。通常，儘管各晶粒可具有不同的電路系統，然而各晶粒68含有相同的電路系統(例如，元件及金屬化圖案)。可藉由鋸切(sawing)、切割(dicing)等來進行單體化。
晶粒68可為邏輯晶粒(例如，中央處理單元、圖形處理單元、系統晶片(system-on-a-chip)、微控制器等)、記憶體晶粒(例如，動態隨機存取記憶體(dynamic random access memory， DRAM)晶粒、靜態隨機存取記憶體(static random access memory，SRAM)晶粒等)、電力管理晶粒(例如，電力管理積體電路(power management integrated circuit，PMIC)晶粒)、射頻(radio frequency，RF)晶粒、感測器晶粒、微機電系統(micro-electro-mechanical-system，MEMS)晶粒、訊號處理晶粒(例如，數位訊號處理(digital signal processing，DSP)晶粒)、前端晶粒(例如，類比前端(analog front-end，AFE)晶粒)等或其組合。此外，在一些實施例中，晶粒68可為不同尺寸(例如，不同高度及/或表面積)，且在其他實施例中，晶粒68可為相同尺寸(例如，相同高度及/或表面積)。
圖3說明形成一或多個組件96的第一側。如圖3中所示，可自基底70形成一或多個組件96。組件96可為插入體或另一晶粒。基底70可為晶圓。基底70可包括塊狀半導體基底、絕緣層上半導體基底、多層式半導體基底等。基底70的半導體材料可為：矽；鍺；化合物半導體，包括矽鍺、碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦；合金半導體，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP；或者其組合。亦可使用例如多層式基底或梯度基底(gradient substrate)等其他基底。基底70可為經摻雜的或未經摻雜的。可在基底70的第一表面72(其亦可稱作主動表面)中及/或在基底70的第一表面72上形成例如電晶體、電容器、電阻器、二極體等元件。在其中組件96為插入體的實施例中，儘管插入體可包括形成於第一表面72 中及/或第一表面72上及/或形成於重佈線結構76中的被動元件，然而通常組件96中將不包括主動元件。
形成自基底70的第一表面72延伸至基底70中的穿孔(through-via，TV)74。有時亦將穿孔74稱作基底穿孔，或者當基底70為矽基底時將穿孔74稱作矽穿孔。可藉由以下方式來形成穿孔74：藉由例如蝕刻、碾磨(milling)、雷射技術、其組合及/或類似技術等在基底70中形成凹陷部。可例如使用氧化技術在凹陷部中形成薄的介電材料。可例如藉由化學氣相沉積、原子層沉積、物理氣相沉積、熱氧化、其組合及/或類似技術等在基底70的前面側之上及在開口中共形地沉積薄的障壁層。障壁層可包含氮化物或氮氧化物，例如氮化鈦、氮氧化鈦、氮化鉭、氮氧化鉭、氮化鎢、其組合及/或類似物。可在薄的障壁層之上及在開口中沉積導電材料。可藉由電化學鍍覆製程(electro-chemical plating process)、化學氣相沉積、原子層沉積、物理氣相沉積、其組合及/或類似技術來形成導電材料。導電材料的實例為銅、鎢、鋁、銀、金、其組合及/或類似物。藉由例如化學機械研磨自基底70的前面側移除過量的導電材料及障壁層。因此，穿孔74可包含導電材料及位於所述導電材料與基底70之間的薄的障壁層。
在基底70的第一表面72之上形成重佈線結構76，並使用重佈線結構76將積體電路元件(若有)及/或穿孔74電性連接於一起及/或將積體電路元件(若有)及/或穿孔74電性連接至外部元件。重佈線結構76可包括一或多個介電層及位於所述介電層 中的相應金屬化圖案。金屬化圖案可包括通孔及/或跡線以將任意元件及/或穿孔74內連於一起及/或將任意元件及/或穿孔74內連至外部元件。有時將金屬化圖案稱作重佈線(Redistribution Line，RDL)。介電層可包含氧化矽、氮化矽、碳化矽、氮氧化矽、低介電常數介電材料(例如，磷矽酸鹽玻璃、硼磷矽酸鹽玻璃、氟矽酸鹽玻璃、SiOxCy、旋塗玻璃、旋塗聚合物、矽碳材料、其化合物、其複合物、其組合等)。可藉由例如旋轉、化學氣相沉積、電漿增強型化學氣相沉積、高密度電漿化學氣相沉積等此項技術中所習知的任何適宜的方法來沉積介電層。可例如藉由以下方式在介電層中形成金屬化圖案：使用微影技術在所述介電層上沉積光阻材料並將所述光阻材料圖案化以暴露出所述介電層的將變成所述金屬化圖案的一些部分。可使用例如非等向性乾蝕刻製程等蝕刻製程在介電層中形成與所述介電層的被暴露出的部分對應的凹陷部及/或開口。可將凹陷部及/或開口與擴散障壁層對齊並使用導電材料填充所述凹陷部及/或開口。擴散障壁層可包括藉由原子層沉積等而沉積的TaN、Ta、TiN、Ti、CoW等的一或多個層，且導電材料可包括藉由化學氣相沉積、物理氣相沉積等而沉積的銅、鋁、鎢、銀及其組合等。可例如使用化學機械研磨等來移除位於介電層上的任何過量的擴散障壁層及/或導電材料。
在導電接墊上的重佈線結構76的頂表面處形成電性連接件77/78。在一些實施例中，導電接墊包括凸塊下金屬(under bump metallurgy，UBM)。在所示實施例中，在重佈線結構76的介電層 的開口中形成接墊。在另一實施例中，接墊(凸塊下金屬)可延伸穿過重佈線結構76的介電層的開口且亦延伸跨越重佈線結構76的頂表面。作為形成接墊的實例，至少在重佈線結構76的介電層中的開口中形成晶種層(圖中未示出)。在一些實施例中，晶種層為金屬層，所述金屬層可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層及位於所述鈦層之上的銅層。可使用例如物理氣相沉積等來形成晶種層。接著在晶種層上形成光阻並將所述光阻圖案化。可藉由旋轉塗佈(spin coating)等來形成光阻且可將所述光阻暴露至光以進行圖案化。光阻的圖案對應於接墊。所述圖案化會形成貫穿光阻的開口以暴露出晶種層。在光阻的開口中及在晶種層的被暴露出的部分上形成導電材料。可藉由鍍覆(例如電鍍(electroplating)或無電鍍覆(electroless plating))等來形成導電材料。所述導電材料可包括金屬，如銅、鈦、鎢、鋁等。接著，移除光阻以及晶種層的上面未形成有導電材料的一些部分。可藉由例如使用氧電漿等的可接受的灰化製程(ashing process)或剝除製程(stripping process)來移除光阻。一旦光阻被移除，則例如使用可接受的蝕刻製程(例如藉由濕式蝕刻(wet etching)或乾式蝕刻(dry etching))來移除晶種層的被暴露出的部分。晶種層的其餘部分與導電材料形成接墊。在其中以不同方式形成接墊的實施例中，可利用更多的光阻及圖案化步驟。
在一些實施例中，電性連接件77/78包括金屬柱(諸如電 性連接件77)，金屬柱(諸如電性連接件77)之上具有金屬頂蓋層(諸如電性連接件78)，金屬頂蓋層(諸如電性連接件78)可為焊料頂蓋。有時將包括柱(諸如電性連接件77)及頂蓋層(諸如電性連接件78)的電性連接件77/78稱作微凸塊。在一些實施例中，金屬柱(諸如電性連接件77)包括例如銅、鋁、金、鎳、鈀、類似物或其組合等導電材料，且可藉由濺鍍(sputtering)、印刷、電鍍、無電鍍覆、化學氣相沉積等來形成。金屬柱(諸如電性連接件77)可為無焊料的(solder free)且具有實質上垂直的側壁。在一些實施例中，在金屬柱(諸如電性連接件77)的頂部上形成金屬頂蓋層(諸如電性連接件78)。金屬頂蓋層(諸如電性連接件78)可包含鎳、錫、錫-鉛、金、銅、銀、鈀、銦、鎳-鈀-金、鎳-金、類似物或其組合，且可藉由鍍覆製程來形成。
在另一實施例中，電性連接件77/78不包括金屬柱，且電性連接件77/78是例如受控塌陷晶片連接(controlled collapse chip connection，C4)、無電鍍鎳浸金(electroless nickel immersion Gold，ENIG)、無電鍍鎳鈀浸金技術(electroless nickel electroless palladium immersion gold technique，ENEPIG)形成的凸塊等焊料球及/或凸塊。在此實施例中，凸塊電性連接件77/78可包含例如焊料、銅、鋁、金、鎳、銀、鈀、錫、類似物或其組合等導電材料。在此實施例中，藉由以下方式來形成電性連接件77/78：首先藉由例如蒸鍍(evaporation)、電鍍、印刷、焊料轉移(solder transfer)、植球(ball placement)等常用方法形成焊料層。一旦已 在結構上形成焊料層，則可執行迴焊(reflow)以將材料造形成所期望的凸塊形狀。
在圖4中，例如利用晶粒68及晶粒88上的電性連接件77/78及金屬柱(諸如電性連接件79)藉由倒裝晶片結合(flip-chip bonding)而將各所述晶粒貼合至組件96的第一側以形成導電接頭91。金屬柱(諸如電性連接件79)可相似於金屬柱(諸如電性連接件77)且本文中不再對其予以贅述。可使用例如拾取及放置工具(pick-and-place tool)將晶粒68及晶粒88放置於電性連接件77/78上。在一些實施例中，在晶粒68及晶粒88的金屬柱(諸如電性連接件77)(如圖3中所示)、金屬柱(諸如電性連接件79)上、或在金屬柱(諸如電性連接件77)與金屬柱(諸如電性連接件79)二者上形成金屬頂蓋層(諸如電性連接件78)。
可藉由與以上參照晶粒68所述的加工相似的加工來形成晶粒88。在一些實施例中，晶粒88包括一或多個記憶體晶粒，例如記憶體晶粒堆疊(例如，動態隨機存取記憶體晶粒、靜態隨機存取記憶體晶粒、高頻寬記憶體(High-Bandwidth Memory，HBM)晶粒、混合記憶體立方(Hybrid Memory Cube，HMC)晶粒等)。在記憶體晶粒堆疊實施例中，晶粒88可包括記憶體晶粒與記憶體控制器二者，例如(舉例而言，具有記憶體控制器的四個或八個記憶體晶粒的堆疊)。此外，在一些實施例中，晶粒88可為不同尺寸(例如，不同高度及/或表面積)，且在其他實施例中，晶粒88可為相同尺寸(例如，相同高度及/或表面積)。
晶粒88包括主體80、內連線結構84及晶粒連接件86。晶粒88的主體80可包括任何數目的晶粒、基底、電晶體、主動元件、被動元件等。在實施例中，主體80可包括塊狀半導體基底、絕緣層上半導體(SOI)基底、多層式半導體基底等。主體80的半導體材料可為：矽；鍺；化合物半導體，包括矽鍺、碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦；合金半導體，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP；或者其組合。亦可使用例如多層式基底或梯度基底等其他基底。主體80可為經摻雜的或未經摻雜的。可在主動表面中及/或在主動表面上形成例如電晶體、電容器、電阻器、二極體等元件。
在主動表面上形成包括一或多個介電層及相應金屬化圖案的內連線結構84。介電層中的金屬化圖案可例如使用通孔及/或跡線在各元件之間對電性訊號進行路由，且亦可含有例如電容器、電阻器、電感器等各種電性元件。可對各種元件及金屬化圖案進行內連以執行一或多個功能。所述功能可包括記憶體結構、處理結構、感測器、放大器、功率分佈、輸入/輸出電路系統等。另外，在內連線結構84中及/或在內連線結構84上形成例如導電柱(例如，包含例如銅等金屬)等晶粒連接件86，以提供與電路系統及元件的外部電性連接。在一些實施例中，晶粒連接件86自內連線結構84突出以形成柱結構，在將晶粒88結合至其他結構時將利用所述柱結構。此項技術中具有通常知識者將知，提供以上實例僅是用於說明目的。可使用適合於給定應用的其他電路系 統。
更具體而言，可在內連線結構64中形成金屬間介電質層。可藉由例如旋轉、化學氣相沉積、電漿增強型化學氣相沉積、高密度電漿化學氣相沉積等此項技術中所習知的任何適宜的方法以例如以下材料來形成金屬間介電質層：低介電常數介電材料，例如磷矽酸鹽玻璃、硼磷矽酸鹽玻璃、氟矽酸鹽玻璃、SiOxCy、旋塗玻璃、旋塗聚合物、矽碳材料、其化合物、其複合物、其組合等。可例如藉由以下方式在金屬間介電質層中形成金屬化圖案：使用微影技術在所述金屬間介電質層上沉積光阻材料並將所述光阻材料圖案化以暴露出所述金屬間介電質層的將變成所述金屬化圖案的一些部分。可使用例如非等向性乾蝕刻製程等蝕刻製程在金屬間介電質層中形成與所述金屬間介電質層的被暴露出的部分對應的凹陷部及/或開口。可將凹陷部及/或開口與擴散障壁層對齊並使用導電材料填充所述凹陷部及/或開口。擴散障壁層可包括藉由原子層沉積等而沉積的氮化鉭、鉭、氮化鈦、鈦、鈷鎢、類似物或其組合的一或多個層。金屬化圖案的導電材料可包括藉由化學氣相沉積、物理氣相沉積等而沉積的銅、鋁、鎢、銀及其組合等。可例如使用化學機械研磨等來移除位於金屬間介電質層上的任何過量的擴散障壁層及/或導電材料。
在其中晶粒連接件66及86分別自內連線結構64及84突出的實施例中，晶粒68及88可不包括金屬柱(諸如電性連接件79)，乃因突出的晶粒連接件66及86可用作金屬頂蓋層(諸如 電性連接件78)的柱。
導電接頭91經由內連線結構84及64以及晶粒連接件86及66將晶粒68及晶粒88中的電路分別電性耦合至組件96中的重佈線結構76及穿孔74。
在一些實施例中，在結合電性連接件77/78之前，使用例如免清洗焊劑(no-clean flux)等焊劑(圖中未示出)塗佈電性連接件77/78。可將電性連接件77/78浸入焊劑中或可將所述焊劑噴射至電性連接件77/78上。在另一實施例中，可將焊劑塗覆至電性連接件79/78。在一些實施例中，在電性連接件77/78及/或79/78被迴焊之前電性連接件77/78及/或79/78上可形成有環氧樹脂焊劑(圖中未示出)，所述環氧樹脂焊劑的環氧樹脂部分中的至少一些環氧樹脂部分將在晶粒68及晶粒88貼合至組件96之後存留。此一存留的環氧樹脂部分可充當底部填充膠以減小應力並保護因迴焊電性連接件77/78/79而形成的接頭。
晶粒68及88與組件96之間的結合可為焊料結合或直接金屬-金屬(例如銅-銅或錫-錫)結合。在實施例中，藉由迴焊製程來將晶粒68及晶粒88接合至組件96。在此回焊製程期間，電性連接件77/78/79分別接觸晶粒連接件66及86，且重佈線結構76的接墊將晶粒68及晶粒88實體地耦合至且電性耦合至組件96。在結合製程之後，可在金屬柱(諸如電性連接件77、79)與金屬頂蓋層(諸如電性連接件78)的介面處形成金屬間介電質層(圖中未示出)。
在圖4及後續各圖中，將說明分別用於形成第一封裝及第二封裝的第一封裝區90及第二封裝區92。切割道區94位於鄰近的封裝區之間。如圖4中所示，在第一封裝區90及第二封裝區92中的每一者中貼合晶粒68及多個晶粒88。
在一些實施例中，晶粒68為系統晶片(SoC)或圖形處理單元(GPU)，且晶粒88為可被晶粒68利用的記憶體晶粒。在實施例中，晶粒88為堆疊記憶體晶粒。舉例而言，堆疊記憶體晶粒88可包括低功率(low-power)雙倍資料速率(double data rate，DDR)記憶體模組，例如LPDDR1、LPDDR2、LPDDR3、LPDD4或類似的記憶體模組。
在圖5中，在晶粒68、晶粒88、重佈線結構76之間的間隙中且環繞導電接頭91分配底部填充膠材料100。在圖5及後續各圖中，對導電接頭91中的每一者的圖示被示出為包括單一結構，但如圖4中所示，導電接頭91中的每一者可包括兩個金屬柱(諸如電性連接件77、79)，所述兩個金屬柱(諸如電性連接件77、79)之間具有金屬層(諸如電性連接件78)。底部填充膠材料100可沿晶粒68及晶粒88的側壁向上延伸。底部填充膠材料100可為例如聚合物、環氧樹脂、模塑底部填充膠等任何可接受的材料。可在貼合晶粒68及88之後藉由毛細流動製程(capillary flow process)來形成底部填充膠材料100，或者可在貼合晶粒68及88之前藉由適宜的沉積方法來形成底部填充膠材料100。
在圖6A及圖6B中，使用貼合結構104在切割道區94 中鄰近晶粒88處黏著虛擬晶粒106。圖6A及圖6B說明貼合結構104的兩個實施例。將虛擬晶粒106放置於切割道區94中可幫助防止在將第一封裝區90中的封裝及第二封裝區92中的封裝單體化(參見圖14)期間及之後出現翹曲。虛擬晶粒106可幫助減少翹曲的一種方式為在實際單體化製程期間對封裝提供支撐。虛擬晶粒106可防止翹曲的另一種方式為減少組件96與後續形成的包封體112之間的熱膨脹係數(CTE)不匹配(若存在)(參見圖8)，乃因虛擬晶粒106具有與組件96相似的熱膨脹係數且虛擬晶粒106會減少封裝中所必需的包封體112的量。
使用貼合結構104將虛擬晶粒106貼合至組件96。在一些實施例中，貼合結構104為將虛擬晶粒106貼合至組件的一或多個微凸塊。在一些實施例中，貼合結構104為將虛擬晶粒106黏著至組件96的黏著劑。虛擬晶粒106可由矽、介電材料、類似物或其組合製成。在一些實施例中，虛擬晶粒106為已作為虛擬晶粒106而回收利用的實際上有缺陷的主動晶粒。在一些實施例中，虛擬晶粒106為塊狀材料且不包括任何主動元件或被動元件。在一些實施例中，虛擬晶粒106的頂表面與晶粒68的背面側齊平。
在圖6A中，說明微凸塊貼合結構104實施例。在此實施例中，在虛擬晶粒106的底表面、組件96的頂表面上、或在虛擬晶粒106的底表面與組件96的頂表面二者上形成微凸塊(諸如貼合結構104)。可在形成用於結合晶粒68及88的微凸塊(例如，電性連接件77/78/79)的同時形成微凸塊(諸如貼合結構104)。 具體而言，貼合結構104的結構104A、104B及104C可分別與電性連接件77、78及79的結構相同，且本文中不再對該些結構予以贅述。微凸塊(諸如貼合結構104)將虛擬晶粒106結合至組件96(例如，圖示中的重佈線結構76)。可對虛擬晶粒106的微凸塊(諸如貼合結構104)與晶粒68及88的電性連接件77/78/79一起進行回焊。可使用例如拾取及放置工具將虛擬晶粒106放置於微凸塊(諸如貼合結構104)上。可在結合虛擬晶粒106之前或之後將底部填充膠材料100固化。
在圖6B中，說明黏著貼合結構104實施例。在此實施例中，黏著劑(諸如貼合結構104)位於虛擬晶粒106的底表面上且將虛擬晶粒106黏著至組件96(例如，圖示中的重佈線結構76)。黏著劑(諸如貼合結構104)可為任何適宜的黏著劑、環氧樹脂、晶粒貼合膜(die attach film，DAF)等。可將黏著劑(諸如貼合結構104)塗覆至虛擬晶粒106的底表面或可將黏著劑(諸如貼合結構104)塗覆於重佈線結構76的表面之上。可使用例如拾取及放置工具藉由黏著劑(諸如貼合結構104)而將虛擬晶粒106黏著至重佈線結構76。可在黏著虛擬晶粒106之前或之後將底部填充膠材料100固化。
在圖7中，在晶粒88的背面側上黏著蓋體結構110。蓋體結構110會顯著地減小晶粒88上的應力且可在後續加工期間保護晶粒88。在一些實施例中，晶粒88包括一或多個記憶體晶粒的堆疊且蓋體結構110厚於晶粒88的所述一或多個記憶體晶粒中的 每一者。在一些實施例中，蓋體結構110具有在與基底70的主表面垂直的方向上量測的厚度，所述厚度介於約50微米(μm)至約200微米範圍內(例如，約100微米)。
在一些實施例中，蓋體結構110的頂表面與晶粒68的背面側及虛擬晶粒106的頂表面齊平。在一些實施例中，使用黏著劑108來黏著蓋體結構110。蓋體結構110可由矽、介電材料、類似物或其組合製成。蓋體結構110可包含與虛擬晶粒106相同的材料。在一些實施例中，蓋體結構110為已作為蓋體結構110而回收利用的實際上有缺陷的主動晶粒。在一些實施例中，蓋體結構110為塊狀材料且不包括任何主動元件或被動元件。黏著劑108位於蓋體結構110的底表面上且將蓋體結構110黏著至晶粒88。黏著劑108可為任何適宜的黏著劑、環氧樹脂、晶粒貼合膜等。可使用例如拾取及放置工具藉由黏著劑108而將蓋體結構110黏著至晶粒88。
在圖8中，在各個組件上形成包封體112。包封體112可為模塑化合物、環氧樹脂等，且可藉由壓縮模塑(compression molding)、轉移模塑(transfer molding)等來塗覆。執行固化步驟以固化包封體112，其中所述固化可為熱固化、紫外光(Ultra-Violet，UV)固化等。在一些實施例中，將晶粒68、虛擬晶粒106及/或蓋體結構110埋置於包封體112中，且在固化包封體112之後，可執行例如磨製(grinding)等平面化步驟(planarization step)以移除包封體112的過量部分，該些過量部 分位於晶粒68的頂表面、虛擬晶粒106的頂表面及/或蓋體結構110的頂表面之上。因此，晶粒68的頂表面、虛擬晶粒106的頂表面及/或蓋體結構110的頂表面被暴露出且與包封體112的頂表面齊平。
圖9至圖12說明形成組件96的第二側。在圖9中，將圖8所示結構翻轉以為形成組件96的第二側做準備。儘管圖中未示出，然而可將所述結構放置於載板或支撐結構上以進行圖9至圖12所示製程。如圖9中所示，在加工的此階段處，組件96的基底70及重佈線結構76具有組合厚度T1，組合厚度T1介於約750微米至約800微米範圍內(例如，約775微米)。虛擬晶粒106(包括貼合結構104)具有厚度T2，厚度T2介於約750微米至約800微米範圍內(例如，約760微米)。在一些實施例中，晶粒68及88(包括用於晶粒88的導電接頭91及蓋體結構110)中的一者或晶粒68與88二者具有厚度T2。
在圖10中，對基底70的第二側執行薄化製程以將基底70薄化至第二表面116直至暴露出穿孔74。薄化製程可包括蝕刻製程、磨製製程、類似製程或其組合。在一些實施例中，在薄化製程之後，組件96的基底70及重佈線結構76具有組合厚度T3，組合厚度T3介於約20微米至約180微米範圍內(例如，約100微米)。
在圖11中，在基底70的第二表面116上形成重佈線結構，並使用所述重佈線結構將各穿孔74電性連接於一起及/或將穿 孔74電性連接至外部元件。重佈線結構包括一或多個介電層117及位於所述一或多個介電層117中的金屬化圖案118。金屬化圖案可包括通孔及/或跡線以將各穿孔74內連於一起及/或將穿孔74內連至外部元件。有時將金屬化圖案118稱作重佈線(RDL)。介電層117可包含氧化矽、氮化矽、碳化矽、氮氧化矽、低介電常數介電材料(例如，磷矽酸鹽玻璃、硼磷矽酸鹽玻璃、氟矽酸鹽玻璃、SiOxCy、旋塗玻璃、旋塗聚合物、矽碳材料、其化合物、其複合物、其組合等)。可藉由例如旋轉、化學氣相沉積、電漿增強型化學氣相沉積、高密度電漿化學氣相沉積等此項技術中所習知的任何適宜的方法來沉積介電層117。可例如藉由以下方式在介電層117中形成金屬化圖案118：使用微影技術在介電層117上沉積光阻材料並將所述光阻材料圖案化以暴露出介電層117的將變成金屬化圖案118的部分。可使用例如非等向性乾蝕刻製程等蝕刻製程在介電層117中形成與介電層117的被暴露出的部分對應的凹陷部及/或開口。可將凹陷部及/或開口與擴散障壁層對齊並使用導電材料填充所述凹陷部及/或開口。擴散障壁層可包括藉由原子層沉積等而沉積的TaN、Ta、TiN、Ti、CoW等的一或多個層，且導電材料可包括藉由化學氣相沉積、物理氣相沉積等而沉積的銅、鋁、鎢、銀及其組合等。可例如使用化學機械研磨等來移除位於介電層上的任何過量的擴散障壁層及/或導電材料。
在圖12中，亦在金屬化圖案118上形成電性耦合至穿孔74的電性連接件120。在金屬化圖案118上的重佈線結構的頂表 面處形成電性連接件120。在一些實施例中，金屬化圖案118包括凸塊下金屬。在所示實施例中，在重佈線結構的介電層117的開口中形成接墊。在另一實施例中，接墊(凸塊下金屬)可延伸穿過重佈線結構的介電層117的開口且亦延伸跨越所述重佈線結構的頂表面。
作為形成接墊的實例，至少在重佈線結構的介電層117中的一者中的開口中形成晶種層(圖中未示出)。在一些實施例中，晶種層為金屬層，所述金屬層可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層及位於所述鈦層之上的銅層。可使用例如物理氣相沉積等來形成晶種層。接著在晶種層上形成光阻並將所述光阻圖案化。可藉由旋轉塗佈等來形成光阻且可將所述光阻暴露至光以進行圖案化。光阻的圖案對應於接墊。所述圖案化會形成貫穿光阻的開口以暴露出晶種層。在光阻的開口中及在晶種層的被暴露出的部分上形成導電材料。可藉由鍍覆(例如電鍍或無電鍍覆)等來形成導電材料。所述導電材料可包括金屬，如銅、鈦、鎢、鋁等。接著，移除光阻以及晶種層的上面未形成有導電材料的一些部分。可藉由例如使用氧電漿等的可接受的灰化製程或剝除製程來移除光阻。一旦光阻被移除，則例如使用可接受的蝕刻製程(例如藉由濕式蝕刻或乾式蝕刻)來移除晶種層的被暴露出的部分。晶種層的其餘部分與導電材料形成接墊。在其中以不同方式形成接墊的實施例中，可利用更多的光阻及圖案化步驟。
在一些實施例中，電性連接件120為例如球柵陣列封裝(ball grid array，BGA)球、受控塌陷晶片連接微凸塊、無電鍍鎳浸金形成的凸塊、無電鍍鎳鈀浸金技術形成的凸塊等焊料球及/或凸塊。電性連接件120可包含例如焊料、銅、鋁、金、鎳、銀、鈀、錫、類似物或其組合等導電材料。在一些實施例中，藉由以下方式來形成電性連接件120：首先藉由例如蒸鍍、電鍍、印刷、焊料轉移、植球等常用方法形成焊料層。一旦已在結構上形成焊料層，則可執行迴焊以將材料造形成所期望的凸塊形狀。在另一實施例中，電性連接件120為藉由濺鍍、印刷、電鍍、無電鍍覆、化學氣相沉積等而形成的金屬柱(例如銅柱)。金屬柱可為無焊料的且具有實質上垂直的側壁。在一些實施例中，在金屬柱連接件(諸如電性連接件120)的頂部上形成金屬頂蓋層(圖中未示出)。金屬頂蓋層可包含鎳、錫、錫-鉛、金、銀、鈀、銦、鎳-鈀-金、鎳-金等或其組合且可藉由鍍覆製程來形成。
可使用電性連接件120來結合至另一電性組件，所述另一電性組件可為半導體基底、封裝基底、印刷電路板(Printed Circuit Board，PCB)等(參見圖15中的基底300)。
圖13說明圖12中的封裝結構的平面圖。圖12是沿圖13中的線A-A的剖視圖。如圖13中所示，虛擬晶粒106沿切割道區94環繞封裝區90及92中的每一者。
在一些實施例中，在切割道區94中貼合虛擬晶粒106且虛擬晶粒106僅沿著沿第一方向(例如，圖13所示垂直方向)的 切割道區94延伸。在一些實施例中，封裝結構可具有多於兩個晶粒88(例如，可具有四個晶粒88)且封裝結構可具有更多虛擬晶粒122夾置於同一區90及/或92的鄰近晶粒88之間。虛擬晶粒122相似於虛擬晶粒106且本文中不再對其予以贅述。
此外，在一些實施例中，在切割道區94中貼合虛擬晶粒106且虛擬晶粒106沿著沿第一方向及第二方向(例如，圖13所示垂直方向與水平方向二者)的切割道區94延伸且亦夾置於同一區90及/或92的鄰近晶粒88之間。
儘管圖13示出晶圓的四個區在單體化之後形成四個封裝結構，然而本發明並非僅限於此數量的區及封裝結構。在其他實施例中，本發明可包括更多個或更少個區及封裝結構。
在圖14中，沿切割道區94在鄰近的區90與92之間將組件96及虛擬晶粒106單體化以形成組件封裝200，組件封裝200包括晶粒68、組件96、晶粒88、蓋體結構110、及虛擬晶粒106的一些部分106’等。可藉由鋸切、切割等來進行單體化。如以上所論述，虛擬晶粒106幫助減少在單體化製程期間及之後造成的應力及翹曲。
在單體化製程之後，虛擬晶粒106的其餘部分106’具有與組件封裝200的側向伸展部相連的側壁表面(參見例如圖14及圖15)。
圖15說明將組件封裝200貼合於基底300上。將電性連接件120對齊至基底300的結合接墊且將電性連接件120放置成 挨靠基底300的所述結合接墊。可對電性連接件120進行回焊以在基底300與組件96之間形成結合件。基底300可包括封裝基底，例如其中包括芯體(core)的增層基底(build-up substrate)、包括多個疊層介電膜的疊層體基底、印刷電路板等。基底300可包括與組件封裝相對的例如焊料球等電性連接件(圖中未示出)以使得基底300能夠安裝至另一元件。可在組件封裝200與基底300之間且環繞電性連接件120分配底部填充膠材料(圖中未示出)。底部填充膠材料可為例如聚合物、環氧樹脂、模塑底部填充膠等任何可接受的材料。
另外，可將一或多個表面元件140連接至基底300。可使用表面元件140來向組件封裝200或整個所述封裝提供額外的功能或對組件封裝200或整個所述封裝進行程式設計。在實施例中，表面元件140可為表面安裝元件(surface mount device，SMD)或積體被動元件(integrated passive device，IPD)，所述積體被動元件(IPD)包括例如電阻器、電感器、電容器、跨接線(jumper)、該些的組合等期望連接至組件封裝200或所述封裝的其他零件並與組件封裝200或所述封裝的其他零件結合利用的被動元件。根據各種實施例，可將表面元件140放置於基底300的第一主表面上、基底300的相對的主表面上、或放置於基底300的所述第一主表面及基底300的所述相對的主表面二者上。
圖16說明根據一些實施例的封裝結構的剖視圖。除圖16不包括包封體112以外，圖16中的實施例相似於圖1至圖15中 的實施例。虛擬晶粒106的部分106’及蓋體結構110可充分減小應力及提供保護，進而使得可省略包封體。本文中不再對此實施例的與前面的實施例相同或相似的細節予以贅述。
圖17說明根據一些實施例的封裝結構的剖視圖。除圖17包括位於整個封裝結構之上且黏著至晶粒68、晶粒88及虛擬晶粒106的部分106’的蓋體結構132以外，圖17中的實施例相似於圖1至圖15中的實施例。黏著劑130及蓋體結構132可由與以上在前面的實施例中所闡述的黏著劑及蓋體結構相似的材料製成。本文中不再對此實施例的與前面的實施例相同或相似的細節予以贅述。
在圖17中，蓋體結構132藉由黏著劑130而黏著至下伏組件。在一些實施例中，蓋體結構132是在形成包封體112之後放置。儘管圖中未示出，然而晶粒88上可包括蓋體結構110，蓋體結構132上覆於蓋體結構110及所述封裝的其他組件上。在一些實施例中，蓋體結構132具有晶圓尺寸，且一個蓋體結構放置於晶圓的所有區(例如，區90、92等)之上並被單體化以在封裝結構區中的每一者中形成各別的蓋體結構132。在其他實施例中，在單體化之前，各別的蓋體結構132放置於晶圓的各個區(例如，區90、92等)中的每一者之上。
圖18說明根據一些實施例的封裝結構的剖視圖。除圖18不包括包封體112以外，圖18中的實施例相似於圖17中的實施例。虛擬晶粒106的部分106’及蓋體結構132可充分減小應力及 提供保護，進而使得可省略包封體。本文中不再對此實施例的與前面的實施例相同或相似的細節予以贅述。
圖19說明根據一些實施例的封裝結構的剖視圖。除圖19中的封裝結構500包括晶粒400A及400B且不包括虛擬晶粒以外，圖19中的實施例相似於圖1至圖15中的實施例。本文中不再對此實施例的與前面的實施例相同或相似的細節予以贅述。
晶粒400A可為邏輯晶粒(例如，中央處理單元、圖形處理單元、系統晶片、微控制器等)、電力管理晶粒(例如，電力管理積體電路(PMIC)晶粒)、射頻(RF)晶粒、感測器晶粒、微機電系統(MEMS)晶粒、訊號處理晶粒(例如，數位訊號處理(DSP)晶粒)、前端晶粒(例如，類比前端(AFE)晶粒)等或其組合。晶粒400A可包括一或多個邏輯晶粒。與上述晶粒68相似，晶粒400A可放置及結合於組件96上且本文中不再對其予以贅述。
晶粒400B可為記憶體晶粒，例如動態隨機存取記憶體晶粒、靜態隨機存取記憶體晶粒、高頻寬記憶體(HBM)晶粒、混合記憶體立方(HMC)晶粒等。在一些實施例中，晶粒400B可包括記憶體晶粒與記憶體控制器二者，例如(舉例而言，具有記憶體控制器的四個或八個記憶體晶粒的堆疊)。與上述晶粒88相似，晶粒400B可放置及結合於組件96上且本文中不再對其予以贅述。
在圖20中更詳細地繪示根據一些實施例的示例性晶粒400B。主體405可包括多個堆疊記憶體晶粒408以及頂部晶粒412。堆疊記憶體晶粒408可皆為相同的晶粒，或者記憶體晶粒408 可包括不同類型及/或結構的晶粒。記憶體晶粒408中的每一者藉由連接件406而連接至上覆的記憶體晶粒408及/或下伏的記憶體晶粒408。連接件406可為微凸塊或其他適宜的連接件。記憶體晶粒408可包括將下伏的連接件406連接至上覆的連接件406的穿孔410。在一些實施例中，記憶體晶粒408分別具有厚度T4，厚度T4介於約20微米至約100微米範圍內(例如，約60微米)。
在一些實施例中，主體405可包括高頻寬記憶體(HBM)模組及/或混合記憶體立方(HMC)模組，所述高頻寬記憶體及/或混合記憶體立方可包括連接至邏輯晶粒402的一或多個記憶體晶粒408。邏輯晶粒402可包括穿孔404，穿孔404將內連線區(圖中未示出)的導電特徵連接至上覆的連接件406及記憶體晶粒408。在一些實施例中，邏輯晶粒402可為記憶體控制器。內連線區(圖中未示出)可提供導電圖案，所述導電圖案容許主體405的引腳輸出接觸圖案(pin-out contact pattern)與導電接頭91的圖案不同，進而容許更靈活地放置導電接頭91。導電接頭91可設置於晶粒400B的底側上且可用於將晶粒400B實體地連接至且電性連接至組件96。導電接頭91可藉由內連線區而電性連接至邏輯晶粒402及/或堆疊記憶體晶粒408。導電接頭91可使用與以上針對導電接頭91所闡述的方法相同或相似的方法來形成，且本文中不再對其予以贅述。
除頂部晶粒412厚於記憶體晶粒408以外，頂部晶粒412可為與記憶體晶粒408相似的晶粒(在功能及電路系統方面)。在 一些實施例中，頂部晶粒412為虛擬晶粒且相似於上述蓋體結構110。在一些實施例中，頂部晶粒412具有厚度T5，厚度T5介於約50微米至約200微米範圍內(例如，約150微米)。在一些實施例中，頂部晶粒412具有大於約120微米的厚度T5。已發現，晶粒400B的頂部晶粒412的厚度大於約120微米會提高封裝結構500的良率而無需使用一些前述實施例的虛擬晶粒106及蓋體結構110及132。
如由圖20所示，主體405可包封於模塑材料414中。模塑材料414可包括模塑化合物、模塑底部填充膠、環氧樹脂、或樹脂。
儘管圖20說明具有記憶體晶粒的晶粒400B，然而圖19所示邏輯晶粒400A可具有帶有較厚的頂部晶粒412的相似堆疊結構。
圖21說明根據一些實施例的封裝結構的剖視圖。除圖21中的封裝結構不包括包封體112以外，圖21中的實施例相似於圖19至圖20中的實施例。本文中不再對此實施例的與前面的實施例相同或相似的細節予以贅述。
一種封裝結構的所揭露實施例包括在鄰近主動晶粒之處的虛擬晶粒結構以減少封裝結構的翹曲。封裝結構的翹曲的此種減少能夠使得藉由降低主動晶粒與插入體之間存在冷接頭的可能性而達成更可靠的封裝結構。在一些實施例中，虛擬晶粒位於切割道區中且蓋體結構覆蓋主動晶粒中的一些，而其他主動晶粒則 不被蓋體結構覆蓋。虛擬晶粒可使得能夠更大程度地控制包封體的比率且因此可減少因熱膨脹係數(CTE)不匹配而造成的應力及翹曲。在一些實施例中，可省略包封體，乃因切割道區中的虛擬晶粒及/或蓋體結構為封裝結構提供充分的支撐及保護。在一些實施例中，主動晶粒是一或多個晶粒的堆疊(邏輯晶粒堆疊及/或記憶體晶粒堆疊)，所述晶粒堆疊的最頂部晶粒厚於所述晶粒堆疊的其他晶粒。在該些實施例中，可省略切割道區中的虛擬晶粒以及包封體，乃因晶粒堆疊的較厚的頂部晶粒為封裝結構提供充分的支撐及保護。
實施例是一種方法，所述方法包括：使用第一電性連接件將第一晶粒貼合至第一組件的第一側；使用第二電性連接件將第二晶粒的第一側貼合至第一組件的第一側；將虛擬晶粒在第一組件的切割道區中貼合至所述第一組件的第一側；將蓋體結構黏著至第二晶粒的第二側；以及將第一組件及虛擬晶粒單體化，以形成封裝結構。
實施方案可包括以下特徵中的一或多者。在所述方法中，第一組件是第三晶粒。所述方法更包括：將封裝結構安裝至第二基底，第一組件夾置於第一晶粒及第二晶粒與所述第二基底之間。在所述方法中，單體化包括鋸開第一組件及虛擬晶粒以形成封裝結構。在所述方法中，第一組件是包括重佈線結構的塊狀基底，第一晶粒及第二晶粒貼合至所述重佈線結構。在所述方法中，第一晶粒包括一或多個邏輯晶粒，且第二晶粒包括一或多個 記憶體晶粒。所述方法更包括：形成延伸穿過第一組件的穿孔，第一晶粒及第二晶粒電性耦合至所述穿孔；在第一組件的第二側上形成第三電性連接件，所述第二側與第一側相對，所述第三電性連接件電性耦合至穿孔；使用第三電性連接件將封裝結構安裝至第二基底；以及將表面安裝元件(SMD)結合至第二基底。在所述方法中，虛擬晶粒及蓋體結構是由矽製成。
實施例是一種方法，所述方法包括：使用第一電性連接件將第一晶粒結合至第一結構的第一側；使用第二電性連接件將記憶體晶粒結合至第一結構的第一側，所述記憶體晶粒鄰近第一晶粒；將第二晶粒貼合至記憶體晶粒的背面側，所述第二晶粒具有較所述記憶體晶粒的厚度大的厚度；以及將第一結構單體化以形成封裝結構。
實施方案可包括以下特徵中的一或多者。在所述方法中，第二晶粒的厚度大於或等於120微米。在所述方法中，將第二晶粒貼合至記憶體晶粒的背面側包括將所述第二晶粒結合至所述記憶體晶粒的所述背面側，所述第二晶粒是電性耦合至所述記憶體晶粒的記憶體晶粒。在所述方法中，將第二晶粒貼合至記憶體晶粒的背面側包括使用黏著層將所述第二晶粒黏著至所述記憶體晶粒的所述背面側，所述第二晶粒是由塊狀材料製成且不包括任何主動元件或被動元件。所述方法更包括：在第一結構的第一側與第一晶粒及記憶體晶粒之間並環繞第一電性連接件及第二電性連接件形成底部填充膠；以及使用包封體包封第一晶粒及記憶 體晶粒，所述包封體鄰接底部填充膠的一些部分。所述方法更包括：將多個虛擬晶粒在第一結構的切割道區中黏著至所述第一結構的第一側，其中將所述第一結構單體化以形成所述封裝結構包括將所述多個虛擬晶粒單體化。所述方法更包括：在將第一晶粒結合至第一結構的第一側之前，在所述第一結構中形成穿孔；在穿孔上形成第一重佈線結構，所述第一重佈線結構是第一結構的第一側，所述第一重佈線結構電性耦合至所述穿孔；薄化第一結構的第二側，以暴露出穿孔的端部，所述第二側與第一側相對；在第一結構的第二側上形成第二重佈線結構，藉此形成第一插入體，所述第二重佈線結構電性耦合至穿孔的被暴露出的端部；在第一插入體上形成電性耦合至所述第一插入體的第三電性連接件；將第三電性連接件結合至第一基底；以及將表面安裝元件(SMD)結合至鄰近第三電性連接件中的一者的第一基底。
實施例是一種結構，所述結構包括：插入體的第一側，結合至封裝基底；第一晶粒的主動側及第二晶粒的主動側，結合至插入體的第二側，所述第二側與第一側相對；虛擬晶粒，貼合至插入體的第二側，所述虛擬晶粒鄰近第一晶粒或第二晶粒中的至少一者；以及蓋體結構，黏著至第二晶粒的背面側。
實施方案可包括以下特徵中的一或多者。在所述結構中，虛擬晶粒是由矽製成。在所述結構中，第二晶粒包括一或多個記憶體晶粒，蓋體結構厚於所述一或多個記憶體晶粒中的每一者。在所述結構中，蓋體結構更黏著至第一晶粒的背面側及虛擬 晶粒的頂表面。
以上概述了若干實施例的特徵，以使熟習此項技術者可更佳地理解本發明的各個態樣。熟習此項技術者應知，其可容易地使用本發明作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或達成與本文中所介紹的實施例相同的優點。熟習此項技術者亦應認識到，該些等效構造並不背離本發明的精神及範圍，而且他們可在不背離本發明的精神及範圍的條件下對其作出各種改變、代替、及變更。

Claims (10)

  1. 一種封裝結構的形成方法，包括：使用第一電性連接件將第一晶粒貼合至第一組件的第一側；使用第二電性連接件將第二晶粒的第一側貼合至所述第一組件的所述第一側；將虛擬晶粒在所述第一組件的切割道區中貼合至所述第一組件的所述第一側；將蓋體結構黏著至所述第二晶粒的第二側；以及將所述第一組件及所述虛擬晶粒單體化，以形成封裝結構，其中在所述單體化過程中，由所述虛擬晶粒的上表面至下表面切割所述虛擬晶粒。
  2. 如申請專利範圍第1項所述的方法，其中所述第一組件是第三晶粒。
  3. 如申請專利範圍第1項所述的方法，更包括：將所述封裝結構安裝至第二基底，所述第一組件夾置於所述第一晶粒及所述第二晶粒與所述第二基底之間。
  4. 如申請專利範圍第1項所述的方法，其中所述第一組件是包括重佈線結構的塊狀基底，所述第一晶粒及所述第二晶粒貼合至所述重佈線結構。
  5. 如申請專利範圍第1項所述的方法，更包括：形成延伸穿過所述第一組件的穿孔，所述第一晶粒及所述第二晶粒電性耦合至所述穿孔；在所述第一組件的第二側上形成第三電性連接件，所述第二側與所述第一側相對，所述第三電性連接件電性耦合至所述穿孔；使用所述第三電性連接件將所述封裝結構安裝至第二基底；以及將表面安裝元件(SMD)結合至所述第二基底。
  6. 一種封裝結構的形成方法，包括：使用第一電性連接件將第一晶粒結合至第一結構的第一側；使用第二電性連接件將記憶體晶粒結合至所述第一結構的所述第一側，所述記憶體晶粒鄰近所述第一晶粒；將第二晶粒貼合至所述記憶體晶粒的背面側，所述第二晶粒具有較所述記憶體晶粒的厚度大的厚度；以及將所述第一結構單體化以形成封裝結構。
  7. 如申請專利範圍第6項所述的方法，其中將所述第二晶粒貼合至所述記憶體晶粒的所述背面側包括：將所述第二晶粒結合至所述記憶體晶粒的所述背面側，所述第二晶粒是電性耦合至所述記憶體晶粒的記憶體晶粒；或使用黏著層將所述第二晶粒黏著至所述記憶體晶粒的所述背面側，所述第二晶粒是由塊狀材料製成且不包括任何主動元件或被動元件。
  8. 如申請專利範圍第6項所述的方法，更包括：在所述第一結構的所述第一側與所述第一晶粒及所述記憶體晶粒之間並環繞所述第一電性連接件及所述第二電性連接件形成底部填充膠；以及使用包封體包封所述第一晶粒及所述記憶體晶粒，所述包封體鄰接所述底部填充膠的一些部分。
  9. 如申請專利範圍第6項所述的方法，更包括：在將所述第一晶粒結合至第一結構的第一側之前，在所述第一結構中形成穿孔；在所述穿孔上形成第一重佈線結構，所述第一重佈線結構是所述第一結構的所述第一側，所述第一重佈線結構電性耦合至所述穿孔；薄化所述第一結構的第二側，以暴露出所述穿孔的端部，所述第二側與所述第一側相對；在所述第一結構的所述第二側上形成第二重佈線結構，藉此形成第一插入體，所述第二重佈線結構電性耦合至所述穿孔的被暴露出的所述端部；在所述第一插入體上形成電性耦合至所述第一插入體的第三電性連接件；將所述第三電性連接件結合至第一基底；以及將表面安裝元件(SMD)結合至鄰近所述第三電性連接件中的一者的所述第一基底。
  10. 一種封裝結構，包括：插入體的第一側，結合至封裝基底；第一晶粒的主動側及第二晶粒的主動側，結合至所述插入體的第二側，所述第二側與所述第一側相對；虛擬晶粒，貼合至所述插入體的所述第二側，所述虛擬晶粒鄰近所述第一晶粒或所述第二晶粒中的至少一者；以及蓋體結構，黏著至所述第二晶粒的背面側，其中所述蓋體結構的頂表面與所述虛擬晶粒的頂表面齊平。
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