TW201322319A - 半導體裝置及其形成方法 - Google Patents

半導體裝置及其形成方法 Download PDF

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TW201322319A
TW201322319A TW101103483A TW101103483A TW201322319A TW 201322319 A TW201322319 A TW 201322319A TW 101103483 A TW101103483 A TW 101103483A TW 101103483 A TW101103483 A TW 101103483A TW 201322319 A TW201322319 A TW 201322319A
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die
bottom wafer
dummy
wafer
substrate
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TWI555074B (zh
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Jing-Cheng Lin
Cheng-Lin Huang
Szu-Wei Lu
Jui-Pin Hung
Shin-Puu Jeng
Chen-Hua Yu
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Taiwan Semiconductor Mfg
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Abstract

一種裝置包括一底部晶片以及一接合至上述底部晶片的有效頂部晶粒。一虛置晶粒黏附至上述底部晶片。上述虛置晶粒與上述底部晶片電性絕緣。

Description

半導體裝置及其形成方法
本發明係有關於一種半導體晶圓，特別是關於一種晶片堆疊晶圓組件。
對形成三維積體電路而言，晶粒通常接合至半導體晶圓上。上述接合製程一般包括選擇已知良品的晶粒(頂部晶粒)，以及利用覆晶接合技術，將上述頂部晶粒接合至在一底部晶圓中的底部晶片。上述每個底部晶片接合至一或多個頂部晶粒。在上述接合之後，底層充填材料(underfill)注入上述頂部晶粒與底部晶片之間的空間，以及一模塑化合物成型於上述頂部晶粒與底部晶圓之上。在上述模塑化合物成型之後，由於上述模塑化合物的收縮，上述封裝可能產生一翹曲變形(warpage)。因此，可能會產生壓力並且對上述底部晶圓以及上方的頂部晶粒施壓。
在上述背部拋光製程之後，上述情形會更趨惡化，在此製程期間，將上述在底部晶圓中的矽基板拋光，使得上述底部晶圓的厚度明顯減少。上述翹曲變形的現象則更加嚴重。上述翹曲變形可能導致在最後產出之封裝中膜層之間的黏附不良、耐濕性不佳、凸塊破裂、以及諸如此類等。因此，更可能出現可靠度的問題，其中可在熱循環試驗(thermal cycle tests)、落下試驗(drop tests)、彎曲試驗(bend tests)、以及諸如此類的試驗中鑑定上述可靠度問題。
本發明提供一種半導體裝置，包括：一底部晶片；一有效頂部晶粒接合至上述底部晶片；以及一虛置晶粒黏附至上述底部晶片，其中上述虛置晶粒與上述底部晶片電性絕緣。
本發明另提供一種半導體裝置，包括：一底部晶片，包括：一基板；一導電通孔自上述基板的一第一側延伸至一第二側；一第一連接器於上述基板的上述第一側上；以及一第二連接器於上述基板的上述第二側上，其中上述第一連接器透過上述導電通孔電性耦接至上述第二連接器；一有效頂部晶粒於上述基板的上述第一側上，並且透過上述第一連接器接合至上述底部晶片；一虛置晶粒於上述基板的上述第一側上；以及一晶粒接著薄膜將上述虛置晶粒黏附至上述底部晶片。
本發明尚提供一種半導體裝置的形成方法，包括：將複數個有效頂部晶粒接合至一底部晶圓，其中上述複數個有效頂部晶粒中的每一個有效頂部晶粒透過電子連接器(electrical connector)，接合至在上述底部晶圓中之複數個相同晶片的其中之一。將複數個虛置晶粒黏附至上述複數個相同晶片，其中上述複數個虛置晶粒中的每一個虛置晶粒透過複數個晶粒接著薄膜的其中之一，黏附至上述複數個相同晶片的其中之一，且其中上述複數個虛置晶粒藉由上述複數個晶粒接著薄膜，與上述複數個相同晶片電性絕緣；以及填充一模塑化合物進入介於上述複數個有效頂部晶粒與上述複數個虛置晶粒之間的縫隙。
為了讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉較佳實施例，作詳細說明如下：
本發明接下來將會提供許多不同的實施例以實施本發明中不同的特徵。值得注意的是，這些實施例提供許多可行之發明概念並可實施於各種特定情況。然而，在此所討論之這些特定實施例僅用於舉例說明本發明之製造及使用方法，但非用於限定本發明之範圍。
根據本發明各種不同的實施例，提供一種封裝結構以及形成上述封裝結構的方法。以下係透過各種圖示及例式說明本發明較佳實施例的形成封裝結構之中間階段。在本發明各種不同之各種實施例和圖示中，相同的符號代表相同或類似的元件。
第1A圖顯示底部晶圓20的俯視圖。在一實施例中，底部晶圓20為一裝置晶圓，包括半導體基板38(未顯示於第1A圖中，請參閱第1B圖)，以及有效元件，像是形成於半導體基板38的表面之電晶體(未顯示)。半導體基板38可為一矽基板，或亦可由其他的半導體材料所形成。底部晶圓20中包括複數個相同的底部晶片24，其中底部晶片24可彼此相同。切割道26將底部晶片24彼此分開。複數個頂部晶粒30，包括有效頂部晶粒30A以及虛置晶粒30B，接合至底部晶片24。綜上所述，”有效晶粒”以及”-有效頂部晶粒”等用辭意指上述對最終封裝的電性操作具有具有電性功能的晶粒或晶片，而”虛置晶粒”則意指沒有任何電性功能的晶粒或晶片。有效頂部晶粒30可為裝置晶粒、或可為包括接合至其他封裝組件，例如一封裝基板、一中介板(interposer)、以及諸如此類等的裝置之晶粒封裝。
第1B圖顯示如在第1A圖中所示之結構的截面圖，其中上述截面為沿著在第1A圖中的平面之截線1B-1B截取所得。底部晶片24可為包括有效元件、接點插塞(contact plugs)、金屬線、導通孔以及諸如此類等(其形成於基板38的頂面38A之上)的有效晶片，雖然上述元件並未顯示於第1B圖中。如第1B圖所示，底部晶片24可與一或複數個有效頂部晶粒30A接合。電子連接器(electrical connectors)32將有效頂部晶粒30A接合至底部晶粒24。電子連接器32可為焊接凸塊(solder bumps)、金屬對金屬鍵結(metal-to-metal bonds)，接合至金屬導桿(metal posts)的焊接凸塊、或諸如此類等，並且可用於傳遞介於底部晶片24與有效頂部晶粒30A之間的電子訊號。因此上述積體電路元件，例如在有效頂部晶粒30A中的電晶體(未顯示)，電性耦接至在底部晶片24中的裝置。在一實施例中，電子連接器32電性耦接至在半導體基板38中之基板穿孔36(through-substrate vias，TSVs，有時候亦稱作穿矽通孔(through-silicon vias))。基板穿孔36(through-substrate vias，TSVs)自基板38的頂面38A延伸至介於基板38的頂面38A與底面38B之間的中間層。
虛置晶粒30B黏附至底部晶粒24，例如，透過晶粒接著薄膜(die-attach film)40，上述晶粒接著薄膜(die-attach film)40可為一聚合物基的膠水(polymer-based glue)。再者，晶粒接著薄膜40可為當加熱時可被固化的一熱塑性薄膜。在一些實施例中，晶粒接著薄膜40可為一接著劑，當曝露在光線底下時，上述接著劑會失去其黏性。虛置晶粒30B可為一空白晶粒，例如，一半導體晶粒(像是一矽晶粒)，其中沒有像是電晶體等的積體電路元件，及/或像是電阻、電容等的被動元件形成。虛置晶粒30B其中亦可不含低介電常數之介電層、金屬線、導通孔、及/或諸如此類等。在其他的實施例中，虛置晶粒38B可為一介電晶粒(dielectric die)。在其他的實施例中，虛置晶粒30B可重複使用在試驗中不合格的不良晶粒，因此其中可包括像是電晶體等的積體電路元件。然而在虛置晶粒30B中若有積體電路元件的話，在最終封裝60的操作中(第5圖)，此積體電路元件並不會表現任何電性功能，且不予其供電。
晶粒接著薄膜40可由電性絕緣材料所形成，並且將虛置晶粒30B與底部晶片24電性絕緣。雖然第1A圖顯示一接合至一底部晶片24的單一虛置晶粒30B，但在替代實施例中，可將複數個虛置晶粒30B黏附至上述相同的底部晶片24。
回頭參閱第1A圖，一些虛置晶粒30B黏附至底部晶片24，其中底部晶片24為矩形的完整晶片，且為功能性晶片。額外的虛置晶粒30B亦可黏附至非完整的底部晶片24’。非完整的底部晶片24’位於晶圓20的邊緣，且非矩形。非完整的底部晶片24’不會像所使用的產品一樣被封裝。因此，沒有任何有效頂部晶粒30A接合至非完整的底部晶片24。
第2A及2B圖係說明上述成型製程。將模塑化合物44填充進入介於有效頂部晶粒30A與虛置晶粒30B之間的縫隙。模塑化合物44的頂面可高於有效頂部晶粒30A以及虛置晶粒30B之頂面。之後進行一固化製程以固化模塑化合物44。
第2A圖顯示在第1A圖中所示之結構的截面圖，其中上述截面為沿著在第1A圖中的相同平面之截線1B-1B截取所得。如第2A圖中所示，模塑化合物44與有效頂部晶粒30A、虛置晶粒30B、晶粒接著薄膜40、以及底部晶片24物理性接觸。第2B圖顯示非完整的底部晶片24’之截面圖，其中上述截面為沿著在第1A圖中的相同平面之截線2B-2B截取所得。如第2B圖中所示，晶粒接著薄膜40將虛置晶粒30B黏附至非完整晶粒24’，並且模塑化合物44可與晶粒接著薄膜40、虛置晶粒30B、以及非完整晶粒24’物理性接觸。
接著，如第3圖中所示，進行一平坦化製程，例如一拋光製程，將多餘的模塑化合物44移除，如此一來，模塑化合物44的頂面44A即是平坦的。在一實施例中，進行上述平坦化製程直到露出有效頂部晶粒30A以及虛置晶粒30B的頂面30C。
在第1A圖的說明實施例中，接合至一相同底部晶片24的有效頂部晶粒30A的總上視面積小於底部晶片24的上視面積。此外，有效頂部晶粒30A不會覆蓋住底部晶片24的晶片區之大部份。上述情形導致大縫隙形成於有效頂部晶粒30A之間，因此，如第3圖中所示之結構，若虛置晶粒30B不存在，模塑化合物44將會有很高的圖案密度(pattern density)，尤其是在包括上述大縫隙的晶片區中。另一方面，在一些包含有效頂部晶粒30A之其他的晶片區，上述模塑化合物44的圖案密度低。藉由插入虛置晶粒30B，穿過晶圓20之模塑化合物44的圖案密度更加均勻。這可有助於減少最終封裝的翹曲變形(例如，第3圖中所示之結構)，上述最終封裝包括底部晶圓20、頂部晶粒30、以及模塑化合物44。
參閱第4圖，將在第3圖中所示之封裝結構反轉。模塑化合物44以及頂部晶粒30，例如，透過接著劑50，黏附(接合)至載板48。在一實施例中，接著劑50為光鍵解薄膜(light-to-debond film)，當其暴露在光線下時會失去黏性。例如，接著劑50可為一紫外線膠水(ultra-violet(UV) glue)。接著劑50以可為一熱鍵解薄膜(thermal-to-debond film)，當其受熱時會失去黏性。接著劑50亦可實質上由與晶粒接著薄膜40相同的材料所形成。在一範例的形成製程中，對基板38進行背面拋光製程，直到露出基板穿孔36(through-substrate vias，TSVs)。
參閱第5圖，形成底部晶片24(以及底部晶圓20)的背面內連線結構。在一實施例中，上述背面內連線結構包括介電層52，並且接合墊/重分配線(bond pads/redistribution lines)54。將接合墊/重分配線(pads/redistribution lines)54電性結合至基板穿孔36(through-substrate vias，TSVs)。接著，連結器56可配置或形成於接合墊54之上。在替代實施例中，連結器56可包括金屬對金屬鍵結(metal-to-metal bonds)，接合至金屬導桿(metal posts)的焊接凸塊、或諸如此類等，並且可用於傳遞介於底部晶片24與另一個封裝組件，例如一裝置晶粒、一中介板(interposer)、一封裝基板、或一印刷電路板(printed circuit board，PCB)，之間的電子訊號。
接著，如第6圖中所示，例如，藉由將第4圖中所示之接著劑50曝露在光線下，將載板48自晶圓20分離(鍵解)，如此一來可移除接著劑50以及載板48。然後進行一晶粒分割步驟將晶圓20切開以形成複數個封裝體60，其中第6圖係顯示上述複數個封裝體60的其中之一。在上述最終封裝體60中，留下虛置晶粒30B，並且在後續的封裝製程，例如將封裝體60接合至一封裝基板、一中介板、一印刷電路板、以及諸如此類等，中不將虛置晶粒30B移除。此外，在使用並供電給封裝60的時候，仍保留虛置晶粒30B。
第7及第8圖係根據本發明中各種不同的替代實施例，顯示在封裝製造中的各階段之截面圖。除非特別指明，否則在這些實施例中的元件符號係代表在第1至6圖所描述之實施例中的相似元件。參閱第7圖，提供底部晶片24。須注意的是，底部晶片24可包括上述有效元件、接點插塞(contact plugs)、金屬線、導通孔以及諸如此類等，雖然上述元件並未顯示於第7圖中。在一些實施例中，底部晶片24已經自各個晶圓被切開，因此在下文中亦可稱作底部晶粒24。在一替代實施例中，底部晶片24為尚未被切開之晶圓的一部份。上述晶圓可包括複數個與所示底部晶片24實質上相同的晶片。包括介電層52以及金屬線/墊54的背面內連線結構形成於底部晶粒24的被面上。連結器56可選擇性地形成於上述背面內連線結構上，並且電性結合至基板穿孔36(through-substrate vias，TSVs)以及像是在底部晶粒24中的電晶體等裝置。
在第8圖中，將有效頂部晶粒30A接合至底部晶粒24，以及將虛置晶粒30B黏附至底部晶粒24。上述接合方法與黏附方法、以及個別材料可實質上與第1B圖中所示相同，因此在此處不再重複。接下來，將模塑化合物44塗覆、固化、並且選擇性拋光。上述最終結構可實質上與第6圖中所示相同。在上述實施例中，第7及第8圖中的底部晶片24為晶圓的一部分，進行一分割步驟以切割上述晶圓，如此一來，將與第8圖中所示相同的上述晶片彼此分開，其中每一個晶片皆具有如第8圖中所示之結構。
在上述實施例中，藉由將虛置晶粒黏附至晶圓或底部晶粒，上述模塑化合物的圖案密度可更加均勻，因此可減少在上述最終封裝中的翹曲變形。上述翹曲變形的減少使得介於不同膜層之間的剝離(delamination)減少。因此，上述模塑化合物對於水氣的穿透具有較佳的抗性。上述封裝的可靠度因此而增加。上述虛置晶粒的使用導致了在複數個晶粒接著薄膜中所使用的模塑化合物減少，因此減少了從上述模塑化合物逸氣的情況。
根據本發明實施例，提供一種半導體裝置，包括一底部晶片以及一有效頂部晶粒接合至上述底部晶片。一虛置晶粒黏附至上述底部晶片。上述虛置晶粒與上述底部晶片電性絕緣。
根據本發明的其他實施例，提供一種半導體裝置，包括：一底部晶片，上述底部晶片包括複數個相同晶片。複數個有效頂部晶粒接合至上述底部晶圓，其中將上述複數個有效頂部晶粒中的每一個有效頂部晶粒黏附至上述複數個相同晶片的其中之一。上述半導體裝置更包括複數個晶粒接著薄膜，其中上述複數個晶粒接著薄膜中的每一個晶粒接著薄膜將複數個虛置晶粒的其中之一黏附至複數個相同晶片的其中之一。
根據本發明的其他實施例，提供一種半導體裝置的形成方法，包括：將複數個有效頂部晶粒接合至一底部晶圓。上述複數個有效頂部晶粒中的每一個有效頂部晶粒透過電子連接器(electrical connector)，接合至在上述底部晶圓中之複數個相同晶片的其中之一。將複數個虛置晶粒黏附至上述複數個相同晶片。上述複數個虛置晶粒中的每一個虛置晶粒透過複數個晶粒接著薄膜的其中之一，黏附至上述複數個相同晶片的其中之一。上述複數個虛置晶粒藉由上述複數個晶粒接著薄膜，與上述複數個相同晶片電性絕緣。將一模塑化合物填充進入介於上述複數個有效頂部晶粒與上述複數個虛置晶粒之間的縫隙。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
20．．．底部晶圓
24．．．底部晶片
24’．．．非完整的底部晶片
26．．．切割道
30．．．頂部晶粒
30A．．．有效頂部晶粒
30B．．．虛置晶粒
30C．．．虛置晶粒的頂面
1B-1B．．．截線
2B-2B．．．截線
32．．．電子連接器
36．．．基板穿孔
38．．．半導體基板
38A．．．基板的頂面
38B．．．基板的底面
40．．．晶粒接著薄膜
44．．．模塑化合物
44A．．．複合物的頂面
48．．．載板
50．．．接著劑
52．．．介電層
54．．．接合墊/重分配線
56．．．連結器
60．．．最終封裝
第1A、1B、2A、2B、3～6圖係根據本發明中各種不同的實施例，顯示在封裝製造中的各階段之截面圖，其中將虛置晶粒黏附至晶圓中的底部晶片。
第7及第8圖係根據本發明中各種不同的替代實施例，顯示在封裝製造中的各階段之截面圖，其中將虛置晶粒黏附至不連續的底部晶片。
20．．．底部晶圓
24．．．底部晶片
24’．．．非完整的底部晶片
26．．．切割道
30A．．．有效頂部晶粒
30B．．．虛置晶粒
1B-1B．．．截線
2B-2B．．．截線

Claims (11)

  1. 一種半導體裝置，包括：一底部晶片；一有效頂部晶粒接合至該底部晶片；以及一虛置晶粒黏附至該底部晶片，其中該虛置晶粒與該底部晶片電性絕緣。
  2. 如申請專利範圍第1項所述之半導體裝置，其中該虛置晶粒實質上擇自下列所組成之群組：一空白晶粒其中不含積體電路、一矽晶粒其中不含低介電常數介電層、金屬線、以及導通孔、以及上述之組合。
  3. 如申請專利範圍第1項所述之半導體裝置，其中該虛置晶粒不耦接至任何供電電源。
  4. 如申請專利範圍第1項所述之半導體裝置，其中該有效頂部晶粒接合至該底部晶片，並且透過電子連接器(electrical connector)電性耦接至該底部晶片，其中該虛置晶粒透過一黏合劑黏著至該底部晶片，且其中該虛置晶粒藉由該黏合劑與該底部晶片電性絕緣。
  5. 如申請專利範圍第1項所述之半導體裝置，更包括一模塑化合物在一介於該有效頂部晶粒與該虛置晶粒之間的縫隙。
  6. 如申請專利範圍第1項所述之半導體裝置，其中該底部晶片為一晶圓的一部分，且未自該晶圓分割出來。
  7. 如申請專利範圍第1項所述之半導體裝置，其中該底部晶片更包括一基板穿孔於該底部晶片的一半導體基板中。
  8. 一種半導體裝置，包括：一底部晶片，包括：一基板；一導電通孔自該基板的一第一側延伸至一第二側；一第一連接器於該基板的該第一側上；以及一第二連接器於該基板的該第二側上，其中該第一連接器透過該導電通孔電性耦接至該第二連接器；一有效頂部晶粒於該基板的該第一側上，並且透過該第一連接器耦接至該底部晶片；一虛置晶粒於該基板的該第一側上；以及一晶粒接著薄膜將該虛置晶粒黏附至該底部晶片。
  9. 一種半導體裝置的形成方法，包括：將複數個有效頂部晶粒接合至一底部晶圓，其中該複數個有效頂部晶粒中的每一個有效頂部晶粒透過電子連接器(electrical connector)，耦接至在該底部晶圓中之複數個相同晶片的其中之一；將複數個虛置晶粒黏附至該複數個相同晶片，其中該複數個虛置晶粒中的每一個虛置晶粒透過複數個晶粒接著薄膜的其中之一，黏附至該複數個相同晶片的其中之一，且其中該複數個虛置晶粒藉由該複數個晶粒接著薄膜，與該複數個相同晶片電性絕緣；以及填充一模塑化合物進入介於該複數個有效頂部晶粒與該複數個虛置晶粒之間的縫隙。
  10. 如申請專利範圍第9項所述之半導體裝置的形成方法，更包括在塗覆該模塑化合物的步驟之前，將一虛置晶粒黏附至一在該底部晶圓中之非完整(incomplete)的底部晶片，其中該模塑化合物與該虛置晶粒物理性相接觸。
  11. 如申請專利範圍第9項所述之半導體裝置的形成方法，包括：在填充該模塑化合物的步驟之後，利用一接著劑將一載板黏附至該底部晶圓；對在該底部晶圓中的一基板進行一背面拋光露出在該底部晶圓中的矽穿孔；形成一背面內連線結構於該底部晶圓的一背面上；以及將該底部晶圓鋸開以形成複數個封裝體，其中該複數個封裝體中的每一個封裝體包括該複數個有效頂部晶粒的其中之一以及該複數個虛置晶粒的其中之一。
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