CN103117279A - 形成芯片在晶圆的总成的方法 - Google Patents

形成芯片在晶圆的总成的方法 Download PDF

Info

Publication number
CN103117279A
CN103117279A CN2012101207486A CN201210120748A CN103117279A CN 103117279 A CN103117279 A CN 103117279A CN 2012101207486 A CN2012101207486 A CN 2012101207486A CN 201210120748 A CN201210120748 A CN 201210120748A CN 103117279 A CN103117279 A CN 103117279A
Authority
CN
China
Prior art keywords
pseudo
tube core
chip
die
bottom chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2012101207486A
Other languages
English (en)
Other versions
CN103117279B (zh
Inventor
林俊成
黄震麟
卢思维
洪瑞斌
郑心圃
余振华
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority to GB201301015A priority Critical patent/GB2502172A/en
Publication of CN103117279A publication Critical patent/CN103117279A/zh
Application granted granted Critical
Publication of CN103117279B publication Critical patent/CN103117279B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1418—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/14181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H01L2225/06586—Housing with external bump or bump-like connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06593—Mounting aids permanently on device; arrangements for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

Abstract

本发明公开了一种器件，该器件包括底部芯片和接合到所述底部芯片的有源顶部管芯。伪管芯附接到所述底部芯片。所述伪管芯与所述底部芯片电隔离。本发明还公开了形成芯片在晶圆的总成的方法。

Description

形成芯片在晶圆的总成的方法
技术领域
本发明涉及半导体领域，更具体地，本发明涉及一种形成芯片在晶圆的总成的方法。
背景技术
在三维集成电路的形成过程中，管芯通常接合在半导体晶圆上。接合工艺典型地接合包括选择合格的管芯(顶部管芯)，并且利用倒装焊接将顶部管芯接合到底部芯片上。底部芯片中的每一个均可以被接合到一个或者多个顶部管芯上。在接合后，将底部填充物分发到顶部管芯和底部芯片之间的间隙内，并且模塑料模制到顶部管芯和底部晶圆上。在模制模塑料后，由于模塑料的收缩，可能导致封装件弯曲。因此，可以产生应力并且将其应用于底部晶圆和覆在上面的顶部管芯。
在底部晶圆中的硅衬底被研磨期间，在背部研磨工艺后，情形变得更糟，并因此显著地减少了底部晶圆的厚度。弯曲相应地更严重。所述弯曲可以导致最终得到的封装件中的层与层之间的粘性差，抗潮性差，防止凸块破裂的能力差等等。结果，可靠性问题很有可能发生，可靠性问题可以在热循环测试，下坠测试，弯曲测试等中验证。
发明内容
为了解决现有技术中所存在的问题，根据本发明的一个方面，提供了一种器件，所述器件包括：
底部芯片；
有源顶部管芯，接合到所述底部芯片；和
伪管芯，附接到所述底部芯片，其中所述伪管芯与所述底部芯片电隔离。
在一些实施例中，所述伪管芯选自基本上由以下组成的组中：在其中没有集成电路的空白管芯，在其中没有低k电介质层、金属线、和通孔的硅管芯，和它们的组合。
在一些实施例中，所述伪管芯设置成不与电源连接。
在一些实施例中，所述有源顶部管芯接合到所述底部芯片并且通过电连接件与所述底部芯片电连接，其中所述伪管芯通过粘接剂粘附到所述底部芯片，并且其中所述伪管芯通过所述粘接剂与所述底部芯片电隔离。
在一些实施例中，所述器件进一步包括在所述有源顶部管芯和所述伪管芯之间的间隙中的模塑料。
在一些实施例中，所述底部芯片是晶圆的一部分，并且没有从所述晶圆切割掉。
在一些实施例中，所述底部芯片进一步包括在所述底部芯片的半导体衬底中的衬底通孔。
根据本发明的另一个方面，提供了一种器件，所述器件包括：
底部芯片，包括：
衬底；
通孔，从所述衬底的第一侧延伸至所述衬底的第二侧；
第一连接件，在所述衬底的所述第一侧上；和
第二连接件，在所述衬底的所述第二侧上，其中所述第一连接件通过所述通孔与所述第二连接件电连接；
有源顶部管芯，在所述衬底的所述第一侧上，所述有源顶部管芯通过所述第一连接件接合到所述底部芯片；
伪管芯，在所述衬底的所述第一侧上；和
管芯附接膜，使所述伪管芯附接到所述底部芯片。
在一些实施例中，所述伪管芯设置成不与任何电源连接。
在一些实施例中，所述管芯附接膜包括介电材料，并且其中没有导电部件穿透所述管芯附接膜。
在一些实施例中，所述器件进一步包括在所述有源顶部管芯和所述伪管芯之间的间隙中的模塑料。
在一些实施例中，所述伪管芯中不包括有源集成电路。
在一些实施例中，所述伪管芯是空白管芯，所述空白管芯中不包括任何集成电路。
在一些实施例中，所述伪管芯是晶圆的一部分，并且没有从所述晶圆切割掉。
根据本发明的又一个方面，提供了一种方法，所述方法包括：
将多个有源顶部管芯接合到底部晶圆，其中所述多个有源顶部管芯的每个均通过电连接件接合到在所述底部晶圆中的多个相同的芯片中的一个；
将多个伪管芯附接到所述多个相同的芯片，其中所述多个伪管芯的每个均通过多个管芯附接膜中的一个附接到多个相同的芯片中的一个，并且其中所述多个伪管芯通过所述多个管芯附接膜与所述多个相同的芯片电隔离；和，
将模塑料填充到所述多个有源顶部管芯和所述多个伪管芯之间的间隙内。
在一些实施例中，所述方法进一步包括：在施加所述模塑料的步骤之前，将伪管芯附接到在所述底部晶圆中的不完整的底部芯片，其中所述模塑料与所述伪管芯物理接触。
在一些实施例中，所述方法进一步包括：在填充所述模塑料的步骤之后，使用粘接剂将载具附接到所述底部晶圆；对在所述底部晶圆中的衬底进行背侧研磨以暴露在所述底部晶圆中的硅通孔；和在所述底部晶圆的背侧上形成背侧互连结构；和切割所述底部晶圆以形成多个封装件，其中所述多个封装件中的每个均包括所述多个有源顶部管芯中的一个和所述多个伪管芯中的一个。
在一些实施例的方法中，没有电连接件将所述多个伪管芯中的任意一个与所述多个相同的芯片中的任意一个电连接。
在一些实施例的方法中，所述多个伪管芯是在其中没有集成电路的空白管芯。
在一些实施例的方法中，所述多个伪管芯是在其中没有低-k电介质层、金属线和通孔的硅管芯。
附图说明
为了更完整地理解本发明实施例及其优点，现将结合附图所进行的以下描述作为参考，其中：
图1到图6是根据各种实施例的在封装件制造的中间阶段的截面图，其中，伪管芯接合到在晶圆上的底部芯片。
图7和图8示出了根据各种可选实施例的在封装件制造的中间阶段的截面图，其中，伪管芯接合到离散的底部芯片。
具体实施方式
下面，详细讨论本发明各实施例的制造和使用。然而，应该理解，本发明提供了许多可以在各种具体环境中实现的可应用的概念。所讨论的具体实施例仅仅示出了制造和使用本发明的具体方式，而不用于限制本发明的范围。
根据各种实施例，提供了封装结构和用于形成封装结构的方法。举例说明了形成封装结构的中间阶段。阐述了不同实施例的差别。遍及各个视图和示例的实施例，相同的参考标号用于标识相同的元件。
图1A示出了底部晶圆20的俯视图。在一种实施例中，底部晶圆20是一种器件晶圆，器件晶圆包括半导体衬底38(图1A中未显示，请参考图1B)，以及形成在半导体衬底38的表面上的有源器件诸如晶体管(图中未显示)。半导体衬底38可以是硅衬底，或者由其它半导体材料形成。底部晶圆20包括在其中的多个相同的底部芯片24，其中底部芯片24可以彼此相同。切割线26将底部芯片24彼此隔离开。多个顶部管芯30包括有源顶部管芯30A和伪管芯30B，所述顶部管芯30接合在底部芯片24上。在整个描述中，术语“有源管芯”和“有源顶部管芯”是指具有电气功能的管芯或者芯片，所述电气功能有助于最终得到的封装件的电气操作，而术语“伪管芯”是指不具有任何电气功能的管芯或者芯片，并且所述伪管芯对最终得到的封装件的电气操作不起作用。有源顶部管芯30可以是器件管芯，也可以是封装件，该封装件包括接合在其它封装元件上的器件管芯，如封装衬底，插入件(interposer)或者类似物。
图1B示出了图1A中显示的结构的截面图，其中截面图沿图1A中的横穿线1B-1B的平面得到。底部芯片24可以是有源芯片，包括有源器件，接触插塞，金属线，通孔等(这些形成在衬底38的顶部表面38A上)，尽管它们未在图1B中显示。如图1B所示，底部芯片24可以与一个或者多个有源顶部管芯30A接合。电连接件32将有源顶部管芯30A接合到底部管芯24。电连接件32可以焊接凸点，粘合金属和金属的粘接剂，接合到金属柱的焊料突块或者类似物，并且可以用于在底部芯片24和有源顶部管芯30A之间传导电信号。因此，有源顶部管芯30A中的集成电路器件例如晶体管(未显示)与在底部芯片24中的器件电连接。在一种实施例中，电连接件32与半导体衬底38中的衬底通孔(TSV，有时也被称为硅通孔)36电连接。TSV36从衬底38的顶部表面38A延伸至衬底38的顶部表面38A和底部表面38B之间的中间水平位置。
伪管芯30B附接到底部管芯24，例如，通过管芯附接膜40，管芯附接膜40可以是基于聚合物的胶粘物。可选地，管芯附接膜40可以是能在受热时固化的热塑性薄膜。在一些实施例中，管芯附接膜40可以是在暴露在光线下时失去粘性的粘接剂。伪管芯30B可以是空白管芯，例如可以是半导体管芯(如硅管芯)，其不具有有源集成电路器件如晶体管，和/或无源器件如电阻器，电容器，和/或诸如此类的器件。伪管芯30B也可以没有低k电介质层，金属线，通孔，和/或类似物。在一些其它实施例中，伪管芯30B可以是电介质管芯。在又一些其它实施例中，伪管芯30B可以再利用在测试中失败的劣质管芯，并因此可以包括本文中诸如晶体管之类的集成电路。然而，如果可以的话，在伪管芯30B中的集成电路器件在最终得到的封装件60(图5)的操作中不执行任何电气功能，并且不被供电。
管芯附接膜40可以由电绝缘材料形成，并且可以使伪管芯30B和底部芯片24电绝缘。尽管图1A示出了接合底部芯片24的单个伪管芯30B，在可替代的实施例中，多个伪管芯30B可以接合到同一底部芯片24上。
再参考图1A，一些伪管芯30B接合到底部芯片24上，底部芯片24是具有矩形形状的完整的芯片，并且是功能性芯片。另外的伪管芯30B也可以接合到不完整的底部芯片24’上。不完整的底部芯片24’位于晶圆20的边缘，并且不具有矩形形状。不完整的底部芯片24’不封装为供使用的产品。因此，没有有源顶部管芯30A接合到不完整的底部芯片24’上。
图2A和图2B示出了模制工艺。模塑料44填充在有源顶部管芯30A和伪管芯30B之间的间隙内。模塑料44的顶部表面可以高于有源顶部管芯30A和伪管芯30B的顶部表面。然后进行固化工艺以固化模塑料44。
图2A示出了通过横穿图1A中的线1B-1B的同一平面得到的截面图。如图2A所示，模塑料44与有源顶部管芯30A，伪管芯30B，管芯附接膜40和底部芯片24物理接触。图2B示出了不完整的底部芯片24’的截面图，其中，其是从横穿图1A中的线2B-2B同一平面获得的截面图。如图2B所示，管芯附接膜40使伪管芯30B接合不完整的管芯24’，并且模塑料44可以与管芯附接膜40，伪管芯30B，和不完整的管芯24’物理接触。
然后，如图3所示，进行平坦化例如研磨以去除过多的模塑料44，以便模塑料44的顶部表面44A是平的。在一实施例中，进行平坦化直到暴露出有源顶部管芯30A的顶部表面30A和伪管芯30B。
在图1A示例的实施例中，接合到同一底部芯片24上的有源顶部管芯30A的整个俯视区域小于底部芯片24的俯视区域。此外，底部芯片24的芯片区域的很大一部分没有被有源顶部管芯30A覆盖。这导致有源顶部管芯30A相互之间形成大间隙，并因此，在如图3所示的结构中，如果伪管芯30B不存在，模塑料44会有高图案密度，特别是在包括大间隙的芯片区域。另一方面，在一些包括有源顶部管芯30A的其他芯片区域，塑料膜44的图案密度低。通过插入伪管芯30B，遍及晶圆20的塑料膜44的图案密度更均匀。这可以帮助降低最终得到的封装件的弯曲(例如如图3中所示的结构)，最终得到的封装件包括底部晶圆20，顶部管芯30和模塑料44。
参考图4，如图3所示的封装件结构被翻转颠倒。塑料膜44和顶部管芯30粘接(接合)在载具48上，例如，通过粘接剂50。在一实施例中，粘接剂50是光脱粘膜，它在暴露于光线时失去粘合性。例如，粘接剂50可以是紫外线胶(UV)。粘接剂50也可以是热脱粘膜，它在受热时失去粘合性。粘接剂50也可以由与管芯附接膜40的材料基本相同的材料形成。在一个示例性的形成工艺中，进行背侧研磨以研磨衬底38，直到露出TSV36。
参考图5，形成底部芯片24(和底部晶圆20)的背侧互连结构。在一个示例性的实施例中，背侧互连结构包括电介质层52，和焊盘/再分配线54。焊盘/再分配线54电连接TSV。其次，连接件56可以设置或者形成在焊盘54上。在一些实施例中，连接件56是焊球或者焊接凸点，连接件56被设置或者形成以便回焊。在可选实施例中，连接件56可以包括用于粘合金属与金属的粘接剂，接合到金属柱的焊接凸点，或者类似物，并且连接件56可用于在芯片24和另一封装元件(例如，器件管芯，插入件，封装衬底或者印刷电路板(PCB))之间传导电信号。
接下来，如图6所示，将载具48与晶圆20分离(不再接合)(例如通过将图4所示的粘接剂暴露在光中)，以致可以去除粘接剂50和载具48。然后进行切割管芯步骤以将晶圆20切割开从而形成多个封装件60，其中，多个封装件60中的一个在图6中显示。在最终得到的封装件60中，伪管芯30B保留，并且伪管芯30B在后续的封装工艺后(例如，将封装件60接合到封装衬底，插入件，印刷电路板(PCB)等)没有被去除。另外，在封装件60被使用以及被供电时，伪管芯30B仍然存在。
图7和图8示出了根据可选实施例的在封装件结构的形成的中间阶段的截面图。除非另有说明，在这些实施例中的参考标号表示如图1至图6中所示的实施例中的相同元件。参考图7，提供了底部芯片24。需要指出的是，底部芯片24可以包括有源器件，接触插塞，金属线，通孔等，尽管图7中未显示它们。在一些实施例中，底部芯片24已经从相应的晶圆锯开并分离，因此这以后也被称为底部管芯24。在可选实施例中，底部芯片24是还没有切割分开的晶圆的一部分。晶圆可以包括多个与示例的底部芯片24大致相同的芯片。背侧互连结构包括形成在底部管芯24上的背侧电介质层52和金属线/焊盘54。连接件56可以任选地形成在背侧互连结构上，并且电连接在底部管芯24中的TSV36和器件诸如晶体管。
在图8中，有源顶部管芯30A接合底部管芯24，并且伪管芯30B附接底部管芯24。接合方法，附接方法，和各自的材料可以基本与图1B中所示的一致，因此在此不再赘述。接下来，模塑料44被应用，固化，并且可选地被研磨。所得的结构可以基本与如图6所示的一致。在图7和图8中的底部芯片是晶圆的一部分的实施例中，可以进行管芯切割步骤以将晶圆切割并分离开，使得与图8中所类似的芯片彼此分离，并且每一个芯片均具有如图8中的结构。在实施例中，通过伪管芯附接到晶圆或者底部管芯上，模塑料的图案密度可以更均匀，因此可以降低在最终得到的封装件中的弯曲。弯曲降低导致最终得到的封装件中不同层之间的分层降低。结果，模塑料具有更好的抗潮渗透性。因而提高了封装的可靠性。伪管芯的使用使得在最终得到的封装件中更少地使用模塑料，并因此降低了来自模塑料的排气。
根据一些实施例，器件包括底部芯片和接合在底部芯片上的有源顶部管芯。伪管芯附接到底部芯片上。伪管芯与底部芯片电隔离。
根据一些其它实施例，器件包括底部晶圆，所述底部晶圆包括多个相同的芯片。多个有源顶部管芯接合到底部晶圆，其中多个有源顶部管芯中的每个均通过电连接件接合多个相同的芯片。多个伪管芯附接到底部芯片，其中，多个伪管芯中的每个附接到多个相同芯片中的一个。所述器件进一步包括多个管芯附接膜，其中多个管芯附接膜中的每一个将多个伪管芯中的一个粘附到在多个相同芯片中的一个。
根据又一些其它实施例，一种方法包括将多个有源顶部管芯接合到底部晶圆上。多个有源顶部管芯中的每个均通过电连接件接合到在底部晶圆中的多个相同芯片中的一个。多个伪管芯附接到多个相同的芯片。多个伪管芯中的每个均通过多个管芯附接膜中的一个附接到多个相同芯片中的一个。多个伪管芯通过多个管芯附接膜与多个相同的芯片电隔离。将模塑料填充到多个有源顶部管芯和多个管芯伪管芯之间的间隙中。
虽然已经对本发明进行详细的描述，应当理解，本发明其它变化的实施方式仍落入本发明的始终和保护范围之内。此外，本申请的范围不局限于说明书中所描述的工艺、机器、制造以及要素组合、装置、方法和步骤的特定实施方式。本领域技术人员根据本发明容易得到目前存在的或随后改进的工艺、机器、制造、要素组合、装置、方法或步骤，根据本发明可实现大体相同的功能或实现与本文所描述的相关实施方式大体相同的结果。因此，所附的权利要求包括在这些工艺、机器、制造、要素组合、装置、方法或步骤的范围内。另外每项权利要求构成独立的实施方式，并且各种权利和实施方式的组合同样属于本发明的范围。

Claims (10)

1.一种器件，所述器件包括：
底部芯片；
有源顶部管芯，接合到所述底部芯片；和
伪管芯，附接到所述底部芯片，其中所述伪管芯与所述底部芯片电隔离。
2.如权利要求1所述的器件，其中所述伪管芯选自基本上由以下组成的组中：在其中没有集成电路的空白管芯，在其中没有低k电介质层、金属线、和通孔的硅管芯，和它们的组合。
3.如权利要求1所述的器件，其中所述伪管芯设置成不与电源连接。
4.如权利要求1所述的器件，其中所述有源顶部管芯接合到所述底部芯片并且通过电连接件与所述底部芯片电连接，其中所述伪管芯通过粘接剂粘附到所述底部芯片，并且其中所述伪管芯通过所述粘接剂与所述底部芯片电隔离。
5.一种器件，所述器件包括：
底部芯片，包括：
衬底；
通孔，从所述衬底的第一侧延伸至所述衬底的第二侧；
第一连接件，在所述衬底的所述第一侧上；和
第二连接件，在所述衬底的所述第二侧上，其中所述第一连接件通过所述通孔与所述第二连接件电连接；
有源顶部管芯，在所述衬底的所述第一侧上，所述有源顶部管芯通过所述第一连接件接合到所述底部芯片；
伪管芯，在所述衬底的所述第一侧上；和
管芯附接膜，使所述伪管芯附接到所述底部芯片。
6.如权利要求5所述的器件，其中所述伪管芯设置成不与任何电源连接。
7.如权利要求6所述的器件，其中所述管芯附接膜包括介电材料，并且其中没有导电部件穿透所述管芯附接膜。
8.一种方法，所述方法包括：
将多个有源顶部管芯接合到底部晶圆，其中所述多个有源顶部管芯的每个均通过电连接件接合到在所述底部晶圆中的多个相同的芯片中的一个；
将多个伪管芯附接到所述多个相同的芯片，其中所述多个伪管芯的每个均通过多个管芯附接膜中的一个附接到多个相同的芯片中的一个，并且其中所述多个伪管芯通过所述多个管芯附接膜与所述多个相同的芯片电隔离；和，
将模塑料填充到所述多个有源顶部管芯和所述多个伪管芯之间的间隙内。
9.如权利要求8所述的方法，进一步包括：
在施加所述模塑料的步骤之前，将伪管芯附接到在所述底部晶圆中的不完整的底部芯片，其中所述模塑料与所述伪管芯物理接触。
10.如权利要求8所述的方法，进一步包括：
在填充所述模塑料的步骤之后，使用粘接剂将载具附接到所述底部晶圆；
对在所述底部晶圆中的衬底进行背侧研磨以暴露在所述底部晶圆中的硅通孔；和
在所述底部晶圆的背侧上形成背侧互连结构；和
切割所述底部晶圆以形成多个封装件，其中所述多个封装件中的每个均包括所述多个有源顶部管芯中的一个和所述多个伪管芯中的一个。
CN201210120748.6A 2011-11-16 2012-04-23 形成芯片在晶圆的总成的方法 Active CN103117279B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB201301015A GB2502172A (en) 2012-04-23 2013-01-21 Operation Control Device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/298,126 2011-11-16
US13/298,126 US8779599B2 (en) 2011-11-16 2011-11-16 Packages including active dies and dummy dies and methods for forming the same

Publications (2)

Publication Number Publication Date
CN103117279A true CN103117279A (zh) 2013-05-22
CN103117279B CN103117279B (zh) 2016-10-05

Family

ID=48279821

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201210120748.6A Active CN103117279B (zh) 2011-11-16 2012-04-23 形成芯片在晶圆的总成的方法

Country Status (3)

Country Link
US (2) US8779599B2 (zh)
CN (1) CN103117279B (zh)
TW (1) TWI555074B (zh)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104241229A (zh) * 2013-06-21 2014-12-24 三星电子株式会社 具有贯穿电极的半导体封装及其制造方法
CN107845611A (zh) * 2016-09-19 2018-03-27 台湾积体电路制造股份有限公司 封装结构
US10026703B2 (en) 2016-08-11 2018-07-17 Samsung Electro-Mechanics Co., Ltd. Fan-out semiconductor package
TWI667748B (zh) * 2016-08-11 2019-08-01 南韓商三星電子股份有限公司 扇出型半導體封裝
CN110112115A (zh) * 2018-02-01 2019-08-09 台湾积体电路制造股份有限公司 集成电路封装件及其形成方法
US10446322B2 (en) 2016-11-16 2019-10-15 Samsung Electro-Mechanics Co., Ltd. Composite electronic component and board having the same mounted thereon
WO2020000933A1 (zh) * 2018-06-25 2020-01-02 华进半导体封装先导技术研发中心有限公司 一种控制形变的扇出封装结构及其制造方法

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8697542B2 (en) * 2012-04-12 2014-04-15 The Research Foundation Of State University Of New York Method for thin die-to-wafer bonding
JP5878823B2 (ja) * 2012-05-15 2016-03-08 太陽誘電株式会社 複合電子部品
US9633869B2 (en) 2013-08-16 2017-04-25 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with interposers and methods for forming the same
US9093337B2 (en) 2013-09-27 2015-07-28 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for controlling warpage in packaging
US9224697B1 (en) * 2013-12-09 2015-12-29 Xilinx, Inc. Multi-die integrated circuits implemented using spacer dies
US9613931B2 (en) 2015-04-30 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out stacked system in package (SIP) having dummy dies and methods of making the same
US10043769B2 (en) * 2015-06-03 2018-08-07 Micron Technology, Inc. Semiconductor devices including dummy chips
US10180454B2 (en) * 2015-12-01 2019-01-15 Texas Instruments Incorporated Systems and methods of testing multiple dies
US10283479B2 (en) * 2016-05-20 2019-05-07 Taiwan Semiconductor Manufacturing Co., Ltd. Package structures and methods of forming the same
KR102609312B1 (ko) * 2016-09-13 2023-12-01 삼성전자주식회사 웨이퍼 워피지 개선 장치 및 방법
US10153222B2 (en) * 2016-11-14 2018-12-11 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods of forming the same
US10529690B2 (en) * 2016-11-14 2020-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods of forming the same
US11527454B2 (en) * 2016-11-14 2022-12-13 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods of forming the same
US10297471B2 (en) 2016-12-15 2019-05-21 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out structure and method of fabricating the same
WO2018125162A1 (en) * 2016-12-29 2018-07-05 Intel Corporation Semiconductor package having passive support wafer
US9865567B1 (en) * 2017-02-02 2018-01-09 Xilinx, Inc. Heterogeneous integration of integrated circuit device and companion device
US10431517B2 (en) 2017-08-25 2019-10-01 Advanced Micro Devices, Inc. Arrangement and thermal management of 3D stacked dies
US10665582B2 (en) * 2017-11-01 2020-05-26 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing semiconductor package structure
US10957672B2 (en) * 2017-11-13 2021-03-23 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of manufacturing the same
US10797005B2 (en) * 2017-11-27 2020-10-06 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package and method for manufacturing the same
US10312221B1 (en) * 2017-12-17 2019-06-04 Advanced Micro Devices, Inc. Stacked dies and dummy components for improved thermal performance
KR102397902B1 (ko) * 2018-01-29 2022-05-13 삼성전자주식회사 반도체 패키지
KR20190115911A (ko) * 2018-04-04 2019-10-14 엘지이노텍 주식회사 인쇄회로기판 및 인쇄회로기판 스트립
US11004803B2 (en) * 2018-07-02 2021-05-11 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy dies for reducing warpage in packages
US10790210B2 (en) * 2018-07-31 2020-09-29 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and manufacturing method thereof
US11508707B2 (en) * 2019-05-15 2022-11-22 Mediatek Inc. Semiconductor package with dummy MIM capacitor die
US11901333B2 (en) * 2019-10-08 2024-02-13 Intel Corporation No mold shelf package design and process flow for advanced package architectures
KR20210135111A (ko) * 2020-05-04 2021-11-12 삼성전자주식회사 반도체 패키지의 제조 방법
KR20210158587A (ko) 2020-06-24 2021-12-31 삼성전자주식회사 반도체 패키지 및 반도체 패키지의 제조 방법
KR20220008093A (ko) 2020-07-13 2022-01-20 삼성전자주식회사 반도체 패키지 및 반도체 패키지의 제조 방법
US11515268B2 (en) * 2021-03-05 2022-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and manufacturing method thereof
US11855003B2 (en) * 2021-05-13 2023-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of fabricating the same

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1400661A (zh) * 2002-08-28 2003-03-05 威盛电子股份有限公司 具有平衡结构的构装集成电路
CN102169841A (zh) * 2010-02-03 2011-08-31 马维尔国际贸易有限公司 凹入的半导体基底和相关技术
US20110221053A1 (en) * 2010-03-11 2011-09-15 Qualcomm Incorporated Pre-processing to reduce wafer level warpage
CN102194804A (zh) * 2010-03-04 2011-09-21 台湾积体电路制造股份有限公司 封装结构

Family Cites Families (63)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4811082A (en) 1986-11-12 1989-03-07 International Business Machines Corporation High performance integrated circuit packaging structure
US5075253A (en) 1989-04-12 1991-12-24 Advanced Micro Devices, Inc. Method of coplanar integration of semiconductor IC devices
US4990462A (en) 1989-04-12 1991-02-05 Advanced Micro Devices, Inc. Method for coplanar integration of semiconductor ic devices
US5380681A (en) 1994-03-21 1995-01-10 United Microelectronics Corporation Three-dimensional multichip package and methods of fabricating
US6002177A (en) 1995-12-27 1999-12-14 International Business Machines Corporation High density integrated circuit packaging with chip stacking and via interconnections
US6213376B1 (en) 1998-06-17 2001-04-10 International Business Machines Corp. Stacked chip process carrier
US6281042B1 (en) 1998-08-31 2001-08-28 Micron Technology, Inc. Structure and method for a high performance electronic packaging assembly
US6271059B1 (en) 1999-01-04 2001-08-07 International Business Machines Corporation Chip interconnection structure using stub terminals
US6461895B1 (en) 1999-01-05 2002-10-08 Intel Corporation Process for making active interposer for high performance packaging applications
US6229216B1 (en) 1999-01-11 2001-05-08 Intel Corporation Silicon interposer and multi-chip-module (MCM) with through substrate vias
US6243272B1 (en) 1999-06-18 2001-06-05 Intel Corporation Method and apparatus for interconnecting multiple devices on a circuit board
US6355501B1 (en) 2000-09-21 2002-03-12 International Business Machines Corporation Three-dimensional chip stacking assembly
KR100364635B1 (ko) 2001-02-09 2002-12-16 삼성전자 주식회사 칩-레벨에 형성된 칩 선택용 패드를 포함하는 칩-레벨3차원 멀티-칩 패키지 및 그 제조 방법
KR100868419B1 (ko) * 2001-06-07 2008-11-11 가부시끼가이샤 르네사스 테크놀로지 반도체장치 및 그 제조방법
KR100394808B1 (ko) 2001-07-19 2003-08-14 삼성전자주식회사 웨이퍼 레벨 적층 칩 패키지 및 그 제조 방법
KR100435813B1 (ko) 2001-12-06 2004-06-12 삼성전자주식회사 금속 바를 이용하는 멀티 칩 패키지와 그 제조 방법
WO2003051637A1 (fr) * 2001-12-18 2003-06-26 Sony Corporation Tete d'impression
DE10200399B4 (de) 2002-01-08 2008-03-27 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Erzeugung einer dreidimensional integrierten Halbleitervorrichtung und dreidimensional integrierte Halbleitervorrichtung
US6661085B2 (en) 2002-02-06 2003-12-09 Intel Corporation Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack
US6887769B2 (en) 2002-02-06 2005-05-03 Intel Corporation Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same
US6975016B2 (en) 2002-02-06 2005-12-13 Intel Corporation Wafer bonding using a flexible bladder press and thinned wafers for three-dimensional (3D) wafer-to-wafer vertical stack integration, and application thereof
US6762076B2 (en) 2002-02-20 2004-07-13 Intel Corporation Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices
US6600222B1 (en) 2002-07-17 2003-07-29 Intel Corporation Stacked microelectronic packages
JP2004071947A (ja) * 2002-08-08 2004-03-04 Renesas Technology Corp 半導体装置
US6790748B2 (en) 2002-12-19 2004-09-14 Intel Corporation Thinning techniques for wafer-to-wafer vertical stacks
US6908565B2 (en) 2002-12-24 2005-06-21 Intel Corporation Etch thinning techniques for wafer-to-wafer vertical stacks
US6924551B2 (en) 2003-05-28 2005-08-02 Intel Corporation Through silicon via, folded flex microelectronic package
US6946384B2 (en) 2003-06-06 2005-09-20 Intel Corporation Stacked device underfill and a method of fabrication
US7320928B2 (en) 2003-06-20 2008-01-22 Intel Corporation Method of forming a stacked device filler
KR100537892B1 (ko) 2003-08-26 2005-12-21 삼성전자주식회사 칩 스택 패키지와 그 제조 방법
US7345350B2 (en) 2003-09-23 2008-03-18 Micron Technology, Inc. Process and integration scheme for fabricating conductive components, through-vias and semiconductor components including conductive through-wafer vias
KR100621992B1 (ko) 2003-11-19 2006-09-13 삼성전자주식회사 이종 소자들의 웨이퍼 레벨 적층 구조와 방법 및 이를이용한 시스템-인-패키지
KR100570514B1 (ko) 2004-06-18 2006-04-13 삼성전자주식회사 웨이퍼 레벨 칩 스택 패키지 제조 방법
KR100618837B1 (ko) 2004-06-22 2006-09-01 삼성전자주식회사 웨이퍼 레벨 패키지를 위한 얇은 웨이퍼들의 스택을형성하는 방법
US7307005B2 (en) 2004-06-30 2007-12-11 Intel Corporation Wafer bonding with highly compliant plate having filler material enclosed hollow core
JP4265997B2 (ja) * 2004-07-14 2009-05-20 富士通マイクロエレクトロニクス株式会社 半導体装置及びその製造方法
US7087538B2 (en) 2004-08-16 2006-08-08 Intel Corporation Method to fill the gap between coupled wafers
US7354800B2 (en) * 2005-04-29 2008-04-08 Stats Chippac Ltd. Method of fabricating a stacked integrated circuit package system
US7317256B2 (en) 2005-06-01 2008-01-08 Intel Corporation Electronic packaging including die with through silicon via
US7557597B2 (en) 2005-06-03 2009-07-07 International Business Machines Corporation Stacked chip security
US7402515B2 (en) 2005-06-28 2008-07-22 Intel Corporation Method of forming through-silicon vias with stress buffer collars and resulting devices
US7432592B2 (en) 2005-10-13 2008-10-07 Intel Corporation Integrated micro-channels for 3D through silicon architectures
US7528494B2 (en) 2005-11-03 2009-05-05 International Business Machines Corporation Accessible chip stack and process of manufacturing thereof
US7410884B2 (en) 2005-11-21 2008-08-12 Intel Corporation 3D integrated circuits using thick metal for backside connections and offset bumps
US7402442B2 (en) 2005-12-21 2008-07-22 International Business Machines Corporation Physically highly secure multi-chip assembly
US7279795B2 (en) 2005-12-29 2007-10-09 Intel Corporation Stacked die semiconductor package
JP4958257B2 (ja) * 2006-03-06 2012-06-20 オンセミコンダクター・トレーディング・リミテッド マルチチップパッケージ
JP5143451B2 (ja) * 2007-03-15 2013-02-13 オンセミコンダクター・トレーディング・リミテッド 半導体装置及びその製造方法
US7576435B2 (en) 2007-04-27 2009-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Low-cost and ultra-fine integrated circuit packaging technique
US20080284037A1 (en) * 2007-05-15 2008-11-20 Andry Paul S Apparatus and Methods for Constructing Semiconductor Chip Packages with Silicon Space Transformer Carriers
KR101213175B1 (ko) 2007-08-20 2012-12-18 삼성전자주식회사 로직 칩에 층층이 쌓인 메모리장치들을 구비하는반도체패키지
JP2009212315A (ja) * 2008-03-04 2009-09-17 Elpida Memory Inc 半導体装置及びその製造方法
JP4828559B2 (ja) * 2008-03-24 2011-11-30 新光電気工業株式会社 配線基板の製造方法及び電子装置の製造方法
US7973310B2 (en) 2008-07-11 2011-07-05 Chipmos Technologies Inc. Semiconductor package structure and method for manufacturing the same
JP5199855B2 (ja) * 2008-12-17 2013-05-15 三井ホーム株式会社 木造枠組壁
US7915080B2 (en) * 2008-12-19 2011-03-29 Texas Instruments Incorporated Bonding IC die to TSV wafers
US8674513B2 (en) * 2010-05-13 2014-03-18 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures for substrate
US8648615B2 (en) * 2010-06-28 2014-02-11 Xilinx, Inc. Testing die-to-die bonding and rework
TWI460834B (zh) * 2010-08-26 2014-11-11 Unimicron Technology Corp 嵌埋穿孔晶片之封裝結構及其製法
US9082869B2 (en) * 2010-09-14 2015-07-14 Terapede Systems, Inc. Apparatus and methods for high-density chip connectivity
US8421073B2 (en) * 2010-10-26 2013-04-16 Taiwan Semiconductor Manufacturing Company, Ltd. Test structures for through silicon vias (TSVs) of three dimensional integrated circuit (3DIC)
KR101215975B1 (ko) * 2011-02-28 2012-12-27 에스케이하이닉스 주식회사 반도체 장치 및 이의 제조방법
US8922230B2 (en) * 2011-05-11 2014-12-30 Taiwan Semiconductor Manufacturing Company, Ltd. 3D IC testing apparatus

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1400661A (zh) * 2002-08-28 2003-03-05 威盛电子股份有限公司 具有平衡结构的构装集成电路
CN102169841A (zh) * 2010-02-03 2011-08-31 马维尔国际贸易有限公司 凹入的半导体基底和相关技术
CN102194804A (zh) * 2010-03-04 2011-09-21 台湾积体电路制造股份有限公司 封装结构
US20110221053A1 (en) * 2010-03-11 2011-09-15 Qualcomm Incorporated Pre-processing to reduce wafer level warpage

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104241229A (zh) * 2013-06-21 2014-12-24 三星电子株式会社 具有贯穿电极的半导体封装及其制造方法
US10026703B2 (en) 2016-08-11 2018-07-17 Samsung Electro-Mechanics Co., Ltd. Fan-out semiconductor package
TWI667748B (zh) * 2016-08-11 2019-08-01 南韓商三星電子股份有限公司 扇出型半導體封裝
CN107845611A (zh) * 2016-09-19 2018-03-27 台湾积体电路制造股份有限公司 封装结构
US11721676B2 (en) 2016-09-19 2023-08-08 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure with dummy die
US10446322B2 (en) 2016-11-16 2019-10-15 Samsung Electro-Mechanics Co., Ltd. Composite electronic component and board having the same mounted thereon
CN110112115A (zh) * 2018-02-01 2019-08-09 台湾积体电路制造股份有限公司 集成电路封装件及其形成方法
CN110112115B (zh) * 2018-02-01 2021-10-22 台湾积体电路制造股份有限公司 集成电路封装件及其形成方法
WO2020000933A1 (zh) * 2018-06-25 2020-01-02 华进半导体封装先导技术研发中心有限公司 一种控制形变的扇出封装结构及其制造方法

Also Published As

Publication number Publication date
TWI555074B (zh) 2016-10-21
CN103117279B (zh) 2016-10-05
US9312149B2 (en) 2016-04-12
US8779599B2 (en) 2014-07-15
US20130119552A1 (en) 2013-05-16
TW201322319A (zh) 2013-06-01
US20140287553A1 (en) 2014-09-25

Similar Documents

Publication Publication Date Title
CN103117279A (zh) 形成芯片在晶圆的总成的方法
US9111870B2 (en) Microelectronic packages containing stacked microelectronic devices and methods for the fabrication thereof
CN104377171B (zh) 具有中介层的封装件及其形成方法
CN104364902B (zh) 半导体封装、其制造方法及封装体叠层
CN103996630B (zh) 封装半导体器件和封装器件及方法
CN103219309B (zh) 多芯片扇出型封装及其形成方法
CN103325703B (zh) 在封装件形成期间探测芯片
US11670624B2 (en) Integrated circuit module with integrated discrete devices
US20070284716A1 (en) Assembly Having Stacked Die Mounted On Substrate
KR101056747B1 (ko) 반도체 패키지 및 그 제조 방법
US11621243B2 (en) Thin bonded interposer package
KR20140130395A (ko) 반도체 디바이스 제조 방법
CN102903691A (zh) 半导体器件、封装方法和结构
US9147600B2 (en) Packages for multiple semiconductor chips
CN104037142B (zh) 封装对准结构及其形成方法
CN103021888B (zh) 用于制造包括高可靠性晶粒底填充的集成电路系统的方法
KR101332859B1 (ko) 원 레이어 섭스트레이트를 갖는 반도체 패키지를 이용한 팬 아웃 타입 반도체 패키지 및 이의 제조 방법
KR20150033937A (ko) 반도체 패키지 및 그 제작 방법
KR20150092015A (ko) 박형 샌드위치 임베디드 패키지
US20130075894A1 (en) Integrated circuit and method of making
CN102569275A (zh) 堆叠式半导体封装结构及其制造方法
KR101616272B1 (ko) 반도체 패키지 제작 방법
KR101745728B1 (ko) 반도체칩의 삼차원 적층 방법
US20240162206A1 (en) Load switch mounting for a semiconductor package
US9761535B1 (en) Interposer, semiconductor package with the same and method for preparing a semiconductor package with the same

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant