CN110112115B - 集成电路封装件及其形成方法 - Google Patents

集成电路封装件及其形成方法 Download PDF

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Publication number
CN110112115B
CN110112115B CN201811476004.1A CN201811476004A CN110112115B CN 110112115 B CN110112115 B CN 110112115B CN 201811476004 A CN201811476004 A CN 201811476004A CN 110112115 B CN110112115 B CN 110112115B
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die
substrate
integrated circuit
dummy die
dummy
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CN110112115A (zh
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侯上勇
黄松辉
黄冠育
胡宪斌
林于顺
黄贺昌
夏兴国
洪志杰
施应庆
高金福
魏文信
郭立中
吴集锡
余振华
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明的实施例提供了一种集成电路封装件及其形成方法。该方法包括将集成电路管芯附接至第一衬底。形成伪管芯。伪管芯附接至第一衬底且与集成电路管芯相邻。在第一衬底上方并且在伪管芯和集成电路管芯周围形成密封剂。平坦化密封剂、伪管芯和集成电路管芯，密封剂的最上表面与伪管芯的最上表面和集成电路管芯的最上表面大致齐平。去除伪管芯的内部部分。伪管芯的剩余部分形成环形结构。

Description

集成电路封装件及其形成方法
技术领域
本发明的实施例总体涉及半导体领域，更具体地，涉及集成电路封装件及其形成方法。
背景技术
半导体器件用在诸如个人电脑、手机、数码相机和其他电子设备的各种电子应用中。通常通过以下步骤来制造半导体器件：在半导体衬底上方依次沉积绝缘或介电层、导电层和半导体材料层；以及使用光刻来图案化各种材料层，以在各种材料层上形成电路组件和元件。通常在单个半导体晶圆上制造数十或数百个集成电路。通过沿着划线锯切集成电路来分割单个管芯。然后，将单个管芯单独地封装在多芯片模块中，或封装在其他类型的封装件中。
由于许多电子组件(例如，晶体管、二极管、电阻器、电容器等)的集成度的不断提高，半导体产业经历了快速发展。在很大程度上，集成度的这种提高源自最小特征尺寸的不断减小(例如，将半导体工艺节点减小至亚20nm节点)，这允许将多个组件集成到给定区域内。由于对小型化的需求，近来更高速度和更大带宽以及更低功耗和延迟已经得到发展，所以已经需要产生一种更小且更富创造性的半导体管芯封装技术。
随着半导体技术的进一步发展，已经出现了堆叠的半导体器件(例如，三维集成电路(3DIC))作为有效替代以进一步减小半导体器件的物理尺寸。在堆叠的半导体器件中，在不同的半导体晶圆上制造诸如逻辑、存储器、处理器电路等的有源电路。两个或多个半导体晶圆可以安装或堆叠在彼此的顶部上以进一步降低半导体器件的形状因子。叠层封装(POP)器件是一种类型的3DIC，其中，封装管芯然后将管芯与另一封装的管芯或多个管芯封装在一起。封装件上芯片(COP)器件是另一种类型的3DIC，其中，封装管芯，然后将管芯与另一管芯或多个管芯封装在一起。
发明内容
根据本发明的一个方面，提供了一种形成封装件的方法，包括：将集成电路管芯附接至第一衬底；形成伪管芯；将所述伪管芯附接至所述第一衬底，所述伪管芯与所述集成电路管芯相邻；在所述第一衬底上方并且在所述伪管芯和所述集成电路管芯周围形成密封剂；平坦化所述密封剂、所述伪管芯和所述集成电路管芯，所述密封剂的最上表面与所述伪管芯的最上表面和所述集成电路管芯的最上表面齐平；以及，去除所述伪管芯的内部部分，所述伪管芯的剩余部分形成环形结构。
根据本发明的另一个方面，提供了一种形成封装件的方法，包括：将集成电路管芯附接至第一衬底的第一侧；形成伪管芯，所述伪管芯包括位于所述伪管芯内的第一环形结构；将所述伪管芯附接至所述第一衬底的第一侧，所述伪管芯与所述集成电路管芯相邻；在所述第一衬底上方并且在所述伪管芯和所述集成电路管芯周围形成模塑料，所述模塑料的顶面与所述伪管芯的最上表面、所述第一环形结构的最上表面和所述集成电路管芯的最上表面齐平；去除所述第一环形结构，在去除所述第一环形结构之后，所述伪管芯分离成内部区和外围环形区；使所述伪管芯的内部区与所述第一衬底脱离，所述伪管芯的外围环形区形成第二环形结构；将功能组件放置在所述第二环形结构内且在所述第一衬底的第一侧上；以及将所述功能组件附接至所述第一衬底的第一侧。
根据本发明的又一个方面，提供了一种封装件，包括：衬底；第一集成电路管芯，接合至所述衬底的第一侧；环形结构，接合至与所述第一集成电路管芯相邻的所述衬底的第一侧；密封剂，位于所述衬底上方并且位于所述环形结构和所述第一集成电路管芯周围，所述密封剂的最上表面与所述环形结构的最上表面和所述第一集成电路管芯的最上表面齐平；以及功能组件，位于所述环形结构内并且接合至所述衬底的第一侧。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳地理解本发明的各个方面。应该注意，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增大或减小。
图1A、图1B和图2至图4示出根据一些实施例的在制造伪管芯期间的各个处理步骤的顶视图和截面图。
图5至图11示出根据一些实施例的在制造集成电路封装件期间的各个处理步骤的截面图。
图12A、图12B和图13至图15示出根据一些实施例的在制造伪管芯期间的各个处理步骤的顶视图和截面图。
图16A、图16B和图17至图24示出根据一些实施例的制造集成电路封装件期间的各个处理步骤的顶视图和截面图。
图25示出根据一些实施例的集成电路封装件的截面图。
图26示出根据一些实施例的集成电路封装件的截面图。
图27示出根据一些实施例的集成电路封装件的截面图。
图28示出根据一些实施例的集成电路封装件的截面图。
图29示出根据一些实施例的集成电路封装件的截面图。
图30示出根据一些实施例的集成电路封装件的截面图。
图31示出根据一些实施例的集成电路封装件的截面图。
图32是根据一些实施例示出的形成伪管芯的方法的流程图。
图33是根据一些实施例示出的形成集成电路封装件的方法的流程图。
图34是根据一些实施例示出的形成集成电路封装件的方法的流程图。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的特定实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件以直接接触的方式形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为了便于描述，在此可以使用诸如“在…下方”、“在…下面”、“下部”、“在…之上”、“上部”等空间相对术语以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，并且在此使用的空间相对描述符可以同样地作出相应的解释。
将相对于特定的上下文(即，集成电路封装件)中的实施例来描述实施例。然而，其他实施例也可以应用于其他电连接的组件，包括但不限于：叠层封装装配件、管芯至管芯装配件、晶圆至晶圆装配件、管芯至衬底装配件、管芯至晶圆装配件、封装装配中、衬底处理中、中介片中的组件等；或安装输入组件、板、管芯或其他组件；或用于封装或安装任何类型的集成电路或电组件的组合的连接件。这里描述的各个实施例允许在同一集成电路封装件中封装具有不同功能和尺寸(诸如，例如，高度)的功能组件(诸如，例如，集成电路管芯)。本文描述的各个实施例可以集成到衬底上晶圆上芯片(CoWoS)工艺和衬底上芯片上芯片(CoCoS)工艺中。
图1A、图1B和图2至图4示出根据一些实施例的在制造伪管芯(诸如图4所示的伪管芯401)期间的各个处理步骤的顶视图和截面图。图1A示出顶视图，而图1B和图2至图4示出沿图1A中的线BB’的截面图。首先参考图1A以及图1B，示出晶圆100的具有通过划线103(还称为切割线或切割区)分离的管芯区101的部分。如下面更详细地描述的，沿着划线103切割晶圆100以形成单个管芯(诸如图4所示的管芯401)。此外，如下面更详细地描述的，单个管芯用作牺牲管芯或伪管芯，其中，在后续的封装步骤中去除单个管芯的部分。因此，晶圆100可以不包括有源器件和无源器件，并且单个管芯可以是功能惰性管芯或伪管芯。
在一些实施例中，晶圆100包括衬底105。在一些实施例中，衬底105可由硅形成，尽管它还可由诸如硅、锗、镓、砷以及它们的组合的其他第III族、第IV族和/或第V族元素形成。衬底105还可以是绝缘体上硅(SOI)的形式。SOI衬底可以包括形成在绝缘层(如，掩埋氧化物等)上方的半导体材料(例如，硅、锗等)层，其中，绝缘层形成在硅衬底上。此外，可使用的其他衬底包括多层衬底、梯度衬底、混合取向衬底、它们的任何组合等。在其他实施例中，衬底105可以包括诸如，例如氧化物、氮化物、它们的组合等的介电材料。
进一步参考图1A和图1B，图案化衬底105以形成开口107和109。在一些实施例中，可以使用合适的光刻和蚀刻方法图案化衬底105，以形成开口107和109。在一些实施例中，用于图案化开口107和109的蚀刻工艺可包括各向异性干蚀刻工艺、中性离子束工艺等。在一些实施例中，可以在同一图案化工艺中同时形成开口107和开口109。在其他实施例中，可以在不同的图案化工艺中在不同的时间处单独形成开口107和开口109。在一些实施例中，开口107可以在后续的工艺步骤期间(诸如，例如，在后续的封装工艺期间)用作对准标记。如图1A所示，每个开口107具有矩形形状。在其他实施例中，根据对准标记的设计要求，开口107可以具有其他形状。还如图1A所示，在平面图中每个开口109具有环形形状。在所示实施例中，开口109的环形形状是矩形环形状。在其他实施例中，开口109的环形形状可以是环形、椭圆形环形形状、多边形环形状等。开口107具有宽度W1并且从衬底105的最上表面下面延伸至深度D1。开口109具有宽度W2并且从衬底105的最上表面下面延伸至深度D2。在一些实施例中，宽度W1介于约10μm和约30μm之间。在一些实施例中，深度D1介于约100μm和约150μm之间。在一些实施例中，比率W1/D1介于约0.1和约0.2之间。在一些实施例中，宽度W2介于约70μm和约150μm之间。在一些实施例中，深度D2介于约200μm和约220μm之间。在一些实施例中，比率W2/D2介于约0.35和约0.7之间。
参考图2，在衬底105上方且在开口107和109(参见图1A和图1B)中形成绝缘材料201。在一些实施例中，绝缘材料201可以包括诸如氮化硅、氧化硅、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)、它们的组合等的不可光图案化的绝缘材料，并且可以使用化学汽相沉积(CVD)、物理汽相沉积(ALD)、原子层沉积(ALD)、旋涂工艺、它们的组合等形成。在其他实施例中，绝缘材料201可以包括诸如聚苯并恶唑(PBO)、聚酰亚胺(PI)、苯并环丁烯(BCB)、它们的组合等的可光图案化的绝缘材料，并且可以使用旋涂工艺等来形成。在一些实施例中，图案化绝缘材料201以从衬底105的顶面去除绝缘材料201的部分。在一些实施例中，在图案化工艺之后，绝缘材料201的未去除部分保留在衬底105的顶面的由相应开口109围绕的部分上(参见图1A)。此外，在图案化工艺之后，绝缘材料201完全填充开口107和109(参见图1A和图1B)。在绝缘材料201包括可光图案化的绝缘材料的一些实施例中，可以使用合适的光刻技术来图案化绝缘材料201。在绝缘材料201包括不可光图案化的绝缘材料的其他实施例中，可以使用合适的光刻和蚀刻技术来图案化绝缘材料201。在一些实施例中，绝缘材料201的位于衬底105的顶面上的未去除部分具有介于约5μm和约15μm之间的厚度T1。
参考图3，在衬底105的顶面和绝缘材料201的剩余部分上形成导电层301。在一些实施例中，导电层301可以包括Ti、TiN、Ta、TaN、Cu、它们的组合等，并且可以使用PVD、ALD、CVD、它们的组合等来形成。在一些实施例中，导电层301的厚度介于约50nm和约100nm之间。在其他实施例中，可以省略导电层301。
参考图4，沿着划线103(参见图1A)切割晶圆100以形成单个管芯401。在一些实施例中，可以使用锯切、蚀刻、激光烧蚀、它们的组合等来切割晶圆100。管芯401还可以称为牺牲管芯或伪管芯。
图5至图11示出根据一些实施例的在制造集成电路封装件期间的各个处理步骤的截面图。首先参考图5，示出堆叠结构500，其中，堆叠结构500包括工件501和接合至工件501的顶面的集成电路(IC)管芯507和509。在一些实施例中，例如，工件501是诸如中介片晶圆的晶圆。在这种实施例中，将堆叠结构500分割成单个堆叠结构。在其他实施例中，例如，工件501是诸如中介片管芯的分割管芯。在工件501是中介片晶圆或中介片管芯的一些实施例中，工件501包括衬底503和位于衬底503内的诸如通孔(TV)505和线(未示出)的互连件。在一些实施例中，可使用与上面参考图1A和图1B描述的衬底105类似的材料和方法形成衬底503，因此这里不重复描述。在一些实施例中，互连件可包括诸如铜、铜合金、银、金、钨、钽、铝、它们的组合等的一种或多种导电材料。在一些实施例中，工件501可以不包括除互连件之外的有源器件和无源器件。
在一些实施例中，IC管芯507和509中的每个可以包括衬底、位于衬底上的一个或多个有源和/或无源器件，以及位于衬底和一个或多个有源和/或无源器件上方的互连结构(未单独示出)。在一些实施例中，可使用与上面参考图1A和图1B描述的衬底105类似的材料和方法形成IC管芯507和509的衬底，因此这里不重复描述。在一些实施例中，IC管芯507和509的一个或多个有源和/或无源器件可以包括诸如晶体管、电容器、电阻器、二极管、光电二极管、熔丝等的各种n型金属氧化物半导体(NMOS)和/或p型金属氧化物半导体(PMOS)器件。
IC管芯507和509的互连结构可以包括多个介电层(诸如层间介电(ILD)/金属间介电(IMD)层)和位于介电层内的互连件(诸如导线和通孔)。例如，可以通过本领域内已知的任何合适的方法(诸如，旋涂方法、CVD、等离子体增强的CVD(PECVD)、它们的组合等)由低K介电材料(诸如，磷硅酸盐玻璃(PSG)、硼磷硅酸盐玻璃(BPSG)、FSG、SiOxCy、旋涂玻璃、旋涂聚合物、硅碳材料、它们的化合物、它们的复合物、它们的组合等)形成介电层。在一些实施例中，可以使用例如镶嵌工艺、双镶嵌工艺、它们的组合等在介电层中形成互连件。在一些实施例中，互连件可以包括铜、铜合金、银、金、钨、钽、铝或它们的组合等。在一些实施例中，互连件可在衬底上形成的一个或多个有源和/或无源器件之间提供电连接。
进一步参考图5，IC管芯507和509中的每个可以是存储器管芯、逻辑管芯、3DIC管芯、CPU、GPU、xPU、SoC管芯、MEMS管芯等。在所示实施例中，IC管芯507和509具有不同的高度。在其他实施例中，IC管芯507和509可以具有相同的高度。在一些实施例中，使用连接件511将IC管芯507和509机械地附接且电附接至工件501。在一些实施例中，连接件511可包括微凸块、焊料凸块、金属柱凸块、其他合适的结构、它们的组合等。在一些实施例中，如图5所示，连接件511的每个可包括夹置在两个金属柱凸块5111和5112之间的焊料元件5113。在一些实施例中，金属柱凸块5111和5112可以包括诸如铜、钨、铝、银、金、它们的组合等的金属材料。在一些实施例中，焊料元件5113可包括诸如PbSn组合物的铅基焊料，包括InSb、锡、银和铜(“SAC”)组合物的无铅焊料，以及具有共同熔点的其他共晶材料，并且在电气应用中形成导电焊料连接件。作为实例，对于无铅焊料，可以使用不同组分的SAC焊料，诸如SAC 105(Sn98.5％、Ag 1.0％、Cu 0.5％)、SAC 305和SAC 405。无铅焊料还包括SnCu化合物，不使用银(Ag)和SnAg化合物，不使用铜(Cu)。
在一些实施例中，在将IC管芯507和509接合至工件501之前，在工件501的顶面上方形成金属柱凸块5111，并且在IC管芯507和509的底面上方形成金属柱凸块5112。后续地，在接合工艺之前对金属柱状凸块5111和5112中的一个或两个施加诸如焊膏的焊料材料。然后，例如，使用回流工艺通过焊料材料将金属柱凸块5111和5112接合在一起。如图5所示，焊料材料在金属柱凸块5111和5112之间形成焊料元件5113。在一些实施例中，形成金属柱凸块5111和5112的方法可以包括形成金属晶种层，在金属晶种层上方形成牺牲材料(诸如光刻胶材料)，图案化牺牲材料以形成开口，使用电化学镀工艺、化学镀工艺、ALD、PVD、它们的组合等在开口中沉积金属材料以形成金属柱凸块5111和5112，去除牺牲层，并且去除晶种层的暴露部分。在一些实施例中，在去除牺牲层之前，使用蒸发、电化学镀工艺、化学镀工艺、印刷、焊料转移、它们的组合等在位于开口中的金属材料上方形成焊料材料。
在一些实施例中，形成底部填充层513以围绕并保护连接件511。在一些实施例中，底部填充层513与连接件511直接接触。在一些实施例中，液体底部填充材料通过毛细作用进行分配并且进行固化以形成底部填充层513。在一些实施例中，底部填充层513包括其中分散有填料的环氧基树脂。填料可包括纤维、颗粒、其他合适的元素、它们的组合等。
参考图6，伪管芯401附接至IC管芯507。在一些实施例中，使用粘合剂601将伪管芯401附接至IC管芯507。在这种实施例中，粘合剂601形成在伪管芯401的前表面(面向IC管芯507的表面)的没有绝缘材料201的部分上。在其他实施例中，可以使用直接接合方法或其他合适的接合方法将伪管芯401附接至IC管芯507。
参考图7，在工件501上方，并且在IC管芯507和509以及伪管芯401周围形成密封剂701。在一些实施例中，密封剂701可包括具有分散在其中的填料的诸如环氧树脂、树脂、可模制聚合物、它们的组合等的模塑料。可在模塑料大致是液体时将其施加，并且然后通过化学反应将模塑料固化。填料可包括绝缘纤维、绝缘颗粒、其他合适的元素、它们的组合等。在一些实施例中，分散在密封剂701中的填料的尺寸和/或密度大于分散在底部填充层513中的填料的尺寸和/或密度。在其他实施例中，密封剂701可为紫外(UV)或热固化的聚合物，其中，该聚合物以能够设置在IC管芯507和509周围和之间以及IC管芯509与伪管芯401周围和之间的凝胶或可塑固体的形式进行涂覆。还在其他实施例中，例如，密封剂701可包括诸如氧化物的介电材料。在一些实施例中，可以对密封剂701实施平坦化工艺以去除密封剂701的多余部分，从而使得密封剂701的最上表面在平坦化工艺之后与伪管芯401的背侧表面401b大致齐平。在一些实施例中，平坦化工艺可包括CMP工艺、蚀刻工艺、研磨、它们的组合等。
参考图8，减薄工件501的背侧501b以暴露TV 505，并且在工件501的背侧501b上形成与相应TV 505电接触的导电连接件801。在一些实施例中，可以使用CMP工艺、蚀刻工艺、研磨、它们的组合等来减薄工件501的背侧501b。在一些实施例中，连接件801可以是可控的塌陷芯片连接(C4)凸块、球栅阵列(BGA)凸块等。在一些实施例中，连接件801可以包括与上面参考图5描述的焊料元件5113类似的焊料材料，并且这里不重复描述。
进一步参考图8，在形成连接件801之后，对伪管芯401和密封剂701实施进一步的平坦化工艺，以暴露设置在伪管芯401的开口109(参见图1A和图1B)中的绝缘材料201。在一些实施例中，平坦化工艺还可以去除IC管芯509的部分。在一些实施例中，在平坦化工艺之后，伪管芯401的背侧表面401b与密封剂701的顶面和IC管芯509的顶面大致齐平。在一些实施例中，平坦化工艺可包括CMP工艺、蚀刻工艺、研磨、它们的组合等。在一些实施例中，设置在伪管芯401的开口109(参见图1A和图1B)中的绝缘材料201保护IC管芯507在平坦化工艺期间免于受到污染。在工件501是晶圆的一些实施例中，可以对堆叠结构500实施分割工艺803以将堆叠结构500分离成单个堆叠结构800。分割工艺803可以包括锯切、蚀刻、激光烧蚀、它们的组合等。
参考图9，使用连接件801将堆叠结构800机械地附接且电附接至工件901。在连接件801由焊料材料形成的一些实施例中，可以实施回流工艺以将堆叠结构800接合至工件901。在一些实施例中，工件901可包括封装衬底、印刷电路板(PCB)、陶瓷衬底等。在一些实施例中，工件901可以包括位于工件901中和/或上的互连件(诸如导线和通孔)。在一些实施例中，在工件901的与堆叠结构800相对的一侧上形成连接件903。在一些实施例中，连接件903可以类似于连接件801，可以使用与上面参考图8描述的类似材料和方法形成连接件903，这里不再重复描述。在一些实施例中，形成底部填充层905以围绕并保护连接件801。在一些实施例中，可以使用与上面参考图5描述的底部填充层513类似的材料和方法来形成底部填充层905，并且这里不再重复描述。
进一步参考图9，在将堆叠结构800附接至工件901之后，从伪管芯401的开口109(参见图1A和图1B)去除绝缘材料201(参见图8)。在一些实施例中，使用激光钻孔工艺907去除绝缘材料201。在其他实施例中，可以使用诸如蚀刻工艺的其他合适的去除工艺来去除绝缘材料201。在去除绝缘材料201之后，将伪管芯401分离成内部区909和环形区911。
参考图10，去除伪管芯401的内部区909以暴露位于伪管芯401的环形区911中的开口1001。在一些实施例中，使用拾取和放置装置去除伪管芯401的内部区909。在其他实施例中，可以手动或使用其他合适的去除方法去除伪管芯401的内部区909。在一些实施例中，导电层301可以通过充当绝缘材料201和IC管芯507之间的缓冲并且通过防止绝缘材料201和IC管芯507之间的接合来辅助内部区909的去除工艺。在一些实施例中，开口1001暴露IC管芯507的顶面。在一些实施例中，开口1001的宽度W3介于约1mm和约30mm之间。在其他实施例中，宽度W3可以大于约30mm。
参考图11，在环形区911的开口1001中放置功能组件1101。在一些实施例中，功能组件1101可以是类似于IC管芯507和509的IC管芯。在这种实施例中，可以使用连接件1103将功能组件1101机械地连接且电连接至IC管芯507。在一些实施例中，可使用与上述参考图5描述的连接件511的材料和方法类似的材料和方法形成连接件1103，并且这里不重复描述。在其他实施例中，可以使用直接接合方法(诸如混合接合方法等)将功能组件1101机械地连接且电连接至IC管芯507。在其中所得到的封装件用于光子学应用的一些实施例中，功能组件1101可包括光子纤维模块、激光模块封装件(LaMP)、耦合器等。在这种实施例中，功能组件1101可以仅机械地附接至IC管芯509。
图12A、图12B和图13至图15示出根据一些实施例的在制造伪管芯(诸如图15所示的伪管芯1501)期间的各个处理步骤的顶视图和截面图。图12A示出晶圆1200的顶视图，而图12B和图13至图15示出沿图12A中的线BB’的截面图。图12A、图12B和图13至图15中所示的实施例类似于图1A、图1B和图2至图4中所示的实施例，其中，使用相同的参考标号来标记相同的部件，并且这里不再重复相同的部件和工艺步骤的详细描述。在图12A、图12B和图13至图15所示的实施例中，对绝缘材料201实施的图案化工艺还从开口109(参见图12A和图12B)去除绝缘材料201的部分以形成如图13所示的凹槽1301。因此，如图15所示，在切割晶圆1200之后形成的伪管芯1501包括凹槽1301，其中，导电层301沿凹槽1301的底部和侧壁延伸。在一些实施例中，凹槽1301具有介于约10μm和约50μm之间的深度D3。
图16A、图16B和图17至图24示出根据一些实施例的制造集成电路封装件期间的各个处理步骤的顶视图和截面图。图16A示出顶视图，而图16B和图17至图24示出沿图16A中的线BB’的截面图。首先参考图16A和图16B，示出工件1600。在一些实施例中，例如，工件1600是诸如中介片晶圆的晶圆。在其他实施例中，例如，工件1600是诸如中介片管芯的分割管芯。在一些实施例中，工件1600包括衬底1601，其中，可以使用与上面参照图5描述的工件501的衬底503类似的材料和方法形成衬底1601，并且这里不再重复描述。工件1600包括位于衬底1601内的诸如TV 1603和线(未示出)的互连件。在一些实施例中，可以使用与上面参考图5描述的工件501的互连件类似的材料和方法形成工件1600的互连件，并且这里不再重复描述。工件1600还包括连接件1605和插塞1607。在一些实施例中，如图16A所示，插塞1607在平面图中具有环形形状。在一些实施例中，插塞1607和伪管芯1501的凹槽1301(参见图15)具有类似的环形形状，从而使得插塞1607可以在后续工艺中插入到凹槽1301中。因此，凹槽1301的深度D3(参见图13)可以大于或等于插塞1607的高度，并且凹槽1301的宽度W2(参见图12B)可以大于或等于插塞1607的宽度。
在一些实施例中，可以在相同的工艺中同时形成连接件1605和插塞1607。在其他实施例中，可以在不同的工艺中在不同的时间处单独地形成连接件1605和插塞1607。在一些实施例中，连接件1605包括金属柱凸块16051和位于金属柱凸块16051上方的焊料元件16052。在一些实施例中，插塞1607包括金属基底16071和位于金属基底16071上方的焊料元件16072。在一些实施例中，可以使用与上面参考图5描述的金属柱凸块5111和5112类似的材料和方法形成，这里不再重复描述金属柱凸块16051和金属基底16071。在一些实施例中，可以使用与上面参考图5描述的焊料元件5113类似的材料和方法形成焊料元件16052和16072，并且这里不再重复描述。在一些实施例中，金属柱凸块16051和金属基底16071可包括相同的材料。在其他实施例中，金属柱凸块16051和金属基底16071可包括不同的材料。在一些实施例中，焊料元件16052和16072可包括相同的材料。在其他实施例中，焊料元件16052和16072可包括不同的材料。在一些实施例中，插塞1607可以不电连接至位于工件1600内或上的其他导电元件。在其他实施例中，插塞1607可以包括诸如聚苯并恶唑(PBO)、聚酰亚胺(PI)、苯并环丁烯(BCB)、它们的组合等的绝缘材料，并且可以使用合适的图案化工艺形成。
参考图17，使用连接件1605将IC管芯1701机械地连接且电连接至工件1600，以开始形成堆叠结构1700。在一些实施例中，可以使用与上面参考图5描述的IC管芯507和509类似的材料和方法形成IC管芯1701，并且这里不再重复描述。
参考图18，使用粘合剂1801将伪管芯1501附接至工件1600。在一些实施例中，插塞1607延伸到伪管芯1501的凹槽1301(参见图15)中并将伪管芯1501固定在工件1600上的期望位置。在其他实施例中，可以使用直接接合方法或其他合适的接合方法将伪管芯1501附接至工件1600。
参考图19，在连接件1605和IC管芯1701周围形成底部填充层1901。还在插塞1607和伪管芯1501周围形成底部填充层1903。在一些实施例中，可以使用与上面参考图5描述的底部填充层513类似的材料和方法来形成底部填充层1901和1903，这里不再重复描述。在一些实施例中，底部填充层1901和1903可包括相同的材料。在其他实施例中，底部填充层1901和1903可包括不同的材料。在其他实施例中，可以省略底部填充层1903。
在一些实施例中，在工件1600上方，并且在IC管芯1701和伪管芯1501周围形成密封剂1905。在一些实施例中，可以使用与上面参考图7描述的密封剂701类似的材料和方法来形成密封剂1905，并且这里不再重复描述。在一些实施例中，可以对密封剂1905实施平坦化工艺以去除密封剂1905的多余部分，从而使得在平坦化工艺之后密封剂1905的最上表面与伪管芯1501的背侧表面1501b和IC管芯1701的最上表面大致齐平。在一些实施例中，平坦化工艺可包括CMP工艺、蚀刻工艺、研磨、它们的组合等。在其中IC管芯1701的高度大于伪管芯1501的高度的一些实施例中，平坦化工艺还可以去除IC管芯1701的部分。
参考图20，减薄工件1600的背侧1600b以暴露TV 1603，并且在工件1600的背侧1600b上形成与相应的TV 1603电接触的连接件2001。在一些实施例中，可以使用CMP工艺、蚀刻工艺、研磨、它们的组合等来减薄工件1600的背侧1600b。在一些实施例中，连接件2001可以类似于连接件801，可以使用与上面参考图8描述的类似材料和方法形成连接件2001，并且这里不再重复描述。
进一步参考图20，在形成连接件2001之后，对IC管芯1701、伪管芯1501和密封剂1905实施进一步的平坦化工艺，以暴露设置在伪管芯1501的开口109(参见图12A和图12B)中的绝缘材料201。在一些实施例中，在平坦化工艺之后，伪管芯1501的背侧表面1501b与密封剂1905的最上表面和IC管芯1701的最上表面大致齐平。在一些实施例中，平坦化工艺可包括CMP工艺、蚀刻工艺、研磨、它们的组合等。在一些实施例中，设置在伪管芯1501的开口109(参见图12A和12B)中的绝缘材料201保护工件1600在平坦化工艺期间免于受到污染。在工件1600是晶圆的一些实施例中，可以实施分割工艺2003以将堆叠结构1700分离成单个堆叠结构2000。分割工艺2003可以包括锯切、蚀刻、激光烧蚀、它们的组合等。
参考图21，使用连接件2001将堆叠结构2000机械地附接且电附接至工件2101。在连接件2001由焊料材料形成的一些实施例中，可以实施回流工艺以将堆叠结构2000接合至工件2101。在一些实施例中，工件2101可包括封装衬底、印刷电路板(PCB)、陶瓷衬底等。在一些实施例中，工件2101可以包括位于工件2101中和/或上的互连件(诸如导线和通孔)。在一些实施例中，在工件2101的与堆叠结构2000相对的一侧上形成连接件2103。在一些实施例中，连接件2103可以类似于连接件903，可以使用与上面参考图9描述的类似材料和方法形成连接件2103，这里不再重复描述。在一些实施例中，在连接件2001周围形成底部填充层2107。在一些实施例中，可以使用与上面参考图5描述的填充层513类似的材料和方法来形成底部填充层2107，这里不再重复描述。在一些实施例中，环形结构2105可以在与堆叠结构2000相同的一侧上附接至工件2101，从而使得在环形结构2105的开口内设置堆叠结构2000。在一些实施例中，环形结构2105可以防止工件2101和附接的堆叠结构2000的翘曲。在一些实施例中，环形结构2105可包括绝缘材料、不锈钢、黄铜、铜、它们的组合等。在其他实施例中，可以省略环形结构2105。
进一步参考图22，在将堆叠结构2000附接至工件2101之后，从伪管芯1501的开口109(参见图12A和图12B)去除绝缘材料201(参见图21)。在一些实施例中，使用激光钻孔工艺2201去除绝缘材料201。在其他实施例中，例如，可以使用诸如蚀刻工艺的其他合适的去除工艺来去除绝缘材料201。在去除绝缘材料201之后，将伪管芯1501分成内部区2203和环形区2205。在一些实施例中，插塞1607可在去除绝缘材料201期间用作停止层。
参考图23，去除伪管芯1501的内部区2203(参见图22)以暴露位于伪管芯1501的环形区2205中的开口2301。在一些实施例中，使用拾取和放置装置去除伪管芯1501的内部区2203。在其他实施例中，可以手动地或使用其他合适的去除方法去除伪管芯1501的内部区2203。在一些实施例中，导电层301可以通过充当绝缘材料201和工件1600之间的缓冲并且通过防止绝缘材料201和工件1600之间的接合来辅助内部区2203的去除工艺。在一些实施例中，开口2301暴露工件1600的顶面。在一些实施例中，开口2301的宽度W4介于约1mm和约30mm之间。在其他实施例中，宽度W4可以大于约30mm。
参考图24，在开口2301中放置功能组件2401。在一些实施例中，功能组件2401可以是与IC管芯1701类似的IC管芯。在这种实施例中，可以使用连接件2403将功能组件2401机械地连接且电连接至工件1600。在一些实施例中，可使用与上面参考图5描述的连接件511类似的材料和方法形成连接件2403，并且这里不重复描述。在其他实施例中，可以使用直接接合方法(诸如混合接合方法等)将功能组件2401机械地连接且电连接至工件1600。在其中所得到的封装件用于光子学应用的一些实施例中，功能组件2401可包括光子纤维模块、LaMP、耦合器等。在这种实施例中，功能组件2401可以仅机械地附接至工件1600。
图25示出根据一些实施例的集成电路封装件2500的截面图。在一些实施例中，可以使用与上面参考图1A、图1B和图2至图11描述的方法类似的方法形成IC封装件2500，并且这里不再重复描述。IC封装件2500包括工件2501。在一些实施例中，工件2501可以类似于上面参考图9描述的工件901，并且这里不再重复描述。在工件2501的底面上形成连接件2503。在一些实施例中，连接件2503可以类似于上面参考图9描述的连接件903，并且这里不再重复描述。表面安装器件(SMD)附接至工件的顶面和/或底面。使用连接件2507将工件2509附接至工件2501。在一些实施例中，工件2509可以类似于上面参考图5描述的工件501，并且这里不再重复描述。在一些实施例中，连接件2507可以类似于上面参考图8描述的连接件801，并且这里不再重复描述。在连接件2507周围形成底部填充层2515。在一些实施例中，底部填充层2515类似于上面参考图9描述的底部填充层905，这里不再重复描述。使用连接件2511将IC管芯2519、2521和2523附接至工件2509，并且在连接件2511周围形成底部填充层2513。在一些实施例中，IC管芯2519、2521和2523类似于上面参考图5描述的IC管芯507和509，并且这里不再重复描述。在一些实施例中，连接件2511可以类似于上面参考图5描述的连接件511，并且这里不再重复描述。在一些实施例中，底部填充层2513类似于上面参考图5描述的底部填充层513，并且这里不再重复描述。IC管芯2519和2523的最上表面位于IC管芯2521的最上表面之上。用粘合剂2527将环形结构2525附接至IC管芯2521。在一些实施例中，可以使用与上面参考图1A、图1B和图2至图11描述的方法类似的方法形成环形结构2525，并且这里不再重复描述。在IC管芯2519、2521和2523以及环形结构2525周围形成密封剂2517，从而使得环形结构2525的开口2529没有密封剂2517。在一些实施例中，密封剂2517可以类似于上面参考图7描述的密封701，并且这里不再重复描述。IC管芯2519和2523的最上表面，以及环形结构2525的最上表面与密封剂2517的最上表面大致齐平或共面。
图26示出根据一些实施例的集成电路封装件2600的截面图。在一些实施例中，可以使用与上面参考图1A、图1B和图2至图11描述的方法类似的方法形成IC封装件2600，并且这里不再重复描述。为了突出IC封装件2600和IC封装件2500(参见图25)之间的差异，用相同的参考标号标记这些封装件的共同部件，并且这里不再重复它们的描述。IC封装件2600类似于IC封装件2500(参见图25)，区别在于IC封装件2600包括IC管芯2601、2603和2605，从而使得IC管芯2601的最上表面与IC管芯2603的最上表面、IC管芯2605的最上表面和密封剂2517的最上表面大致齐平或共面。此外，IC管芯2601和2605分别包括封装在密封剂2607和2609中的相应管芯堆叠件。在一些实施例中，IC管芯2601和2605的管芯堆叠件包括彼此接合的多个管芯。在一些实施例中，可以使用直接接合方法(诸如混合接合方法等)将多个管芯彼此接合。在其他实施例中，可以使用连接件将多个管芯彼此接合。在所示实施例中，使用粘合剂2613将环形结构2611附接至IC管芯2601和2605，从而使得环形结构2611的开口2615暴露IC管芯2603的最上表面。在一些实施例中，可以使用与上面参考图1A、图1B和图2至图11描述的方法类似的方法形成环形结构2611，并且这里不再重复描述。
图27示出根据一些实施例的集成电路封装件2700的截面图。在一些实施例中，可以使用与上面参考图12A、图12B、图13至图15、图16A、图16B和图17至图24描述的方法类似的方法形成IC封装件2700，并且这里不再重复描述。为了突出IC封装件2700和IC封装件2500(参见图25)之间的差异，用相同的参考标号标记这些封装件的共同部件，并且这里不再重复它们的描述。IC封装件2700类似于IC封装件2500(参见图25)，区别在于IC封装件2700包括IC管芯2701和2703以及环形结构2705，从而使得IC管芯2701的最上表面与IC管芯2703的最上表面、环形结构2705的最上表面和密封剂2517的最上表面大致齐平或共面。在所示实施例中，使用粘合剂2707将环形结构2705附接至工件2509，从而使得环形结构2705的开口2709暴露IC管芯2509的最上表面。在一些实施例中，可以使用与上面参考图12A、图12B、图13至图15、图16A、图16B和图17至图24描述的方法类似的方法形成环形结构2705，并且这里不再重复描述。
图28示出根据一些实施例的集成电路封装件2800的截面图。在一些实施例中，可以通过将功能组件2801放置在IC封装件2700的环形结构2705的开口2709(参见图27)中并使用连接件2803将功能组件2801接合至工件2509来形成IC封装件2800。后续地，在连接件2803周围形成底部填充层2805。在一些实施例中，底部填充层2805类似于上面参考图5描述的底部填充层513，这里不再重复描述。在一些实施例中，功能组件2801可以类似于上面参考图24描述的功能组件2401，这里不再重复描述。在所示实施例中，功能组件2801的最上表面位于环形结构2705的最上表面之上。在其他实施例中，功能部件2801的最上表面可以位于环形结构2705的最上表面下面。
图29示出根据一些实施例的集成电路封装件2900的截面图。在一些实施例中，可以使用与上面参考图12A、图12B、图13至图15、图16A、图16B和图17至图24描述的方法类似的方法形成IC封装件2900，并且这里不再重复描述。为了突出IC封装件2900和IC封装件270(参见图27)之间的差异，用相同的参考标号标记这些封装件的共同部件，并且这里不再重复它们的描述。IC封装件2900类似于IC封装件2700(参见图27)，区别在于插塞2901保持在开口2709中。在一些实施例中，可使用与上面参考图16A和图16B描述的插塞1607类似的材料和方法形成插塞2901，这里不再重复描述。
图30示出根据一些实施例的集成电路封装件3000的截面图。在一些实施例中，可以使用与上面参考图12A、图12B、图13至图15、图16A、图16B和图17至图24描述的方法类似的方法形成IC封装件3000，这里不再重复描述。为了突出IC封装件3000和IC封装件2700(参见图27)之间的差异，用相同的参考标号标记这些封装件的共同部件，并且这里不再重复它们的描述。IC封装件3000类似于IC封装件2700(参见图27)，区别在于完全去除伪管芯(诸如，例如，分别在图4和图15中示出的伪管芯401和1501)。在一些实施例中，可以使用任何合适的去除工艺来去除伪管芯以形成开口3001。开口3001暴露工件2509的顶面。
图31示出根据一些实施例的集成电路封装件3100的截面图。在一些实施例中，可以使用与上面参考图12A、图12B、图13至图15、图16A、图16B和图17至图24描述的方法类似的方法形成IC封装件3100，并且这里不再重复描述。为了突出IC封装件3100和IC封装件3000(参见图30)之间的差异，用相同的参考标号标记这些封装件的共同部件，并且这里不再重复它们的描述。IC封装件3100类似于IC封装件3000(参见图30)，区别在于除了完全去除伪管芯(诸如，例如，分别在图4和图15中示出的伪管芯401和1501)之外，还去除底部填充层2513和密封剂2517的围绕伪管芯的部分。在一些实施例中，可以使用任何合适的去除工艺来去除伪管芯和底部填充层2513和密封剂2517的部分，以形成开口3101。开口3101暴露工件2509的顶面。
图32是根据一些实施例示出的形成伪管芯的方法3200的流程图。从步骤3201开始方法3200，如上参考图1A和图1B所述，其中，图案化衬底(诸如，例如，图1A和图1B中所示的衬底105)以在衬底中形成开口(诸如，例如，图1A和图1B中所示的开口109)。在步骤3203中，如上参考图2所述，在开口中沉积绝缘材料(诸如，例如，图2中所示的绝缘材料201)。在步骤3205中，如上参考图3所述，在衬底上方沉积导电材料(诸如，例如，图3中所示的导电层301)。在步骤3207中，如上参考图4所述，将衬底分割成单个伪管芯(诸如，例如，图4中所示的伪管芯401)。
图33是根据一些实施例示出的形成集成电路封装件的方法3300的流程图。从步骤3301开始方法3300，如上参考图5所述，其中，集成电路管芯(诸如，例如，图5中所示的IC管芯507)附接至衬底(诸如，例如，图5中所示的工件501)。在步骤3303中，如上参考图6所述，将伪管芯(诸如，例如，图6中所示的伪管芯401)附接至集成电路管芯。在步骤3305中，如上参考图7所述，将集成电路管芯和伪管芯密封在密封剂(诸如，例如，图6中所示的密封剂701)中。在步骤3307中，如上参考图8至图10所述，去除伪管芯的内部区(诸如，例如，图10中所示的内部区909)，从而使得伪管芯的剩余部分形成环形结构(诸如，例如，图10中所示的环形区911)。
图34是根据一些实施例示出的形成集成电路封装件的方法3400的流程图。从步骤3401开始方法3400，如上参考图17所述，其中，集成电路管芯(诸如，例如，图17中所示的IC管芯1701)附接至衬底(诸如，例如，图17中所示的工件1600)。在步骤3403中，如上参考图18所述，将伪管芯(诸如，例如，图18中所示的伪管芯1501)附接至衬底。在步骤3405中，如上参考图19所述，将集成电路管芯和伪管芯密封在密封剂(诸如，例如，图19中所示的密封剂1905)中。在步骤3407中，如上参考图20至图23所述，去除伪管芯的内部区(诸如，例如，图23中所示的内部区2203)，从而使得伪管芯的剩余部分形成环形结构(诸如，例如，图23中所示的环形区2205)。
根据实施例，一种方法包括：将集成电路管芯附接至第一衬底；形成伪管芯；将伪管芯附接至第一衬底且与集成电路管芯相邻；在第一衬底上方且在伪管芯和集成电路管芯周围形成密封剂；平坦化密封剂、伪管芯和集成电路管芯，密封剂的最上表面与伪管芯的最上表面和集成电路管芯的最上表面大致齐平；以及去除伪管芯的内部部分，伪管芯的剩余部分形成环形结构。在实施例中，形成伪管芯包括：图案化第二衬底以在第二衬底中形成开口，该开口在平面图中具有环形形状；以及在开口中沉积绝缘材料。在实施例中，平坦化密封剂、伪管芯和集成电路管芯包括暴露绝缘材料。在实施例中，去除伪管芯的内部部分包括：去除绝缘材料，其中，在去除绝缘材料之后，将伪管芯分离成内部区和外围区；以及从第一衬底拾取内部区，外围区形成环形结构。在实施例中，去除绝缘材料包括使用激光钻孔方法去除绝缘材料。在实施例中，使用粘合剂将伪管芯附接至第一衬底。在实施例中，该方法还包括：将功能组件放置在环形结构内；以及将功能组件接合至第一衬底，其中，功能组件和环形结构具有不同的高度。
根据另一实施例，一种方法包括：将集成电路管芯附接至第一衬底的第一侧；形成伪管芯，伪管芯包括位于伪管芯内的第一环形结构；将伪管芯附接至第一衬底的第一侧且与集成电路管芯相邻；在第一衬底上方且在伪管芯和集成电路管芯周围形成模塑料，模塑料的顶面与伪管芯的最上表面、第一环形结构的最上表面和集成电路管芯的最上表面大致齐平；去除第一环形结构，在去除第一环形结构之后，将伪管芯分离成内部区和外围环形区；将伪管芯的内部区与第一衬底脱粘，伪管芯的外围环形区形成第二环形结构；将功能组件放置在第二环形结构内的第一衬底的第一侧上；以及将功能组件附接至第一衬底的第一侧。在实施例中，形成伪管芯包括：图案化第二衬底以在第二衬底中形成开口，该开口在平面图中具有环形形状；以及在开口中沉积绝缘材料以形成第一环形结构。在实施例中，去除第一环形结构包括实施激光钻孔工艺。在实施例中，使用粘合剂将伪管芯附接至第一衬底的第一侧。在实施例中，功能组件和第二环形结构具有不同的高度。在实施例中，该方法还包括在第一衬底的第二侧上形成多个连接件，第一衬底的第二侧与第一衬底的第一侧相对。在实施例中，第一衬底包括中介片。
根据又一实施例，一种封装件包括：衬底；第一集成电路管芯，接合至衬底的第一侧；环形结构，接合至衬底的第一侧且与第一集成电路管芯相邻；密封剂，位于衬底上方且位于环形结构和第一集成电路管芯周围，密封剂的最上表面与环形结构的最上表面和第一集成电路管芯的最上表面齐平；以及功能组件，位于环形结构内并且接合至衬底的第一侧。在实施例中，封装件还包括插接在衬底的第一侧和环形结构之间的粘合剂。在实施例中，封装件还包括位于衬底的第二侧上的多个连接件，衬底的第二侧与衬底的第一侧相对。在实施例中，衬底包括中介片。在实施例中，功能组件包括第二集成电路管芯。在实施例中，功能组件和环形结构具有不同的高度。
也可以包括其他部件和工艺。例如，可以包括测试结构以辅助3D封装件或3DIC器件的验证测试。测试结构可以包括例如形成在再分布层中或衬底上测试焊盘以允许使用探针和/或探针卡等测试3D封装件或3DIC。可以对中间结构以及最终结构实施验证测试。额外地，本文公开的结构和方法可以与测试方法结合使用，其中，该测试方法结合了已知良好管芯的中间验证以增加产量并降低成本。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的各个方面。本领域技术人员应当理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，在此他们可以做出多种变化、替换以及改变。

Claims (20)

1.一种形成集成电路封装件的方法，包括：
将集成电路管芯附接至第一衬底；
形成伪管芯，所述伪管芯内具有第一环形结构和位于所述第一环形结构所限定区域内的内部部分；
将所述伪管芯附接至所述第一衬底，所述伪管芯与所述集成电路管芯相邻；
在所述第一衬底上方并且在所述伪管芯和所述集成电路管芯周围形成密封剂；
平坦化所述密封剂、所述伪管芯和所述集成电路管芯，所述密封剂的最上表面与所述伪管芯的最上表面、所述第一环形结构的最上表面和所述集成电路管芯的最上表面齐平；以及，
去除所述第一环形结构，在去除所述第一环形结构之后，去除所述伪管芯的所述内部部分，所述伪管芯的剩余部分形成第二环形结构。
2.根据权利要求1所述的方法，其中，形成所述伪管芯包括：
图案化第二衬底以在所述第二衬底中形成开口，所述开口在平面图中具有环形形状；以及
在所述开口中沉积绝缘材料。
3.根据权利要求2所述的方法，其中，平坦化所述密封剂、所述伪管芯和所述集成电路管芯包括暴露所述绝缘材料。
4.根据权利要求2所述的方法，其中，去除所述伪管芯的内部部分包括：
去除所述绝缘材料，其中，在去除所述绝缘材料之后，将所述伪管芯分离成内部区和外围区；以及
从所述第一衬底拾取所述内部区，所述外围区形成所述第二环形结构。
5.根据权利要求4所述的方法，其中，去除所述绝缘材料包括使用激光钻孔方法去除所述绝缘材料。
6.根据权利要求1所述的方法，其中，使用粘合剂将所述伪管芯附接至所述第一衬底。
7.根据权利要求1所述的方法，还包括：
将功能组件放置在所述第二环形结构内；以及
将所述功能组件接合至所述第一衬底，其中，所述功能组件和所述第二环形结构具有不同的高度。
8.一种形成集成电路封装件的方法，包括：
将集成电路管芯附接至第一衬底的第一侧；
形成伪管芯，所述伪管芯包括位于所述伪管芯内的第一环形结构；
将所述伪管芯附接至所述第一衬底的第一侧，所述伪管芯与所述集成电路管芯相邻；
在所述第一衬底上方并且在所述伪管芯和所述集成电路管芯周围形成模塑料，所述模塑料的顶面与所述伪管芯的最上表面、所述第一环形结构的最上表面和所述集成电路管芯的最上表面齐平；
去除所述第一环形结构，在去除所述第一环形结构之后，所述伪管芯分离成内部区和外围环形区；
使所述伪管芯的内部区与所述第一衬底脱离，所述伪管芯的外围环形区形成第二环形结构；
将功能组件放置在所述第二环形结构内且在所述第一衬底的第一侧上；以及
将所述功能组件附接至所述第一衬底的第一侧。
9.根据权利要求8所述的方法，其中，形成所述伪管芯包括：
图案化第二衬底以在所述第二衬底中形成开口，所述开口在平面图中具有环形形状；以及
在所述开口中沉积绝缘材料以形成所述第一环形结构。
10.根据权利要求8所述的方法，其中，去除所述第一环形结构包括实施激光钻孔工艺。
11.根据权利要求8所述的方法，其中，使用粘合剂将所述伪管芯附接至所述第一衬底的第一侧。
12.根据权利要求8所述的方法，其中，所述功能组件和所述第二环形结构具有不同的高度。
13.根据权利要求8所述的方法，还包括：在所述第一衬底的第二侧上形成多个连接件，所述第一衬底的第二侧与所述第一衬底的第一侧相对。
14.根据权利要求8所述的方法，其中，所述第一衬底包括中介片。
15.一种集成电路封装件，包括：
衬底；
第一集成电路管芯，具有接合至所述衬底的第一侧的下表面和与所述下表面相对设置的最上表面；
环形结构，接合至所述第一集成电路管芯的所述最上表面；
密封剂，位于所述衬底上方并且位于所述环形结构和所述第一集成电路管芯周围，所述密封剂的最上表面与所述环形结构的最上表面齐平；以及
功能组件，位于所述环形结构内并且接合至所述第一集成电路管芯的所述最上表面。
16.根据权利要求15所述的集成电路封装件，其中，所述功能组件的高度大于所述环形结构的高度。
17.根据权利要求15所述的集成电路封装件，还包括：多个连接件，位于所述衬底的第二侧上，所述衬底的第二侧与所述衬底的第一侧相对。
18.根据权利要求15所述的集成电路封装件，其中，所述衬底包括中介片。
19.根据权利要求15所述的集成电路封装件，其中，所述功能组件包括第二集成电路管芯。
20.根据权利要求15所述的集成电路封装件，其中，所述功能组件和所述环形结构具有不同的高度。
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