TWI673848B - 積體電路封裝及其形成方法 - Google Patents

積體電路封裝及其形成方法 Download PDF

Info

Publication number
TWI673848B
TWI673848B TW106143045A TW106143045A TWI673848B TW I673848 B TWI673848 B TW I673848B TW 106143045 A TW106143045 A TW 106143045A TW 106143045 A TW106143045 A TW 106143045A TW I673848 B TWI673848 B TW I673848B
Authority
TW
Taiwan
Prior art keywords
integrated circuit
encapsulation body
forming
conductive pillar
polymer material
Prior art date
Application number
TW106143045A
Other languages
English (en)
Other versions
TW201906121A (zh
Inventor
林俊成
鄭禮輝
蔡柏豪
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW201906121A publication Critical patent/TW201906121A/zh
Application granted granted Critical
Publication of TWI673848B publication Critical patent/TWI673848B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H01L2221/68331—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding of passive members, e.g. die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026—Bonding areas specifically adapted for layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

Abstract

本發明提供一種積體電路封裝及其形成方法。一種積體電路封裝的形成方法包括在載體之上形成導電柱。將積體電路晶粒接著至所述載體，所述積體電路晶粒鄰近所述導電柱設置。在所述導電柱及所述積體電路晶粒周圍形成包封體。移除所述載體以暴露出所述導電柱的第一表面及所述包封體的第二表面。在所述第一表面及所述第二表面之上形成聚合物材料。將所述聚合物材料固化以形成環形結構。在平面圖中所述環形結構的內邊緣與所述第一表面交疊。在所述平面圖中所述環形結構的外邊緣與所述第二表面交疊。

Description

積體電路封裝及其形成方法
本發明實施例有關於一種積體電路封裝及其形成方法。
半導體元件被用於各種電子應用中，例如個人電腦、手機、數位相機以及其他電子設備。半導體元件通常是藉由以下步驟來製作：於半導體基板之上依序沈積絕緣層或介電層、導電層、以及半導體材料層；以及利用微影來對所述各種材料進行圖案化，以在上面形成電路組件(circuit components)及電路部件(elements)。通常於單個半導體晶圓上製造數十或數以百計的積體電路(integrated circuit)。藉由沿切割道(scribe line)對所述積體電路進行鋸切來使個別晶粒單體化。接著將所述個別晶粒單獨地封裝於多晶片模組中或其他類型的封裝形式中。
由於各種電子組件(例如，電晶體、二極體、電阻器、電容器等)的積體密度持續地提高，因此半導體產業經歷了快速成長。在很大程度上，積體密度的此種提高是源自最小特徵大小(minimum feature size)的連番減小(例如，朝次20nm節點(sub- 20nm node)縮減半導體製程節點)，此使得更多的組件能夠整合於給定區域中。隨著近來對小型化、提高速度、及增大頻寬、以及降低功耗及減少延遲的需求增加，對半導體晶粒的更小且更具創造性的封裝技術的需求已相對地增加。
隨著半導體技術更加進步，堆疊半導體元件(stacked semiconductor device)(例如，三維積體電路(three dimensional integrated circuit，3DIC))已成為一種有效的替代方案來進一步減小半導體元件的實體大小。在堆疊半導體元件中，在不同的半導體晶圓上製作主動電路，例如邏輯電路、記憶體電路、處理器電路等。可將兩個或更多個半導體晶圓安裝或堆疊於彼此頂上，以進一步降低半導體元件的形狀因數(form factor)。疊層封裝(package-on-package，POP)元件為其中先對晶粒進行封裝、接著將所述晶粒與另一個或另一些經封裝晶粒封裝於一起的一種類型的三維積體電路。封裝上晶片(chip-on-package，COP)元件為其中先對晶粒進行封裝、接著將所述晶粒與另一個或另一些晶粒封裝於一起的另一種類型的三維積體電路。
本發明一些實施例的積體電路封裝的形成方法包括：在載體之上形成導電柱；將積體電路晶粒接著至所述載體，所述積體電路晶粒鄰近所述導電柱設置；在所述導電柱及所述積體電路晶粒周圍形成包封體；移除所述載體，以暴露出所述導電柱的第一表 面及所述包封體的第二表面；在所述第一表面及所述第二表面之上形成聚合物材料；以及將所述聚合物材料固化以形成環形結構，其中在平面圖中所述環形結構的內邊緣與所述第一表面交疊，且其中在所述平面圖中所述環形結構的外邊緣與所述第二表面交疊。
本發明另一些實施例的積體電路封裝的形成方法包括：在載體之上形成導電柱；將積體電路晶粒接著至所述載體，所述積體電路晶粒鄰近所述導電柱設置；在所述載體之上及所述導電柱周圍形成聚合物材料；將所述聚合物材料固化以形成環形結構；以及在所述環形結構之上以及所述導電柱及所述積體電路晶粒周圍形成包封體。
本發明實施例的積體電路封裝包括：積體電路晶粒；包封體，沿所述積體電路晶粒的側壁延伸，所述包封體具有第一表面及與所述第一表面相對的第二表面；導電柱，在所述第一表面與所述第二表面之間延伸穿過所述包封體；以及環形結構，設置於所述包封體的所述第一表面處，在平面圖中，所述環形結構環繞所述導電柱。
100、1901‧‧‧工件
101‧‧‧晶粒區
103‧‧‧切割道
105‧‧‧基板
107‧‧‧主動及/或被動元件
109‧‧‧金屬層
111‧‧‧接觸接墊
113‧‧‧鈍化層
115、203、403、909‧‧‧開口
201‧‧‧緩衝層
301、905‧‧‧晶種層
401、907‧‧‧圖案化罩幕
501、1001‧‧‧導電樁
503‧‧‧焊料層
701‧‧‧保護層
703、1609‧‧‧膠帶
801‧‧‧積體電路晶粒
803、1611‧‧‧框架
805‧‧‧黏合劑
901‧‧‧載體
903‧‧‧離形層
1003‧‧‧導通孔
1201‧‧‧黏合層
1301‧‧‧包封體
1501‧‧‧重佈線結構
15031、15032、15033‧‧‧絕緣層
15051、15052‧‧‧重佈線層
1507‧‧‧凸塊下金屬
1509、1903‧‧‧連接件
1601‧‧‧分配設備
1603‧‧‧聚合物材料
1605‧‧‧箭頭
1607、2101‧‧‧環形結構
1613‧‧‧表面
1801A、1801B、2400、2601‧‧‧積體電路封裝
1900、2000、2500、2600‧‧‧堆疊半導體元件
1905‧‧‧底部填充材料
1907、2001、2501‧‧‧區
2700、2800‧‧‧方法
2701、2703、2705、2707、2709、2711、2801、2803、2805、2807、2809‧‧‧步驟
H1、H2、H3、H4、H5‧‧‧高度
W1‧‧‧寬度
W2‧‧‧內徑
W3、W5‧‧‧外徑
W4‧‧‧寬度/內徑
α1、α2‧‧‧角度
結合附圖閱讀以下詳細說明，會最佳地理解本發明的各個態樣。應注意，根據本行業中的標準慣例，各種特徵並非按比例繪製。事實上，為論述清晰起見，可任意增大或減小各種特徵的尺寸。
圖1至圖8是根據一些實施例的製作積體電路晶粒期間的各個處理步驟的剖視圖。
圖9至圖15、圖16A、圖16B、圖17、圖18A、圖18B、圖19A、圖19B、圖20A、及圖20B是根據一些實施例的製作積體電路封裝期間的各個處理步驟的剖視圖。
圖21至圖24、圖25A、圖25B、及圖26是根據一些實施例的製作積體電路封裝期間的各個處理步驟的剖視圖。
圖27是說明根據一些實施例的一種形成積體電路封裝的方法的流程圖。
圖28是說明根據一些實施例的一種形成積體電路封裝的方法的流程圖。
以下揭露內容提供用於實作本發明的不同特徵的諸多不同的實施例或實例。以下闡述組件及配置的具體實例以簡化本揭露內容。當然，該些僅為實例且不旨在進行限制。舉例而言，以下說明中將第一特徵形成於第二特徵「之上」或第二特徵「上」可包括其中第一特徵與第二特徵被形成為直接接觸的實施例，且亦可包括其中第一特徵與第二特徵之間可形成有附加特徵、進而使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。另外，本揭露內容可能在各個實例中重複使用參考編號及/或字母。此種重複使用是出於簡潔及清晰的目的，但自身並不表示所論述的各種 實施例及/或配置之間的關係。
此外，為易於說明，本文中可能使用例如「位於…之下(beneath)」、「位於...下面(below)」、「下部的(lower)」、「位於...上方(above)」、「上部的(upper)」等空間相對性用語來闡述圖中所示一個部件或特徵與另一(其他)部件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的定向外亦囊括元件在使用或操作中的不同定向。裝置可具有其他定向(旋轉90度或處於其他定向)，且本文中所用的空間相對性描述語可同樣相應地進行解釋。
將參照特定領域中(即，例如積體扇出型(integrated fan-out，InFO)封裝等積體電路封裝以及包括積體扇出型封裝的疊層封裝)的實施例來闡述本發明的實施例。然而，亦可對其他電性連接的組件應用其他實施例，所述實施例包括但不限於：疊層封裝組裝(package-on-package assemblies)、晶粒對晶粒組裝(die-to-die assemblies)、晶圓對晶圓組裝(wafer-to-wafer assmblies)、晶粒對基板組裝、對封裝進行組裝、對基板、中介層(interposer)等進行處理、對輸入組件、板、晶粒或其他組件進行安裝、或者用於連接封裝、或對任意類型的積體電路或電性電路的組合進行安裝。
本文所述各種實施例使得能夠在延伸穿過積體扇出型封裝的包封體(例如(舉例而言)，模塑化合物)的通孔周圍形成保護環。在一些實施例中，保護環使得能夠改善接著至通孔的連接件(例如，(舉例而言)，焊料凸塊)的輪廓。在一些實施例中，所述保護環使得能夠在執行積體電路封裝的可靠性測試的同時及/或在 積體電路封裝的正常運作期間防止或消除包封體自通孔分層、底部填充膠(underfill)自連接件分層、包封體及/或底部填充膠中形成裂紋、包封體與底部填充膠之間的裂紋的擴展、以及在由通孔以及對應的連接件形成的接合體中形成裂紋。本文所述各種實施例更使得能夠減少製造步驟的數目並減低用於形成積體電路封裝的製造成本。
圖1至圖8是根據一些實施例的製作積體電路晶粒期間的各個處理步驟的剖視圖。參照圖1，圖1示出具有藉由切割道103(也被稱為劃切道(dicing line)或劃切區(dicing street))而隔開的晶粒區101的工件100的一部分。如以下更詳細地闡述，將沿切割道103來對工件100進行劃切以形成個別的積體電路晶粒(例如，圖8所示積體電路晶粒801)。在一些實施例中，工件100包括基板105、位於基板105上的一或多個主動及/或被動元件107、以及位於基板105之上的一或多個金屬層109。
在一些實施例中，基板105可由矽形成，但是基板105亦可由其他III族、IV族、及/或V族元素(例如，矽、鍺、鎵、砷、及其組合)形成。基板105亦可為絕緣體上覆矽(silicon-on-insulator，SOI)的形式。絕緣體上覆矽基板可包括形成於絕緣體層(例如，隱埋氧化物及/或類似物質)之上的半導體材料層(例如，矽、鍺、及/或類似材料)，所述絕緣體層形成於矽基板上。另外，可使用的其他基板，包括多層式基板、梯度基板(gradient substrate)、混合定向基板(hybrid oreientation substrate)、其任意 組合等等及/或類似者。在一些實施例中，所述一或多個主動及/或被動元件107可包括例如是電晶體的各種n型金屬氧化物半導體(n-type metal-oxide semiconductor，NMOS)元件及/或p型金屬氧化物半導體(p-type metal-oxide semiconductor，PMOS)元件、電容器、電阻器、二極體、光二極體(photo-diode)、熔絲(fuse)及/或類似元件。
所述一或多個金屬層109可包括形成於基板105之上的層間介電層(inter-layer dielectric，ILD)/金屬層間介電層(inter-metal dielectric，IMD)。層間介電層/金屬層間介電層可例如由低介電常數(low-K)介電材料(例如，磷矽酸鹽玻璃(phosphosilicate glass，PSG)、硼磷矽酸鹽玻璃(borophosphosilicate glass，BPSG)、氟矽酸鹽玻璃(fluorinated silicate glass，FSG)、SiOxCy、旋塗玻璃(Spin-On-Glass)、旋塗聚合物(Spin-On-Polymer)、矽碳材料、其化合物、其複合材料、其組合等)藉由此項技術中習知的任意適合的方法(例如，旋轉塗佈方法(spin-on coating method)、化學氣相沈積(chemical vapor deposition，CVD)、電漿增強型化學氣相沈積(plasma enhanced chemical vapor deposition，PECVD)、其組合、或類似方法)來形成。在一些實施例中，可使用例如鑲嵌製程、雙鑲嵌製程、或類似製程在層間介電層/金屬層間介電層中形成內連線結構(圖中未示出)。在一些實施例中，內連線結構可包含銅、銅合金、銀、金、鎢、鉭、鋁等。在一些實施例中，內連線結構可在形成於基板105上的一或多個主動及/或被動元件107之 間提供電性連接。
在一些實施例中，在所述一或多個金屬層109之上形成接觸接墊111。接觸接墊111可經由所述一或多個金屬層109電性耦合至所述一個或多個主動及/或被動元件107。在一些實施例中，接觸接墊111可包含導電材料，例如鋁、銅、鎢、銀、金、其組合等。在一些實施例中，可使用例如以下方法在所述一或多個金屬層109之上形成導電材料：物理氣相沈積(physical vapor deposition，PVD)、原子層沈積(atomic layer deposition，ALD)、電化學鍍覆(electro-chemical plating)、無電鍍覆、其組合等。接著，將導電材料圖案化以形成接觸接墊111。在一些實施例中，可使用適合的微影及蝕刻技術將導電材料圖案化。一般而言，微影技術涉及沈積光阻材料(圖中未示出)，緊接著對光阻材料進行照射(曝光)及顯影以移除光阻材料的一部分。剩餘的光阻材料保護下伏的材料(例如，接觸接墊111的導電材料)不受後續處理步驟(例如，蝕刻)的影響。可對導電材料應用適合的蝕刻製程(例如，反應性離子蝕刻(reactive ion etch，RIE)或其他乾蝕刻、各向同性或各向異性濕蝕刻、或任意其他適合的蝕刻或圖案化製程)以移除導電材料的暴露部分並形成接觸接墊111。緊接著，可使用例如灰化製程以及之後的濕清潔製程來移除光阻材料。
進一步參照圖1，在基板105及接觸接墊111之上形成鈍化層(passivation layer)113。在一些實施例中，鈍化層113可包含例如氮化矽、氧化矽、磷矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃 (borosilicate glass，BSG)、摻雜硼的磷矽酸鹽玻璃(boron-doped phosphosilicate glass，BPSG)、其組合等非光可圖案化(non-photo-patternable)的介電材料的一或多層，且可使用化學氣相沈積(CVD)、物理氣相沈積、原子層沈積、旋轉塗佈製程、其組合、或類似方法形成。在其他實施例中，鈍化層113可包含例如聚苯並噁唑(polybenzoxazole，PBO)、聚醯亞胺(polyimide，PI)、苯並環丁烯(benzocyclobutene，BCB)等光可圖案化(photo-patternable)的絕緣材料的一或多層，且可使用旋轉塗佈製程等來形成。可使用與光阻材料相似的微影方法將此種光可圖案化的介電材料圖案化。
在一些實施例中，在鈍化層113中形成開口115以暴露出接觸接墊111的部分。在其中鈍化層113包含非光可圖案化介電材料的一些實施例中，可使用適合的微影及蝕刻方法將鈍化層113圖案化。在一些實施例中，在鈍化層113之上形成光阻材料(圖中未示出)。接著對光阻材料進行照射(曝光)及顯影以移除光阻材料的一部分。緊接著，使用例如適合的蝕刻製程來移除鈍化層113的暴露部分以形成開口115。
參照圖2，在鈍化層113及接觸接墊111之上形成緩衝層201。在一些實施例中，緩衝層201可包含例如聚苯並噁唑(PBO)、聚醯亞胺(PI)、苯並環丁烯(BCB)、其組合等光可圖案化絕緣材料的一或多層，且可使用旋轉塗佈製程等形成。在一些實施例中，對緩衝層201進行圖案化以形成開口203且暴露出接觸接墊111。 在一些實施例中，可使用適合的微影技術將緩衝層201暴露至光，以形成開口203。在曝光之後對緩衝層201進行顯影及/或固化。
參照圖3，在緩衝層201及開口203之上毯覆沈積晶種層301。晶種層301可包含銅、鈦、鎳、金、錳、其組合等的一或多層，且可藉由原子層沈積、物理氣相沈積、濺鍍、其組合、或類似方法形成。在一些實施例中，晶種層301包含鈦層以及形成於鈦層之上的銅層。
參照圖4，在晶種層301之上形成圖案化罩幕401。在一些實施例中，圖案化罩幕401包含光阻材料、或任意光可圖案化材料。在一些實施例中，對圖案化罩幕401的材料進行沈積、照射(曝光)及顯影以移除所述材料的部分並形成開口403，進而形成圖案化罩幕401。在所說明的實施例中，開口403暴露出晶種層301的在開口203中形成於接觸接墊111之上的部分。如以下更詳細地論述，將在開口403中形成導電樁(例如，圖5所示導電樁501)以提供與接觸接墊111的電性連接。
參照圖5，在由開口403與開口203形成的組合開口(參見圖4)中形成導電樁501。在一些實施例中，使用電化學鍍覆製程、無電鍍覆製程、原子層沈積、物理氣相沈積、其組合等利用導電材料(例如，銅、鎢、鋁、銀、金、其組合等)填充所述組合開口以形成導電樁501。在一些實施例中，導電樁501局部地填充所述組合開口且組合開口的剩餘部分被焊料材料填充以在導電樁501之上形成焊料層503。在一些實施例中，焊料材料可為：鉛系 焊料，例如PbSn組成物；無鉛焊料，包括InSb、錫、銀、及銅(錫銀銅合金(SAC))組成物；以及具有共同的熔點且在電性應用中形成導電焊料連接的其他共晶材料(eutectic material)。對於無鉛焊料而言，可使用由不同組成物形成的SAC焊料，例如(舉例而言)，SAC 105(Sn 98.5%、Ag 1.0%、Cu 0.5%)、SAC 305及SAC 405。無鉛焊料亦包括不使用銀(Ag)的SnCu化合物以及不使用銅(Cu)的SnAg化合物。在一些實施例中，焊料層503可使用蒸鍍、電化學鍍覆製程、無電鍍覆製程、印刷、焊料轉移、其組合等來形成。
參照圖6，在形成導電樁501及焊料層503之後，移除圖案化罩幕401。在一些實施例中，可使用例如灰化製程並接著進行濕清潔製程來移除包含光阻材料的圖案化罩幕401。緊接著，使用例如適合的蝕刻製程來移除晶種層301的暴露的部分。
參照圖7，形成保護層701，其中保護層701經形成在導電樁501以及對應的焊料層503之上並環繞導電樁501以及對應的焊料層503。在一些實施例中，保護層701可包含例如聚苯並噁唑(PBO)、聚醯亞胺(PI)、苯並環丁烯(BCB)、其組合等光可圖案化絕緣材料的一或多層，且可使用旋轉塗佈製程等形成。在一些實施例中，在形成保護層701之前，可對各晶粒區101中的每一者進行測試以辨識已知良好晶粒(known good dies，KGD)以進行進一步處理。
進一步參照圖7，在一些實施例中，期望對基板105進行 例如背部研磨，以減小工件100的厚度以及後續形成的積體電路晶粒的厚度。在該些實施例中，執行薄化製程，在所述薄化製程中，向保護層701的頂表面施加膠帶703(例如，背部研磨(back grinding，BG)膠帶)且藉由研磨、蝕刻、化學機械研磨(chemical mechanical polishing，CMP)製程、其組合等來將基板105的背側薄化。在一些實施例中，膠帶703保護工件100不受由研磨/蝕刻流體及/或碎片造成的污染。
參照圖8，在完成上述薄化製程之後，移除膠帶703並將工件100單體化以形成個別的積體電路晶粒801。在一些實施例中，可使用黏合劑805將工件100接著至框架803以對工件100進行製備以使其可應用於後續劃切製程。在一些實施例中，框架803可為膜框架或任意適合的載體以為後續操作(例如，劃切)提供機械支撐。黏合劑805可為晶粒接著膜、劃切膜、或任意適合的黏合劑、環氧樹脂、紫外光(ultraviolet，UV)膠(當暴露至紫外光輻射時其會失去黏合性質)等，且黏合劑805可使用沈積製程、旋轉塗佈、印刷製程、疊層製程等形成。在一些實施例中，黏合劑805可具有多層式結構且可包括離形層(圖中未示出)。離形層可有助於在完成劃切製程之後將個別的積體電路晶粒801自框架803安全地移除。在一些實施例中，離形層可為紫外光型，其中在將離形層暴露至紫外光輻射之後，離形層的黏合強度實質上降低。在其他實施例中，離形層可為熱型，其中在將離形層暴露至適合的熱源之後，離形層的黏合強度實質上降低。在一些實施例中，可例 如藉由鋸切、雷射燒蝕(laser ablation)、其組合等來將工件100單體化成個別的晶粒。
如圖8所示，每一積體電路晶粒801包括單個鈍化層(例如，鈍化層113)、單個緩衝層(例如，緩衝層201)、兩個接觸接墊(例如，接觸接墊111)、兩個導電樁(例如，導電樁501)、以及單個保護層(例如，保護層701)。熟習此項技術者應認識到，保護層、緩衝層、接觸接墊、導電樁、以及保護層的數目僅供用於說明，而非限制本發明的範圍。在其他實施例中，視對積體電路晶粒801的設計要求而定，每一積體電路晶粒801可包括適當數目的保護層、緩衝層、接觸接墊、導電樁、及保護層。
圖9至圖15、圖16A、圖16B、圖17、圖18A、圖18B、圖19A、圖19B、圖20A、及圖20B是根據一些實施例的使用在圖1至圖8中製作的積體電路晶粒來製作積體電路封裝期間的各個處理步驟的剖視圖。首先參照圖9，在一些實施例中，在載體901之上形成離形層903，並且在離形層903之上形成晶種層905以開始形成積體電路封裝。在一些實施例中，載體901可由石英、玻璃等形成，且對後續操作提供機械支撐。在一些實施例中，離形層903可包含光熱轉換(light to heat conversion，LTHC)材料、紫外光(ultraviolet，UV)黏合劑、聚合物層等，且可使用旋轉塗佈(spin-on coating)製程、印刷製程、疊層(lamination)製程等形成。在其中離形層903是由光熱轉換材料形成的一些實施例中，可容易地將在暴露至光時會局部地或完全地失去其黏合強度的離形層 903、及載體901自後續形成的結構的背側移除。在一些實施例中，可使用與以上參照圖3闡述的晶種層301相似的材料及方法形成晶種層905，且為簡潔起見在本文中將不再對其予以贅述。在一些實施例中，晶種層905可具有介於約0.005微米與1微米之間的厚度。
進一步參照圖9，在晶種層905之上形成其中具有開口909的圖案化罩幕907。在一些實施例中，可使用與以上參照圖4闡述的圖案化罩幕401相似的材料及方法形成圖案化罩幕907，且為簡潔起見在本文中將不再對其予以贅述。
參照圖10，在開口909(參見圖9)中形成導電樁1001。在一些實施例中，可使用與以上參照圖5闡述的導電樁501相似的材料及方法形成導電樁1001，且為簡潔起見在本文中將不再對其予以贅述。在一些實施例中，在形成導電樁1001之後，移除圖案化罩幕907。在一些實施例中，可使用與以上參照圖6闡述的圖案化罩幕401相似的方法移除圖案化罩幕907，且為簡潔起見在本文中將不再對其予以贅述。緊接著，移除晶種層905的暴露部分。在一些實施例中，可使用與以上參照圖6闡述的晶種層301的暴露部分相似的方法移除晶種層905的暴露部分，且為簡潔起見在本文中將不再對其予以贅述。在一些實施例中，導電樁1001與對應的晶種層905可被稱為導通孔1003。
參照圖12，使用黏合層1201來將積體電路晶粒801接著至離形層903。在一些實施例中，使用例如拾取及放置(pick-and- place)設備來將積體電路晶粒801放置於離形層903上。在其他實施例中，可用人工的方式或使用任意其他適合的方法將積體電路晶粒801放置於離形層903上。在一些實施例中，黏合層1201可包含光熱轉換材料、紫外光黏合劑、晶粒接著膜等，且可使用旋轉塗佈製程、印刷製程、疊層製程等來形成。
參照圖13，形成包封體1301，其中包封體1301晶形成在載體901之上、以及在積體電路晶粒801及導通孔1003之上並環繞積體電路晶粒801及導通孔1003。在一些實施例中，包封體1301可包含模塑化合物，例如環氧樹脂、樹脂、可模塑聚合物等。可在模塑化合物實質上為液體的情況下施加模塑化合物，且接著可藉由化學反應(例如在環氧樹脂或樹脂中)而將模塑化合物固化。在其他實施例中，模塑化合物可為作為凝膠或延展性固體(malleable solid)來施加的紫外光(UV)固化聚合物或熱固化聚合物，所述凝膠或延展性固體能夠被設置在積體電路晶粒801與導通孔1003周圍及之間。
進一步參照圖14，在一些實施例中，使用化學機械研磨製程、研磨製程、其組合等來將包封體1301平坦化。在一些實施例中，執行平坦化製程直至暴露出積體電路晶粒801的導電樁501為止。在一些實施例中，平坦化製程亦可將導電樁501之上的焊料層503(參見圖8)移除。在一些實施例中，導電樁501的頂表面與導通孔1003的頂表面及包封體1301的頂表面實質上共面。
參照圖15，在積體電路晶粒801、導通孔1003、及包封 體1301之上形成重佈線結構1501。在一些實施例中，重佈線結構1501可包括絕緣層15031至絕緣層15033、以及設置在絕緣層15031至絕緣層15033內的重佈線層(redistribution layer，RDL)15051及重佈線層15052(包括導線及導通孔)。在一些實施例中，可使用與以上參照圖2闡述的緩衝層201相似的材料及方法形成絕緣層15031至絕緣層15033，且為簡潔起見在本文中將不再對其予以贅述。在一些實施例中，可使用與以上參照圖5闡述的導電樁501相似的材料及方法形成重佈線層15051及重佈線層15052，且為簡潔起見在本文中將不再對其予以贅述。
進一步參照圖15，在一些實施例中，用於形成重佈線結構1501的製程步驟可包括使用與以上參照圖2所述的緩衝層201相似的方法將絕緣層15031圖案化以在其中形成開口，且為簡潔起見在本文中將不再對其予以贅述。重佈線層15051形成於絕緣層15031之上以及絕緣層15031中的開口中以接觸導通孔1003及導電樁501。重佈線層15051可包括各種線/跡線(「水平地」橫跨絕緣層15031的頂表面行進)及/或通孔(「垂直地」延伸至絕緣層15031中)。在一些實施例中，在絕緣層15031之上以及絕緣層15031內的開口中沈積晶種層(圖中未示出)。可使用與以上參照圖3闡述的晶種層301相似的材料及方法形成晶種層，且為簡潔起見在本文中將不再對其予以贅述。接著，在晶種層之上設置圖案化罩幕(圖中未示出)以界定重佈線層15051的期望圖案。在一些實施例中，可使用與以上參照圖4闡述的圖案化罩幕401相似的材料及 方法形成其中具有開口的圖案化罩幕，且為簡潔起見在本文中將不再對其予以贅述。在一些實施例中，藉由電化學鍍覆製程、無電鍍覆製程、原子層沈積、物理氣相沈積、濺鍍、其組合等在晶種層上形成導電材料。緊接著，移除圖案化罩幕且亦移除在移除圖案化罩幕之後暴露出的晶種層的部分。在一些實施例中，可使用與以上參照圖6闡述的圖案化罩幕401相似的方法移除圖案化罩幕，且為簡潔起見在本文中將不再對其予以贅述。在一些實施例中，可使用與以上參照圖6闡述的晶種層301的暴露部分相似的方法移除晶種層的暴露部分，且為簡潔起見在本文中將不再對其予以贅述。
進一步參照圖15，在絕緣層15031及重佈線層15051之上形成絕緣層15032、重佈線層15052、及絕緣層15033，由此完成重佈線結構1501的形成。在一些實施例中，可使用與重佈線層15051相似的方法在絕緣層15032之上形成重佈線層15052，且為簡潔起見在本文中將不再對其予以贅述。在一些實施例中，重佈線層15052延伸穿過絕緣層15032並接觸重佈線層15051的部分。
如圖15所示，重佈線結構1501包括三個絕緣層(例如絕緣層15031至絕緣層15033)以及夾置於各個絕緣層之間的重佈線層(例如，重佈線層15051及重佈線層15052)。熟習此項技術者應認識到，絕緣層的數目及重佈線層的數目僅供用於說明，而非限制本發明的範圍。在其他實施例中，視對所得封裝元件的設計要求而定，重佈線結構可包括適當數目的絕緣層及重佈線層。
進一步參照圖15，在重佈線結構1501之上形成電性耦合 至重佈線結構1501的凸塊下金屬(underbump metallization，UMB)1507。在一些實施例中，可形成穿過絕緣層15033的一組開口以暴露出重佈線層15052的部分。在一些實施例中，凸塊下金屬1507可包含多個導電材料層，例如鈦層、銅層及鎳層。然而，此項技術中具有通常知識者應認識到，存在諸多適合於形成凸塊下金屬1507的材料及層的適合配置方式，例如鉻/鉻銅合金/銅/金的配置方式、鈦/鈦鎢/銅的配置方式或銅/鎳/金的配置方式。可用於凸塊下金屬1507的任何適合的材料或材料層應完全包含於本申請案的範圍內。在一些實施例中，在凸塊下金屬1507之上形成電性耦合至凸塊下金屬1507的連接件1509。在一些實施例中，連接件1509可為焊球、受控塌陷晶片連接(controlled collapse chip connection，C4)凸塊、球柵陣列封裝(ball grid array，BGA)球、微凸塊、無電鍍鎳鈀浸金技術(electroless nickel-electroless palladium-immersion gold technique，ENEPIG)所形成的凸塊等。在其中連接件1509是由焊料材料形成的一些實施例中，可執行回焊製程以將焊料材料塑形成所期望凸塊形狀。在其他實施例中，連接件1509可為可使用與以上參照圖5闡述的導電樁501相似的材料及方法形成的導電樁，且為簡潔起見在本文中將不再對其予以贅述。在其中連接件1509包括導電樁的一些實施例中，連接件1509可更包括可形成於導電樁的頂部上的頂蓋層。在一些實施例中，頂蓋層可包含焊料、鎳、錫、錫-鉛、金、銀、鈀、銦、鎳-鈀-金、鎳-金、類似材料、或其組合等，且可使用電化學鍍覆製程、無電鍍覆製程、 其組合等形成。
參照圖16A，在形成連接件1509之後，將所得結構接著至由框架1611支撐的膠帶1609，以使得連接件1509接觸膠帶1609。在一些實施例中，膠帶1609可包括晶粒接著膜、劃切膠帶等。緊接著，將載體901(參見圖15)自所得結構分離並暴露出所得結構的表面1613。
進一步參照圖16A，在導通孔1003的暴露的表面及包封體1301的暴露的表面之上形成環形結構1607。在一些實施例中，環形結構1607在圖17所示的平面圖中環繞對應的導通孔1003。在一些實施例中，環形結構1607是藉由使用分配設備(dispensing apparatus)1601在表面1613上的期望位置之上分配聚合物材料1603來形成。在一些實施例中，聚合物材料1603可包括可紫外光固化聚合物材料，例如環氧樹脂、丙烯酸酯(acrylate)、胺基甲酸脂、硫醇(thiols)、其組合等。在一些實施例中，可在導通孔1003與包封體1301之間的介面處或所述介面附近以液體形式分配聚合物材料1603。在一些實施例中，分配設備1601可如箭頭1605所指示般掃過表面1613且在表面1613上的期望位置之上分配聚合物材料1603。在一些實施例中，分配設備1601可包括紫外光源。在一些實施例中，在表面1613上的期望位置之上分配聚合物材料1603之後，紫外光源可將所分配的聚合物材料1603暴露至紫外光。在一些實施例中，紫外光的波長可介於約250奈米與約600奈米之間。在一些實施例中，紫外光源可將所分配的聚合物材料1603 暴露至紫外光達約0.1毫秒與約1毫秒之間的時間。在紫外光的影響下，所分配的聚合物材料1603被固化且經歷聚合(交聯(cross-linking))以使所分配的聚合物材料1603硬化。在固化之後，所分配的聚合物材料1603形成環形結構1607，以使得環形結構1607橫跨包封體1301與導通孔1003之間的介面而延伸。
在其他實施例中，聚合物材料1603可包括熱固性聚合物材料，例如環氧樹脂、聚醯亞胺、其組合等。在該些實施例中，可藉由使聚合物材料1603經受適合的熱處理來將聚合物材料1603固化。在一些實施例中，可以介於約100℃與約400℃之間的溫度執行熱處理。在一些實施例中，可執行熱處理達約5分鐘與4小時之間的時間。
在一些實施例中，在形成環形結構1607之前，可使包封體1301的暴露的表面凹陷以如圖16B所示暴露出導通孔1003的側壁。在該些實施例中，環形結構1607接觸導通孔1003的暴露的側壁。在一些實施例中，可使用適合的蝕刻製程(例如(舉例而言)，各向異性乾蝕刻製程)來使包封體1301的暴露的表面凹陷。在一些實施例中，可使用包含CF4、O2、N2、其組合等的氣體混合物來執行適合的蝕刻製程。如以上更詳細地闡述，不對所分配的聚合物材料1603執行單獨的圖案化製程來形成環形結構1607。因此，本文所述各種實施例能夠減少製造步驟的數目並降低用於形成積體電路封裝的製造成本。
參照圖17，其示出導通孔1003以及對應的環形結構1607 的平面圖。在一些實施例中，導通孔1003具有寬度W1。在一些實施例中，環形結構1607具有內徑W2及外徑W3，且使得外徑W3大於內徑W2。在一些實施例中，內徑W2小於寬度W1，且寬度W1小於外徑W3，以使得環形結構1607與導通孔1003和包封體1301之間的介面交疊。在一些實施例中，寬度W1介於約20微米與約500微米之間。在一些實施例中，內徑W2介於約10微米與約450微米之間。在一些實施例中，外徑W3介於約30微米與約600微米之間。在一些實施例中，比率W1/W2介於約1.1與約2.0之間。在一些實施例中，比率W3/W2介於約1與約2.5之間。在所說明的實施例中，導通孔1003在平面圖中具有圓形形狀且環形結構1607在平面圖中具有環形形狀。在其他實施例中，導通孔1003在平面圖中可具有橢圓形形狀、正方形形狀、矩形形狀、多邊形形狀等，且環形結構1607的內邊緣及外邊緣在平面圖中可具有橢圓形形狀、正方形形狀、矩形形狀、多邊形形狀等。在一些實施例中，導通孔1003及環形結構1607在平面圖中可具有相似的形狀。舉例而言，在其中導通孔1003在平面圖中具有橢圓形形狀的一些實施例中，對應的環形結構1607的內邊緣及外邊緣亦可具有橢圓形形狀。
參照圖18A及圖18B，在形成環形結構1607之後，可對所得結構進行劃切以分別形成個別的積體電路封裝1801A及積體電路封裝1801B。積體電路封裝1801A對應於其中在形成環形結構1607之前包封體1301不凹陷的實施例。積體電路封裝1801B 對應於其中在形成環形結構1607之前包封體1301凹陷的實施例。在一些實施例中，可藉由鋸切、雷射燒蝕方法、其組合等來對所得結構進行劃切。緊接著，可對積體電路封裝1801A中的每一者以及積體電路封裝1801B中的每一者進行測試以辨識已知良好封裝(known good package，KGP)以進行進一步處理。
參照圖19A，在一些實施例中，利用穿過環形結構1607中的開口而延伸的一組連接件1903來將工件1901結合至積體電路封裝1801A以形成堆疊半導體元件1900。在所說明的實施例中，工件1901為封裝。在其他實施例中，工件1901可為一或多個晶粒、印刷電路板(printed circuit board，PCB)、封裝基板、中介層等。在其中工件1901為封裝的一些實施例中，堆疊半導體元件1900為疊層封裝(package on package，PoP)元件。在其中工件1901為晶粒的其他實施例中，堆疊半導體元件1900為封裝上晶片(CoP)元件。在一些實施例中，可使用與以上參照圖15闡述的連接件1509相似的材料及方法形成連接件1903，且為簡潔起見在本文中將不再對其予以贅述。在其他實施例中，可在以上參照圖18A闡述的劃切製程之前將工件1901結合至積體電路封裝1801A。
進一步參照圖19A，可將底部填充材料1905注入於或以其他方式形成於位於工件1901與積體電路封裝1801A之間以及環繞連接件1903的空間中。底部填充材料1905可例如為被分配於各結構之間的液體環氧樹脂、可變形凝膠、矽橡膠等，且底部填充材料1905接著被固化以進行硬化。此底部填充材料1905可尤 其用於減少連接件1903的損壞並且保護連接件1903。
圖19B示出圖19A所示區1907的放大剖視圖。在一些實施例中，包封體1301及導通孔1003具有高度H1，且環形結構1607的最頂部表面相對於包封體1301的底表面具有高度H2。在一些實施例中，高度H2大於高度H1。在一些實施例中，高度H1介於約30微米與約300微米之間。在一些實施例中，高度H2介於約35微米與約350微米之間。在一些實施例中，比率H1/H2介於約0.8與約0.99之間。在一些實施例中，連接件1903的側壁與對應的導通孔1003的頂表面形成角度α1。在一些實施例中，角度α1小於約70度，例如介於約20度與約50度之間。在一些實施例中，環形結構1607在導通孔1003與對應的連接件1903之間的介面處將包封體1301自底部填充材料1905隔開。在一些實施例中，藉由在導通孔1003與對應的連接件1903之間的介面處形成環形結構1607，可在對堆疊半導體元件1900執行可靠性測試的同時及/或在堆疊半導體元件1900的正常運作期間防止或消除包封體1301自導通孔1003分層以及底部填充材料1905自連接件1903分層。在一些實施例中，藉由在包封體1301與底部填充材料1905之間形成環形結構，在對堆疊半導體元件1900執行可靠性測試的同時及/或在堆疊半導體元件1900的正常運作期間可防止或消除包封體1301及/或底部填充材料1905中形成裂紋、以及包封體1301與底部填充材料1905之間的裂紋擴展。
參照圖20A，在一些實施例中，利用延伸穿過環形結構 1607中的開口的一組連接件1903來將工件1901結合至積體電路封裝1801B以形成堆疊半導體元件2000。在所說明的實施例中，工件1901為封裝。在其他實施例中，工件1901可為一或多個晶粒、印刷電路板(PCB)、封裝基板、中介層等。在其中工件1901為封裝的一些實施例中，堆疊半導體元件2000為疊層封裝(PoP)元件。在其中工件1901為晶粒的其他實施例中，堆疊半導體元件2000為封裝上晶片(CoP)元件。在其他實施例中，可在以上參照圖18B闡述的劃切製程之前將工件1901結合至積體電路封裝1801B。在一些實施例中，可將底部填充材料1905注入於或以其他方式形成於位於工件1901與積體電路封裝1801B之間以及環繞連接件1903的空間中。
圖20B示出圖20A所示區2001的放大剖視圖。在一些實施例中，包封體1301具有高度H5，導通孔1003具有高度H3，且環形結構1607的最頂部表面相對於包封體1301的底表面具有高度H4。在一些實施例中，高度H4大於高度H3，且高度H3大於高度H5。在一些實施例中，高度H3介於約30微米與約300微米之間。在一些實施例中，高度H4介於約35微米與約350微米之間。在一些實施例中，高度H5介於約20微米與約290微米之間。在一些實施例中，比率H3/H4介於約0.8與約0.99之間。在一些實施例中，比率H4/H5介於約1.1與約1.5之間。在一些實施例中，連接件1903的側壁與對應的導通孔1003的頂表面形成角度α2。在一些實施例中，角度α2小於約70度，例如介於約30度與約50 度之間。在一些實施例中，環形結構1607在導通孔1003與對應的連接件1903之間的介面處將包封體1301自底部填充材料1905隔開。在一些實施例中，藉由在導通孔1003與對應的連接件1903之間的介面處形成環形結構1607，可在對堆疊半導體元件2000執行可靠性測試的同時及/或在堆疊半導體元件2000的正常運作期間防止或消除包封體1301自導通孔1003分層以及底部填充材料1905自連接件1903分層。在一些實施例中，藉由在包封體1301與底部填充材料1905之間形成環形結構1607，可在對堆疊半導體元件2000執行可靠性測試的同時及/或在堆疊半導體元件2000的正常運作期間防止或消除包封體1301及/或底部填充材料1905中形成裂紋、以及包封體1301與底部填充材料1905之間的裂紋擴展。
圖21至圖24、圖25A、圖25B、及圖26是根據一些實施例的使用在圖1至圖8中製作的積體電路晶粒來製作積體電路封裝期間的各個處理步驟的剖視圖。以下參照圖21至圖24、圖25A、圖25B、及圖26闡述的實施例與以上參照圖9至圖15、圖16A、圖16B、圖17、圖18A、圖18B、圖19A、圖19B、圖20A及圖20B闡述的實施例相似，其中使用相同的參考編號來標示相同的元件。
參照圖21，在一些實施例中，在載體901之上形成離形層903，在離形層903之上形成導通孔1003，且將積體電路晶粒801接著至離形層903。在一些實施例中，導通孔1003包括晶種 層905以及位於晶種層905之上的導電樁1001。在一些實施例中，可使用以上參照圖9至圖12闡述的方法形成圖21所示結構，且為簡潔起見在本文中將不再對其予以贅述。
進一步參照圖21，在形成導通孔1003並將積體電路晶粒801接著至離形層903之後，在離形層903之上形成環繞導通孔1003的環形結構2101。在一些實施例中，環形結構2101是藉由使用分配設備1601在離形層903上的期望位置之上分配聚合物材料1603形成。在一些實施例中，分配設備1601可如箭頭1605所指示般掃過離形層903且在離形層903上的期望位置之上以液體形式分配聚合物材料1603。在一些實施例中，聚合物材料1603可包括可紫外光固化聚合物材料，例如環氧樹脂、丙烯酸酯、胺基甲酸脂、硫醇、其組合等。在一些實施例中，分配設備1601可包括紫外光源。在一些實施例中，在離形層903上的期望位置之上分配聚合物材料1603之後，紫外光源可將所分配的聚合物材料1603暴露至紫外光。在一些實施例中，紫外光的波長可介於約250奈米與約600奈米之間。在一些實施例中，紫外光源可將所分配的聚合物材料1603暴露至紫外光達約0.1毫秒與約1毫秒之間的時間。在紫外光的影響下，所分配的聚合物材料1603被固化且經歷聚合(交聯)以使所分配的聚合物材料1603硬化。在固化之後，所分配的聚合物材料1603形成環形結構2101。在一些實施例中，環形結構2101的暴露表面可為非平面表面，例如凹的表面(參見圖25B)。
在其他實施例中，聚合物材料1603可包括熱固性聚合物材料，例如環氧樹脂、聚醯亞胺、其組合等。在該些實施例中，可藉由使聚合物材料1603經受適合的熱處理來將聚合物材料1603固化。在一些實施例中，可以介於約100℃與約400℃之間的溫度執行熱處理。在一些實施例中，可執行熱處理達約5分鐘與4小時之間的時間。如以上更詳細地闡述，不對所分配的聚合物材料1603執行單獨的圖案化製程來形成環形結構2101。因此，本文所述各種實施例能夠減少製造步驟的數目並降低用於形成積體電路封裝的製造成本。
參照圖22，其示出導通孔1003以及對應的環形結構2101的平面圖。在一些實施例中，導通孔1003具有寬度W4。在一些實施例中，環形結構2101具有內徑W4及外徑W5，使得外徑W5大於內徑W4。在一些實施例中，內徑W4介於約10微米與約450微米之間。在一些實施例中，外徑W5介於約30微米與約600微米之間。在一些實施例中，比率W4/W5介於約0.2與約0.99之間。在一些實施例中，可將導通孔1003完全設置於環形結構2101中的開口內。在所說明的實施例中，導通孔1003在平面圖中具有圓形形狀且環形結構2101在平面圖中具有環形形狀。在其他實施例中，導通孔1003在平面圖中可具有橢圓形形狀、正方形形狀、矩形形狀、多邊形形狀等，且環形結構2101的內邊緣及外邊緣在平面圖中可具有橢圓形形狀、正方形形狀、矩形形狀、多邊形形狀等。在一些實施例中，導通孔1003及環形結構2101在平面圖中可具 有相似的形狀。舉例而言，在其中導通孔1003在平面圖中具有橢圓形形狀的一些實施例中，對應的環形結構2101的內邊緣及外邊緣亦可具有橢圓形形狀。
參照圖23，形成包封體1301，其中包封體1301經形成在載體901之上、以及在積體電路晶粒801及導通孔1003之上並環繞積體電路晶粒801及導通孔1003。接著，對包封體1301進行平坦化，以使得積體電路晶粒801的導電樁501的頂表面與導通孔1003的頂表面及包封體1301的頂表面實質上共面。在一些實施例中，可使用參照圖13及圖14闡述的方法形成包封體1301並將包封體1301圖案化，且為簡潔起見將不再對其予以贅述。
進一步參照圖23，在將包封體1301平坦化之後，在積體電路晶粒801、導通孔1003、及包封體1301之上形成重佈線結構1501。緊接著，在重佈線結構1501之上形成電性耦合至重佈線結構1501的凸塊下金屬(UBM)1507，並且在凸塊下金屬1507之上形成電性耦合至凸塊下金屬1507的連接件1509。在一些實施例中，可使用以上參照圖15闡述的方法形成重佈線結構1501、凸塊下金屬1507、及連接件1509，且為簡潔起見在本文中將不再對其予以贅述。
參照圖24，在一些實施例中，將所得結構接著至由框架1611支撐的膠帶1609，以使連接件1509接觸膠帶1609。在一些實施例中，膠帶1609可包括晶粒接著膜、劃切膠帶等。接著，將載體901(參見圖23)自所得結構分離，且對所得結構進行劃切以 形成個別的積體電路封裝2400。在一些實施例中，可藉由鋸切、雷射燒蝕方法、其組合等來對所得結構進行劃切。接著，可對積體電路封裝2400中的每一者進行測試以辨識已知良好封裝(known good package，KGP)以進行進一步處理。
參照圖25A，在一些實施例中，利用耦合至對應的導通孔1003的一組連接件1903來將工件1901結合至積體電路封裝2400以形成堆疊半導體元件2500。在所說明的實施例中，工件1901為封裝。在其他實施例中，工件1901可為一或多個晶粒、印刷電路板(PCB)、封裝基板、中介層等。在其中工件1901為封裝的一些實施例中，堆疊半導體元件2500為疊層封裝(PoP)元件。在其中工件1901為晶粒的其他實施例中，堆疊半導體元件2500為封裝上晶片(CoP)元件。在其他實施例中，可在以上參照圖24闡述的劃切製程之前將工件1901結合至積體電路封裝2400。
進一步參照圖25A，可將底部填充材料1905注入於或以其他方式形成於位於工件1901與積體電路封裝2400之間以及環繞連接件1903的空間中。在一些實施例中，可使用參照圖18A闡述的方法形成底部填充材料1905，且為簡潔起見在本文中將不再對其予以贅述。
圖25B示出圖25A所示區2501的放大剖視圖。在一些實施例中，與包封體1301接觸的環形結構2101的表面可為非平面表面，例如為凹的表面。在一些實施例中，環形結構2101在導通孔1003與對應的連接件1903之間的介面處將包封體1301自底 部填充材料1905隔開。在一些實施例中，藉由在導通孔1003與對應的連接件1903之間的介面處形成環形結構2101，可在對堆疊半導體元件2500執行可靠性測試的同時及/或在堆疊半導體元件2500的正常運作期間防止或消除包封體1301自導通孔1003分層以及底部填充材料1905自連接件1903分層。在一些實施例中，藉由在包封體1301與底部填充材料1905之間形成環形結構2101，在對堆疊半導體元件2500執行可靠性測試的同時及/或在堆疊半導體元件2500的正常運作期間可防止或消除包封體1301及/或底部填充材料1905中形成裂紋、以及包封體1301與底部填充材料1905之間的裂紋擴展。
圖26示出藉由利用一組耦合至對應導通孔1003的連接件1903將工件1901結合至積體電路封裝2601而形成的堆疊半導體元件2600。在一些實施例中，可使用與以上參照圖21至圖24闡述的積體電路封裝2400相似的方法來形成積體電路封裝2601，其中藉由相同的參考編號來標示相同的元件，且為簡潔起見在本文中將不再對其予以贅述。在所說明的實施例中，對相鄰的環形結構2101進行合併以形成經合併的環形結構2101。在一些實施例中，經合併的環形結構2101在相鄰的導通孔1003之間延伸，以使得經合併的環形結構2101的背對底部填充材料1905的表面包括凹的表面。在其中相鄰的導通孔1003之間的距離小於個別環形結構2101的寬度(環形結構2101的外徑與內徑之間的差的量測寬度)的兩倍的一些實施例中，相鄰的個別環形結構2101可彼此 接觸且可合併於一起以形成經合併的環形結構2101。
圖27是說明根據一些實施例的一種形成積體電路封裝的方法2700的流程圖。方法2700始於步驟2701，在步驟2701中，如以上參照圖9至圖11所述，在載體(例如，圖11所示載體901)之上形成一或多個導電柱(例如，圖11所示導通孔1003)。在步驟2703中，如以上參照圖12所述，將一或多個積體電路晶粒(例如，圖12所示積體電路晶粒801)接著至載體。在步驟2705中，如以上參照圖13及圖14所述，在所述一或多個導電柱及所述一或多個積體電路晶粒周圍形成包封體(例如，圖14所示包封體1301)。在步驟2707中，如以上參照圖16A及圖16B所述，移除載體。在步驟2709中，如以上參照圖16A及圖16B所述，在所述一或多個導電柱及包封體之上分配聚合物材料(例如，圖16A及圖16B所示聚合物材料1603)。在步驟2711中，如以上參照圖16A及圖16B所述，將聚合物材料固化以形成一或多個環形結構(例如，圖16A及圖16B所示環形結構1607)，所述一或多個環形結構環繞對應的導電柱。
圖28是說明根據一些實施例的一種形成積體電路封裝的方法2800的流程圖。方法2800始於步驟2801，在步驟2801中，如以上參照圖21所述，在載體(例如，圖21所示載體901)之上形成一或多個導電柱(例如，圖21所示導通孔1003)。在步驟2803中，如以上參照圖21所述，將一或多個積體電路晶粒(例如，圖21所示積體電路晶粒801)接著至載體。在步驟2805中，如以上 參照圖21所述，在載體之上以及在所述一或多個導電柱周圍分配聚合物材料(例如，圖21所示聚合物材料1603)。在步驟2807中，如以上參照圖21所述，將聚合物材料固化以形成一或多個環形結構(例如，圖21所示環形結構2101)，所述一或多個環形結構環繞對應的導電柱。在步驟2809中，如以上參照圖23所述，在所述一或多個環形結構之上以及在所述一或多個導電柱及所述一或多個積體電路晶粒周圍形成包封體(例如，圖23所示包封體1301)。
根據實施例，一種積體電路封裝的形成方法包括：在載體之上形成導電柱；將積體電路晶粒接著至所述載體，所述積體電路晶粒鄰近所述導電柱設置；在所述導電柱及所述積體電路晶粒周圍形成包封體；移除所述載體，以暴露出所述導電柱的第一表面及所述包封體的第二表面；在所述第一表面及所述第二表面之上形成聚合物材料；以及將所述聚合物材料固化以形成環形結構，其中在平面圖中所述環形結構的內邊緣與所述第一表面交疊，且其中在所述平面圖中所述環形結構的外邊緣與所述第二表面交疊。在實施例中，所述聚合物材料包括可紫外光固化聚合物材料。在實施例中，將所述聚合物材料固化包括將所述聚合物材料暴露至紫外光。在實施例中，所述聚合物材料包括可熱固化聚合物材料。在實施例中，將所述聚合物材料固化包括對所述聚合物材料執行熱處理。在實施例中，所述方法更包括：在移除所述載體之前，在所述導電柱、所述積體電路晶粒及所述包封體之上形成重佈線結構，所述重佈線結構電性耦合至所述導電柱及所述積體電路晶粒。在實 施例中，所述方法更包括：在形成所述聚合物材料之前，使所述包封體凹陷以暴露出所述導電柱的側壁。在實施例中，所述環形結構的至少一部分沿所述導電柱的側壁延伸。在實施例中，所述導電柱的至少一部分被所述環形結構中的開口暴露。
根據另一實施例，一種積體電路封裝的形成方法包括：在載體之上形成導電柱；將積體電路晶粒接著至所述載體，所述積體電路晶粒鄰近所述導電柱設置；在所述載體之上及所述導電柱周圍形成聚合物材料；將所述聚合物材料固化以形成環形結構；以及在所述環形結構之上以及所述導電柱及所述積體電路晶粒周圍形成包封體。在實施例中，所述聚合物材料包括可紫外光固化聚合物材料。在實施例中，將所述聚合物材料固化包括將所述聚合物材料暴露至紫外光。在實施例中，所述聚合物材料包括可熱固化聚合物材料。在實施例中，將所述聚合物材料固化包括對所述聚合物材料執行熱處理。在實施例中，所述方法更包括在所述導電柱、所述積體電路晶粒及所述包封體之上形成重佈線結構，所述重佈線結構電性耦合至所述導電柱及所述積體電路晶粒。在實施例中，所述方法更包括：在形成所述重佈線結構之後，移除所述載體以暴露出所述導電柱的第一表面及所述環形結構的第二表面。在實施例中，所述第一表面與所述第二表面實質上齊平。在實施例中，位於環形結構與包封體之間的介面不是平面。
根據再一實施例，一種半導體封裝結構包括：積體電路晶粒；包封體，沿所述積體電路晶粒的側壁延伸，所述包封體具有第 一表面及與所述第一表面相對的第二表面；導電柱，在所述第一表面與所述第二表面之間延伸穿過所述包封體；以及環形結構，設置於所述包封體的所述第一表面處，在平面圖中，所述環形結構環繞所述導電柱。在實施例中，所述導電柱的第三表面與所述包封體的所述第一表面實質上齊平，其中在所述平面圖中所述環形結構的內邊緣與所述第三表面交疊，且其中在所述平面圖中所述環形結構的外邊緣與所述第一表面交疊。在實施例中，所述結構更包括延伸至所述環形結構的開口中的焊料區，所述焊料區電性耦合至所述導電柱。在實施例中，所述導電柱的至少一部分在所述包封體的所述第一表面上方延伸，且其中所述環形結構的至少一部分沿所述導電柱的側壁延伸。在實施例中，所述導電柱的第三表面與所述環形結構的第四表面實質上齊平。在實施例中，所述環形結構與所述包封體之間的介面不是平面。
亦可包括其他特徵及製程。舉例而言，可包括測試結構，以幫助對三維(three dimensional，3D)封裝或三維積體電路(three dimensional integrated circuit，3DIC)元件進行驗證測試。所述測試結構可例如包括在重佈線層中或在基板上形成的測試接墊(test pad)，以便能夠對三維封裝或三維積體電路進行測試、使用探針及/或探針卡(probe card)等。可對中間結構以及最終結構執行驗證測試。另外，可將本文中所揭露的結構及方法與包含對已知良好晶粒進行中間驗證的測試方法結合使用，以提高良率並降低成本。
以上概述了若干實施例的特徵，以使熟習此項技術者可 更佳地理解本發明的各個態樣。熟習此項技術者應知，其可容易地使用本發明作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或達成與本文中所介紹的實施例相同的優點。熟習此項技術者亦應認識到，該些等效構造並不背離本發明的精神及範圍，而且其可在不背離本發明的精神及範圍的條件下對其作出各種改變、代替及變更。

Claims (14)

  1. 一種積體電路封裝的形成方法，包括：在載體之上形成導電柱；將積體電路晶粒接著至所述載體，所述積體電路晶粒鄰近所述導電柱設置；在所述導電柱及所述積體電路晶粒周圍形成包封體；移除所述載體，以暴露出所述導電柱的第一表面及所述包封體的第二表面；在所述第一表面及所述第二表面之上形成聚合物材料；以及將所述聚合物材料固化以形成環形結構，其中在平面圖中所述環形結構的內邊緣與所述第一表面交疊，其中在所述平面圖中所述環形結構的外邊緣與所述第二表面交疊，其中所述環形結構實體接觸並環繞所述導電柱的一部分，且其中所述導電柱的另一部分實體接觸於所述包封體。
  2. 如申請專利範圍第1項所述的積體電路封裝的形成方法，其中所述聚合物材料包括可紫外光固化聚合物材料或可熱固化聚合物材料。
  3. 如申請專利範圍第1項所述的積體電路封裝的形成方法，更包括：在移除所述載體之前，在所述導電柱、所述積體電路晶粒及所述包封體之上形成重佈線結構，所述重佈線結構電性耦合至所述導電柱及所述積體電路晶粒。
  4. 如申請專利範圍第1項所述的積體電路封裝的形成方法，更包括：在形成所述聚合物材料之前，使所述包封體凹陷以暴露出所述導電柱的側壁。
  5. 一種積體電路封裝的形成方法，包括：在載體之上形成導電柱；將積體電路晶粒接著至所述載體，所述積體電路晶粒鄰近所述導電柱設置；在所述載體之上及所述導電柱周圍形成聚合物材料；將所述聚合物材料固化以形成環形結構；以及在所述環形結構之上以及所述導電柱及所述積體電路晶粒周圍形成包封體，其中所述環形結構實體接觸並環繞所述導電柱的一部分，且其中所述導電柱的另一部分實體接觸於所述包封體。
  6. 如申請專利範圍第5項所述的積體電路封裝的形成方法，其中所述聚合物材料包括可紫外光固化聚合物材料或可熱固化聚合物材料。
  7. 如申請專利範圍第5項所述的積體電路封裝的形成方法，更包括在所述導電柱、所述積體電路晶粒及所述包封體之上形成重佈線結構，所述重佈線結構電性耦合至所述導電柱及所述積體電路晶粒。
  8. 如申請專利範圍第7項所述的積體電路封裝的形成方法，更包括：在形成所述重佈線結構之後，移除所述載體以暴露出所述導電柱的第一表面及所述環形結構的第二表面。
  9. 一種積體電路封裝，包括：積體電路晶粒；包封體，沿所述積體電路晶粒的側壁延伸，所述包封體具有第一表面及與所述第一表面相對的第二表面；導電柱，在所述第一表面與所述第二表面之間延伸穿過所述包封體；以及環形結構，設置於所述包封體的所述第一表面處，在平面圖中，所述環形結構環繞所述導電柱，其中所述導電柱的一部分實體接觸於所述環形結構，且其中所述導電柱的另一部分實體接觸於所述包封體。
  10. 如申請專利範圍第9項所述的積體電路封裝，其中所述導電柱的第三表面與所述包封體的所述第一表面實質上齊平，其中在所述平面圖中所述環形結構的內邊緣與所述第三表面交疊，且其中在所述平面圖中所述環形結構的外邊緣與所述第一表面交疊。
  11. 如申請專利範圍第10項所述的積體電路封裝，更包括延伸至所述環形結構的開口中的焊料區，所述焊料區電性耦合至所述導電柱。
  12. 如申請專利範圍第9項所述的積體電路封裝，其中所述導電柱的至少一部分在所述包封體的所述第一表面上方延伸，且其中所述環形結構的至少一部分沿所述導電柱的側壁延伸。
  13. 如申請專利範圍第9項所述的積體電路封裝，其中所述導電柱的第三表面與所述環形結構的第四表面實質上齊平。
  14. 如申請專利範圍第9項所述的積體電路封裝，其中所述環形結構與所述包封體之間的介面不是平面。
TW106143045A 2017-06-30 2017-12-08 積體電路封裝及其形成方法 TWI673848B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201762527506P 2017-06-30 2017-06-30
US62/527,506 2017-06-30
US15/722,655 2017-10-02
US15/722,655 US10269587B2 (en) 2017-06-30 2017-10-02 Integrated circuit packages and methods of forming same

Publications (2)

Publication Number Publication Date
TW201906121A TW201906121A (zh) 2019-02-01
TWI673848B true TWI673848B (zh) 2019-10-01

Family

ID=64738308

Family Applications (1)

Application Number Title Priority Date Filing Date
TW106143045A TWI673848B (zh) 2017-06-30 2017-12-08 積體電路封裝及其形成方法

Country Status (3)

Country Link
US (3) US10269587B2 (zh)
CN (1) CN109216204B (zh)
TW (1) TWI673848B (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10199311B2 (en) * 2009-01-29 2019-02-05 Semiconductor Components Industries, Llc Leadless semiconductor packages, leadframes therefor, and methods of making
US11257679B2 (en) * 2018-11-26 2022-02-22 Stmicroelectronics Pte Ltd Method for removing a sacrificial layer on semiconductor wafers
TWI709212B (zh) * 2019-03-05 2020-11-01 台灣積體電路製造股份有限公司 晶圓接合結構及其形成方法
KR20210095442A (ko) 2020-01-23 2021-08-02 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US11929261B2 (en) * 2020-05-01 2024-03-12 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method of manufacturing the same
DE102020130996A1 (de) * 2020-05-01 2021-11-04 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleiter-package und verfahren zu dessen herstellung
KR20220014492A (ko) 2020-07-29 2022-02-07 삼성전자주식회사 팬-아웃 반도체 패키지

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000306949A (ja) * 1999-04-23 2000-11-02 Casio Comput Co Ltd 半導体装置及びその製造方法並びにその実装構造
CN103972191A (zh) * 2013-01-31 2014-08-06 台湾积体电路制造股份有限公司 具有环绕封装通孔端部的开口的管芯封装件及层叠封装件
CN105590914A (zh) * 2014-10-24 2016-05-18 宏启胜精密电子(秦皇岛)有限公司 电子元件封装结构及制作方法
TW201642360A (zh) * 2015-03-03 2016-12-01 蘋果公司 扇出系統級封裝及用於形成其之方法

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6578755B1 (en) 2000-09-22 2003-06-17 Flip Chip Technologies, L.L.C. Polymer collar for solder bumps
US9048233B2 (en) 2010-05-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
US9064879B2 (en) 2010-10-14 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures using a die attach film
US8797057B2 (en) 2011-02-11 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Testing of semiconductor chips with microbumps
US8643148B2 (en) 2011-11-30 2014-02-04 Taiwan Semiconductor Manufacturing Company, Ltd. Chip-on-Wafer structures and methods for forming the same
SG11201402261SA (en) 2011-12-07 2014-08-28 Georgia Tech Res Inst Packaging compatible wafer level capping of mems devices
US9000584B2 (en) 2011-12-28 2015-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor device with a molding compound and a method of forming the same
US9111949B2 (en) 2012-04-09 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus of wafer level package for heterogeneous integration technology
KR101867955B1 (ko) 2012-04-13 2018-06-15 삼성전자주식회사 패키지 온 패키지 장치 및 이의 제조 방법
US9508674B2 (en) 2012-11-14 2016-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Warpage control of semiconductor die package
US9263511B2 (en) 2013-02-11 2016-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Package with metal-insulator-metal capacitor and method of manufacturing the same
US9048222B2 (en) 2013-03-06 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating interconnect structure for package-on-package devices
US8987922B2 (en) * 2013-03-11 2015-03-24 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for wafer level packaging
US9368460B2 (en) 2013-03-15 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out interconnect structure and method for forming same
US9281254B2 (en) 2014-02-13 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming integrated circuit package
US9496189B2 (en) 2014-06-13 2016-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked semiconductor devices and methods of forming same
US10153175B2 (en) 2015-02-13 2018-12-11 Taiwan Semiconductor Manufacturing Company, Ltd. Metal oxide layered structure and methods of forming the same
US9595482B2 (en) * 2015-03-16 2017-03-14 Taiwan Semiconductor Manufacturing Company, Ltd. Structure for die probing
US9461018B1 (en) 2015-04-17 2016-10-04 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out PoP structure with inconsecutive polymer layer
US9793231B2 (en) * 2015-06-30 2017-10-17 Taiwan Semiconductor Manufacturing Company, Ltd. Under bump metallurgy (UBM) and methods of forming same
US9570410B1 (en) 2015-07-31 2017-02-14 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming connector pad structures, interconnect structures, and structures thereof
CN106486453A (zh) * 2015-08-25 2017-03-08 力成科技股份有限公司 一种柱顶互连型态半导体封装构造及其制造方法
US9786614B2 (en) * 2015-11-16 2017-10-10 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out structure and method of forming
US9892962B2 (en) 2015-11-30 2018-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level chip scale package interconnects and methods of manufacture thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000306949A (ja) * 1999-04-23 2000-11-02 Casio Comput Co Ltd 半導体装置及びその製造方法並びにその実装構造
CN103972191A (zh) * 2013-01-31 2014-08-06 台湾积体电路制造股份有限公司 具有环绕封装通孔端部的开口的管芯封装件及层叠封装件
CN105590914A (zh) * 2014-10-24 2016-05-18 宏启胜精密电子(秦皇岛)有限公司 电子元件封装结构及制作方法
TW201642360A (zh) * 2015-03-03 2016-12-01 蘋果公司 扇出系統級封裝及用於形成其之方法

Also Published As

Publication number Publication date
CN109216204B (zh) 2021-11-09
US10269587B2 (en) 2019-04-23
US20190109020A1 (en) 2019-04-11
US20210005464A1 (en) 2021-01-07
TW201906121A (zh) 2019-02-01
US11527418B2 (en) 2022-12-13
CN109216204A (zh) 2019-01-15
US20190006194A1 (en) 2019-01-03
US10784123B2 (en) 2020-09-22

Similar Documents

Publication Publication Date Title
US11967563B2 (en) Fan-out package having a main die and a dummy die
US9496189B2 (en) Stacked semiconductor devices and methods of forming same
TWI673848B (zh) 積體電路封裝及其形成方法
US11139249B2 (en) Semiconductor devices and methods of forming the same
US20210320097A1 (en) Integrated circuit package and method of forming same
US11309289B2 (en) Integrated circuit package having heat dissipation structure
US11410918B2 (en) Method of making an integrated circuit package including an integrated circuit die soldered to a bond pad of a carrier
US20240021597A1 (en) Molded Dies in Semiconductor Packages and Methods of Forming Same
TWI713858B (zh) 積體電路封裝及其形成方法
US11842955B2 (en) Method of making an integrated circuit package including an integrated circuit die soldered to a bond pad of a redistribution structure
US11239233B2 (en) Integrated circuit packages and methods of forming same
KR101921007B1 (ko) 집적 회로 패키지 및 그 형성 방법