TW201935562A - 封裝及其形成方法 - Google Patents

封裝及其形成方法 Download PDF

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Publication number
TW201935562A
TW201935562A TW107137387A TW107137387A TW201935562A TW 201935562 A TW201935562 A TW 201935562A TW 107137387 A TW107137387 A TW 107137387A TW 107137387 A TW107137387 A TW 107137387A TW 201935562 A TW201935562 A TW 201935562A
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Taiwan
Prior art keywords
substrate
die
pseudo
integrated circuit
package
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TW107137387A
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English (en)
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TWI695432B (zh
Inventor
侯上勇
高金福
吳集錫
余振華
胡憲斌
郭立中
黃松輝
魏文信
施應慶
洪志杰
夏興國
黃賀昌
黃冠育
林于順
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台灣積體電路製造股份有限公司
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Publication of TWI695432B publication Critical patent/TWI695432B/zh

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Abstract

一種積體電路封裝及一種形成所述封裝的方法。所述方法包含將積體電路晶粒貼合至第一基底。形成擬晶粒。將擬晶粒貼合至第一基底，與積體電路晶粒相鄰。包封體形成於第一基底上方且包圍擬晶粒及積體電路晶粒。使包封體、擬晶粒以及積體電路晶粒平坦化，包封體的最頂部表面與擬晶粒的最頂部表面及積體電路晶粒的最頂部表面實質上水平。移除擬晶粒的內部部分。擬晶粒的剩餘部分形成環形結構。

Description

積體電路封裝及其形成方法
半導體裝置用於多種電子應用中，諸如個人電腦、蜂巢式電話、數位攝影機以及其他電子設備。通常藉由在半導體基底上依序沈積絕緣材料層或介電材料層、導電材料層以及半導電材料層以及使用微影術圖案化各種材料層而在其上形成電路組件及元件來製造半導體裝置。通常在單一半導體晶圓上製造數十或數百個積體電路。藉由沿著切割道鋸割積體電路而使個別晶粒單體化。接著以多晶片模組形式或以其他類型的封裝形式單獨地封裝個別晶粒。
半導體產業歸因於各種電子組件（例如，電晶體、二極體、電阻器、電容器等）的積體密度的持續改良而經歷快速發展。主要地，所述積體密度的改良來自反覆減小最小特徵尺寸（例如，使半導體製程節點向小於20奈米的節點縮小），這允許將更多組件整合至給定區域中。隨著近來對小型化、較高速度及較大頻寬以及較低功率消耗及潛時（latency）的需求增加，對半導體晶粒的更小且更具創造性封裝技術的需要亦有所增加。
隨著半導體技術進一步發展，堆疊半導體裝置 （例如三維積體電路（three dimensional integrated circuit；3DIC））已出現為進一步減小半導體裝置的尺寸的有效替代物。在堆疊半導體裝置中，諸如邏輯、記憶體、處理器電路及類似者的主動電路經製造於不同半導體晶圓上。兩個或以上的半導體晶圓可安裝或堆疊於彼此頂部以進一步減小半導體裝置的外觀尺寸。疊層封裝(Package-on-package；POP)裝置是一種3DIC，其中晶粒經封裝且隨後與另一或多個經封裝晶粒封裝在一起。覆晶封裝（chip-on-package；COP）裝置是另一種3DIC，其中晶粒經封裝且隨後與另一或多個晶粒封裝在一起。
以下揭露內容提供用於實施本發明的不同特徵的多個不同實施例或實例。下文描述組件及配置的特定實例以簡化本揭露。當然，這些組件及配置僅為實例且不意欲為限制性的。舉例而言，在以下描述中，第一特徵形成於第二特徵上方或上的可包括第一特徵及第二特徵直接接觸地形成的實施例，且亦可包括額外特徵可形成在第一特徵與第二特徵之間，使得第一特徵及第二特徵可不直接接觸的實施例。另外，本揭露可在各種實例中重複圖式元件符號及/或字母。此重複是出於簡化及清楚的目的，且本身並不指示所論述的各種實施例及/或組態之間的關係。
另外，為易於描述，諸如「在……下方」、「在……之下」、「下部」、「在……之上」、「上部」以及其類似者在本文中可用於描述如圖所示的一個元件或特徵與另一或多個元件或特徵的關係。除圖式中所描繪的定向以外，空間相對術語意欲涵蓋裝置在使用或操作中的不同定向。設備可以其他方式定向（旋轉90度或處於其他定向）且本文中所使用的空間相對描述詞可同樣相應地進行解譯。
實施例將在相關特定背景下來描述，亦即積體電路封裝的背景。然而，其他實施例亦可應用於其他電連接組件，包含但不限於：在組裝封裝中的疊層封裝總成、晶粒間總成、晶圓間總成、晶粒至基底總成、晶粒至晶圓總成；在處理基底、插入件或其類似物中；或安裝輸入組件、板、晶粒或其他組件中；或用於連接任何類型的積體電路或電組件的封裝或安裝組合。本文所描述的各種實施例允許封裝具有不同功能和尺寸（諸如高度）的功能組件（諸如積體電路晶粒）。本文所描述的各種實施例可整合至基底上晶圓覆晶（chip-on-wafer-on-substrate；CoWoS）製程及基底上疊層晶片（chip-on-chip-on-substrate；CoCoS）製程中。
圖1A、圖1B以及圖2至圖4繪示根據一些實施例的在製造擬晶粒（dummy die）（諸如圖4中所繪示的擬晶粒401）期間的各種處理步驟的俯視圖及截面視圖。圖1A繪示俯視圖，而圖1B及圖2至圖4繪示沿圖1A中的線BB'的截面視圖。首先參看圖1A及圖1B，繪示具有由切割道103（亦稱為分割線（dicing line）或分割道（dicing street））分離的晶粒區域101的晶圓100的一部分。如下文更詳細地描述，晶圓100沿切割道103分割以形成個別晶粒（諸如圖4中所繪示的晶粒401）。此外，如下文更詳細地描述，個別晶粒用作犧牲或擬晶粒，其部分在後續封裝步驟中經移除。因此，晶圓100可不包括主動裝置及被動裝置，且個別晶粒可為功能上惰性的或擬晶粒。
在一些實施例中，晶圓100包括基底105。在一些實施例中，基底105可由矽形成，但其亦可由其他第III族、第IV族及/或第V族元素（諸如矽、鍺、鎵、砷以及其組合）形成。基底105亦可呈絕緣體上矽（silicon-on-insulator；SOI）的形式。SOI基底可包括形成於絕緣層（例如內埋氧化物（buried oxide）及/或其類似者）上方的半導體材料層（例如，矽層、鍺層及/或類似層），所述絕緣層形成於矽基底上。另外，可使用的其他基底包含多層基底（multi-layered substrate）、梯度基底（gradient substrate）、混合定向基底（hybrid orientation substrate）、其任何組合及/或其類似者。在其他實施例中，基底105可包括諸如氧化物、氮化物、其組合或其類似者的介電材料。
進一步參看圖1A及圖1B，基底105經圖案化以形成開口107及開口109。在一些實施例中，基底105可使用適合光微影及蝕刻方法來圖案化以形成開口107及開口109。在一些實施例中，用於圖案化開口107及開口109的蝕刻製程可包括非等向性乾式蝕刻（anisotropic dry etching）製程、中性離子束（neutral ion beam）製程或其類似者。在一些實施例中，開口107及開口109可在同一圖案化製程中同時形成。在其他實施例中，開口107及開口109可在不同圖案化製程中在不同時間分別地形成。在一些實施例中，開口107可在後續製程步驟期間，諸如，在後續封裝製程期間用作對準標記。如圖1A中所示，各開口107具有矩形形狀。在其他實施例中，開口107可因對準標記的設計要求而具有其他形狀。如圖1A中進一步所示，各開口109在平面視圖中具有環狀。在所繪示的實施例中，開口109的環狀為矩形環狀。在其他實施例中，開口109的環狀可為圓環狀、橢圓環狀、多邊環狀或其類似者。開口107具有寬度W1且延伸至基底105的最頂部表面下方的深度D1處。開口109具有寬度W2且延伸至基底105的最頂部表面下方的深度D2處。在一些實施例中，寬度W1在約10微米與約30微米之間。在一些實施例中，深度D1在約100微米與約150微米之間。在一些實施例中，比率W1/D1在約0.1與約0.2之間。在一些實施例中，寬度W2在約70微米與約150微米之間。在一些實施例中，深度D2在約200微米與約220微米之間。在一些實施例中，比率W2/D2在約0.35與約0.7之間。
參看圖2，絕緣材料201形成於基底105上方以及開口107及開口109中（參看圖1A及圖1B）。在一些實施例中，絕緣材料201可包括非光可圖案化絕緣材料，諸如氮化矽、氧化矽、磷矽酸鹽玻璃（phosphosilicate glass；PSG）、硼矽酸鹽玻璃（borosilicate glass；BSG）、硼摻磷矽酸鹽玻璃（boron-doped phosphosilicate glass；BPSG）、其組合或其類似者，且可使用化學氣相沈積（chemical vapor deposition；CVD）、物理氣相沈積（physical vapor deposition；PVD）、原子層沈積（atomic layer deposition；ALD）、旋塗式塗佈（spin-on coating）製程、其組合或其類似方法形成。在其他實施例中，絕緣材料201可包括光可圖案化絕緣材料層，諸如聚苯并噁唑（polybenzoxazole；PBO）、聚醯亞胺（polyimide；PI）、苯并環丁烯（benzocyclobutene；BCB）、其組合或其類似者，且可使用旋塗式塗佈製程或其類似方法形成。在一些實施例中，絕緣材料201經圖案化以自基底105的頂部表面移除部分絕緣材料201。在一些實施例中，在圖案化製程之後，絕緣材料201的未經移除部分保持在基底105的頂部表面的部分上，所述部分由各別開口109包圍（參看圖1A）。此外，在圖案化製程之後，絕緣材料201完全填充開口107及開口109（參看圖1A及圖1B）。在絕緣材料201包括光可圖案化絕緣材料的一些實施例中，絕緣材料201可使用適合光微影技術圖案化。在絕緣材料201包括非光可圖案化絕緣材料的其他實施例中，絕緣材料201可使用適合光微影及蝕刻技術圖案化。在一些實施例中，基底105的頂部表面上之絕緣材料201的未經移除部分的厚度T1在約5微米與約15微米之間。
參看圖3，導電層301形成於基底105的頂部表面及絕緣材料201的剩餘部分上方。在一些實施例中，導電層301可包括鈦、氮化鈦、鉭、氮化鉭、銅、其組合或其類似者，且可使用物理氣相沈積、原子層沈積、化學氣相沈積、其組合或其類似方法形成。在一些實施例中，導電層301的厚度在約50奈米與約100奈米之間。在其他實施例中，導電層301可省略。
參看圖4，晶圓100沿切割道103（參看圖1A）經分割以形成個別晶粒401。在一些實施例中，晶圓100可使用鋸割、蝕刻、雷射剝蝕（laser ablation）、其組合或其類似方法分割。晶粒401亦可稱為犧牲晶粒或擬晶粒。
圖5至圖11繪示根據一些實施例的在製造積體電路封裝期間的各種處理步驟的截面視圖。首先參看圖5，繪示堆疊結構500，所述堆疊結構500包括工件501及接合至工件501的頂部表面的積體電路（integrated circuit；IC）晶粒507及積體電路晶粒509。在一些實施例中，工件501為例如晶圓，諸如插入件晶圓。在這類實施例中，堆疊結構500經單體化為個別堆疊結構。在其他實施例中，工件501為例如單體化晶粒，諸如插入件晶粒。在工件501為插入件晶圓或插入件晶粒的一些實施例中，工件501包括基底503及互連件，諸如基底503內的穿孔（through via；TV）505及線（未繪示）。在一些實施例中，基底503可使用與上文參看圖1A及圖1B所描述的基底105類似的材料及方法形成，且在本文中不重複描述。在一些實施例中，互連件可包括一或多種導電材料，諸如銅、銅合金、銀、金、鎢、鉭、鋁、其組合或其類似物。在一些實施例中，除互連件以外，工件501可不包括主動及被動裝置。
在一些實施例中，IC晶粒507及IC晶粒509各自可包括基底、基底上的一或多個主動及/或被動裝置以及基底及一或多個主動及/或被動裝置上方的互連件結構（未個別地展示）。在一些實施例中，IC晶粒507及IC晶粒509的基底可使用與上文參看圖1A及圖1B所描述的基底105類似的材料及方法形成，且在本文中不重複描述。在一些實施例中，IC晶粒507及509的一或多個主動及/或被動裝置可包含各種n型金屬氧化物半導體（n-type metal-oxide semiconductor；NMOS）及/或p型金屬氧化物半導體（p-type metal-oxide semiconductor；PMOS）裝置，諸如電晶體、電容器、電阻器、二極體、光電二極體、熔斷器及/或其類似者。
IC晶粒507及IC晶粒509的互連結構可包括多個介電層（諸如層間介電（inter-layer dielectric；ILD）層/金屬間介電層（inter-metal dielectric layer；IMD））及介電層內的互連件（諸如導電線及導通孔）。介電層可藉由本領域中已知的任何適合的方法（諸如旋塗式塗佈方法、化學氣相沈積、電漿增強式化學氣相沈積（plasma enhanced CVD；PECVD）、其組合或其類似方法），且由例如低K介電材料（諸如磷矽酸鹽玻璃（PSG）、硼磷矽玻璃（BPSG）、FSG、SiOx Cy 、旋塗式玻璃（Spin-On-Glass）、旋塗式聚合物（Spin-On-Polymer））、矽碳材料、其化合物、其複合物、其組合或其類似者形成。在一些實施例中，互連件可使用例如金屬鑲嵌製程（damascene process）、雙金屬鑲嵌製程（dual damascene process）、其組合或其類似者形成於介電層中。在一些實施例中，互連件可包括銅、銅合金、銀、金、鎢、鉭、鋁、其組合或其類似物。在一些實施例中，互連件可在形成於基底上的一或多個主動及/或被動裝置之間提供電連接。
進一步參看圖5，IC晶粒507及IC晶粒509各自可為記憶體晶粒、邏輯晶粒、3DIC晶粒、CPU、GPU、xPU、SoC晶粒、MEMS晶粒或其類似者。在所繪示實施例中，IC晶粒507及IC晶粒509具有不同高度。在其他實施例中，IC晶粒507及IC晶粒509可具有相同高度。在一些實施例中，IC晶粒507及IC晶粒509使用連接件511以機械方式及電氣方式貼合至工件501。在一些實施例中，連接件511可包括微凸塊、焊料凸塊、金屬柱凸塊、其他適合的結構、其組合或其類似者。在一些實施例中，各連接件511可包含包夾在兩個金屬柱凸塊5111 與5112 之間的焊接元件5113 ，如圖5中所示。在一些實施例中，金屬柱凸塊5111 及金屬柱凸塊5112 可包括金屬材料，諸如銅、鎢、鋁、銀、金、其組合或其類似物。在一些實施例中，焊接元件5113 可包括：諸如PbSn組成物的鉛類焊料；包含InSb、錫、銀以及銅（「SAC」）組成物的無鉛焊料；以及具有共同熔點且在電氣應用中形成導電焊料連接的其他共熔材料（eutectic material）。對於無鉛焊料，作為實例，可使用具有不同組成的SAC焊料，諸如SAC 105（Sn 98.5%、Ag 1.0%、Cu 0.5%）、SAC 305以及SAC 405。無鉛焊料亦包含SnCu化合物而不使用銀，以及包含SnAg化合物而不使用銅。
在一些實施例中，在將IC晶粒507及IC晶粒509接合至工件501之前，將金屬柱凸塊5111 形成於工件501的頂部表面上方，且將金屬柱凸塊5112 形成於IC晶粒507及IC晶粒509的底部表面上方。隨後，在接合製程之前將諸如焊錫膏的焊接材料塗覆於金屬柱凸塊5111 及金屬柱凸塊5112 中的一者或兩者上。之後，舉例而言，金屬柱凸塊5111 及金屬柱凸塊5112 使用回焊製程藉由焊接材料接合在一起。焊接材料在金屬柱凸塊5111 與金屬柱凸塊5112 之間形成焊接元件5113 ，如圖5中所示。在一些實施例中，形成金屬柱凸塊5111 及金屬柱凸塊5112 的方法可包括：形成金屬晶種層；在金屬晶種層上方形成犧牲材料（諸如光阻材料）；圖案化犧牲材料以形成開口；使用電化學電鍍製程、無電極電鍍製程、原子層沈積、物理氣相沈積、其組合或其類似者將金屬材料沈積於開口中，以形成金屬柱凸塊5111 及金屬柱凸塊5112 ；移除犧牲層；以及移除晶種層的暴露部分。在一些實施例中，在移除犧牲層之前，使用蒸鍍、電化學電鍍製程、無電極電鍍製程、印刷、焊料轉移、其組合或其類似者將焊接材料形成於開口中的金屬材料上方。
在一些實施例中，形成底填充層513以包圍並保護連接件511。在一些實施例中，底填充層513與連接件511直接接觸。在一些實施例中，藉由毛細作用來分配液體底填充材料且將其固化以形成底填充層513。在一些實施例中，底填充層513包含其中分散有填料（filler）的環氧類樹脂。填料可包含纖維、顆粒、其他適合的元件、其組合或其類似者。
參看圖6，擬晶粒401貼合至IC晶粒507。在一些實施例中，使用黏著劑601將擬晶粒401貼合至IC晶粒507。在這類實施例中，黏著劑601形成於不含絕緣材料201的擬晶粒401之前表面（面對IC晶粒507的表面）的部分上。在其他實施例中，可使用直接接合方法或其他適合的接合方法將擬晶粒401貼合至IC晶粒507。
參看圖7，包封體701形成於工件501上方以及IC晶粒507及IC晶粒509以及擬晶粒401周圍。在一些實施例中，包封體701可包括其中分散有填料的模製化合物，諸如環氧樹脂、樹脂、可模製聚合物、其組合或其類似者。模製化合物可在實質上為液體時塗覆，且隨後可通過化學反應固化。填料可包含絕緣纖維、絕緣顆粒、其他適合的元件、其組合或其類似者。在一些實施例中，分散於包封體701中的填料的大小及/或密度大於分散於底填充層513中的填料的大小及/或密度。在其他實施例中，包封體701可為以膠或展性固體塗覆且能夠安置於IC晶粒507及IC晶粒509周圍及之間以及IC晶粒509與擬晶粒401之間的經紫外線或熱固化聚合物。在其他實施例中，包封體701可包括介電材料，諸如氧化物。在一些實施例中，可對包封體701執行平坦化製程以移除包封體701的多餘部分，以使得在平坦化製程之後包封體701的最頂部表面與擬晶粒401的背側表面401b實質上水平。在一些實施例中，平坦化製程可包括CMP製程、蝕刻製程、研磨、其組合或其類似製程。
參看圖8，工件501的背側501b經薄化以暴露穿孔505，且導電連接件801形成於與各別穿孔505電接觸的工件501的背側501b上。在一些實施例中，工件501的背側501b可使用化學機械平坦化（CMP）製程、蝕刻製程、研磨、其組合或其類似製程來薄化。在一些實施例中，連接件801可為受控塌陷晶片連接（controlled collapse chip connection；C4）凸塊、球柵陣列封裝（ball grid array；BGA）凸塊或其類似者。在一些實施例中，連接件801可構成與上文參看圖5所描述的焊接元件5113 類似的焊接材料，且在本文中不重複描述。
進一步參看圖8，在形成連接件801之後，對擬晶粒401及包封體701執行另一平坦化製程，以暴露安置於擬晶粒401的開口109（參看圖1A及圖1B）中的絕緣材料201。在一些實施例中，平坦化製程亦可移除IC晶粒509的一部分。在一些實施例中，在平坦化製程之後，擬晶粒401的背側表面401b與包封體701的頂部表面及IC晶粒509的頂部表面實質上水平。在一些實施例中，平坦化製程可包括CMP製程、蝕刻製程、研磨、其組合或其類似製程。在一些實施例中，安置於擬晶粒401的開口109（參看圖1A及圖1B）中的絕緣材料201在平坦化製程期間保護IC晶粒507免受污染。在工件501為晶圓的一些實施例中，可對堆疊結構500執行單體化製程803以將堆疊結構500分成個別堆疊結構800。單體化製程803可包括鋸割、蝕刻、雷射剝蝕、其組合或其類似者。
參看圖9，使用連接件801將堆疊結構800以機械方式及電氣方式貼合至工件901。在連接件801由焊接材料形成的一些實施例中，可執行回焊製程以將堆疊結構800接合至工件901。在一些實施例中，工件901可包括封裝基底、印刷電路板（printed circuit board；PCB）、陶瓷基底或其類似者。在一些實施例中，工件901可包括工件901中及/或上的互連件（諸如導電線及導通孔）。在一些實施例中，連接件903形成於工件901上與堆疊結構800相反的側面上。在一些實施例中，連接件903可類似於連接件801，可使用與上文參看圖8所描述的材料及方法類似的材料及方法形成，且在本文中不重複描述。在一些實施例中，形成底填充層905以包圍並保護連接件801。在一些實施例中，底填充層905可使用與上文參看圖5所描述的底填充層513類似的材料及方法形成，且在本文中不重複描述。
進一步參看圖9，在將堆疊結構800貼合連接至工件901之後，自擬晶粒401的開口109（參看圖1A及圖1B）移除絕緣材料201（參看圖8）。在一些實施例中，使用雷射鑽孔製程907移除絕緣材料201。在其他實施例中，舉例而言，可使用其他適合的移除製程（諸如蝕刻製程）移除絕緣材料201。在移除絕緣材料201之後，擬晶粒401分成內部區域909及環形區域911。
參看圖10，移除擬晶粒401的內部區域909以暴露擬晶粒401的環形區域911中的開口1001。在一些實施例中，使用取放型（pick-and-place）設備移除擬晶粒401的內部區域909。在其他實施例中，可手動或使用其他適合的移除方法移除擬晶粒401的內部區域909。在一些實施例中，導電層301可藉由在絕緣材料201與IC晶粒507之間充當緩衝物及藉由防止絕緣材料201與IC晶粒507之間的接合來輔助內部區域909的移除製程。在一些實施例中，開口1001暴露IC晶粒507的頂部表面。在一些實施例中，開口1001的寬度W3在約1毫米與約30毫米之間。在其他實施例中，寬度W3可大於約30毫米。
參看圖11，功能組件1101置放於環形區域911的開口1001中。在一些實施例中，功能組件1101可為類似於IC晶粒507及IC晶粒509的IC晶粒。在這類實施例中，可使用連接件1103將功能組件1101機械連接及電連接至IC晶粒507。在一些實施例中，連接件1103可使用與上文參看圖5所描述的連接件511類似的材料及方法形成，且在本文中不重複描述。在其他實施例中，可使用直接接合方法（諸如混合接合方法或其類似者）將功能組件1101機械連接及電連接至IC晶粒507。在將所得封裝用於光子學應用中的一些實施例中，功能組件1101可包括光子纖維模組、雷射模組封裝（laser module package；LaMP）、耦合器或其類似者。在這類實施例中，功能組件1101可僅以機械方式貼合至IC晶粒509。
圖12A、圖12B以及圖13至圖15繪示根據一些實施例的在製造擬晶粒（諸如圖15中所繪示的擬晶粒1501）期間的各種處理步驟的俯視圖及截面視圖。圖12A繪示晶圓1200的俯視圖，而圖12B及圖13至圖15繪示沿圖12A中的線BB'的截面視圖。圖12A、圖12B以及圖13至圖15中所繪示的實施例類似於圖1A、圖1B以及圖2至圖4中所繪示的實施例，其中相同特徵使用相同元件符號標記，且本文中不重複相同特徵及製程步驟的詳細描述。在圖12A、圖12B以及圖13至圖15中所繪示的實施例中，對絕緣材料201執行的圖案化製程亦自開口109（參看圖12A及圖12B）移除絕緣材料201的部分，以形成如圖13中所示的凹槽1301。因此，在分割晶圓1200之後形成的擬晶粒1501包括凹槽1301及沿凹槽1301的底部及側壁延伸的導電層301，如圖15中所示。在一些實施例中，凹槽1301的深度D3在約10微米與約50微米之間。
圖16A、圖16B以及圖17至圖24繪示根據一些實施例的在製造積體電路封裝期間的各種處理步驟的俯視圖及截面視圖。圖16A繪示俯視圖，而圖16B及圖17至圖24繪示沿圖16A中的線BB'的截面視圖。首先參看圖16A及圖16B，繪示工件1600。在一些實施例中，工件1600為晶圓，諸如插入件晶圓。在其他實施例中，工件1600為單體化晶粒，諸如插入件晶粒。在一些實施例中，工件1600包括基底1601，所述基底1601可使用與上文參看圖5所描述的工件501的基底503類似的材料及方法形成，且在本文中不重複描述。工件1600包括互連件，諸如基底1601內的穿孔 1603及線（未圖示）。在一些實施例中，工件1600的互連件可使用與上文參看圖5所描述的工件501的互連件類似的材料及方法形成，且在本文中不重複描述。工件1600更包括連接件1605及插塞1607。在一些實施例中，插塞1607在如圖16A中所示的平面視圖中具有環狀。在一些實施例中，擬晶粒1501（參看圖15）的插塞1607及凹槽1301具有類似環狀，以使得插塞1607可在後續製程中插入凹槽1301中。因此，凹槽1301的深度D3（參看圖13）可大於或等於插塞1607的高度，且凹槽1301的寬度W2（參看圖12B）可大於或等於插塞1607的寬度。
在一些實施例中，連接件1605及插塞1607可在同一製程中同時形成。在其他實施例中，連接件1605及插塞1607可在不同製程中在不同時間分別地形成。在一些實施例中，連接件1605包括金屬柱凸塊16051 及金屬柱凸塊16051 上方的焊接元件16052 。在一些實施例中，插塞1607包括金屬底座16071 及金屬底座16071 上方的焊接元件16072 。在一些實施例中，金屬柱凸塊16051 及金屬底座16071 可使用與上文參看圖5所描述的金屬柱凸塊5111 及金屬柱凸塊5112 類似的材料及方法形成，且在本文中不重複描述。在一些實施例中，焊接元件16052 及焊接元件16072 可使用與上文參看圖5所描述的焊接元件5113 類似的材料及方法形成，且在本文中不重複描述。在一些實施例中，金屬柱凸塊16051 及金屬底座16071 可包括相同材料。在其他實施例中，金屬柱凸塊16051 及金屬底座16071 可包括不同材料。在一些實施例中，焊接元件16052 及焊接元件16072 可包括相同材料。在其他實施例中，焊接元件16052 及焊接元件16072 可包括不同材料。在一些實施例中，插塞1607可不電連接至工件1600內或上的其他導電元件。在其他實施例中，插塞1607可包括絕緣材料，諸如聚苯并噁唑（PBO）、聚醯亞胺（PI）、苯并環丁烯（BCB）、其組合或其類似者，且可使用適合的圖案化製程形成。
參看圖17，使用連接件1605將IC晶粒1701以機械方式及電氣方式貼合至工件1600以開始形成堆疊結構1700。在一些實施例中，IC晶粒1701可使用與上文參看圖5所描述的IC晶粒507及IC晶粒509類似的材料及方法形成，且在本文中不重複描述。
參看圖18，使用黏著劑1801將擬晶粒1501貼合至工件1600。在一些實施例中，插塞1607延伸至擬晶粒1501的凹槽1301（參看圖15）中且將擬晶粒1501固定於工件1600上的所需位置中。在其他實施例中，可使用直接接合方法或其他適合的接合方法將擬晶粒1501貼合至工件1600。
參看圖19，底填充層1901形成於連接件1605及IC晶粒1701周圍。底填充層1903亦形成於插塞1607及擬晶粒1501周圍。在一些實施例中，底填充層1901及底填充層1903可使用與上文參看圖5所描述的底填充層513類似的材料及方法形成，且在本文中不重複描述。在一些實施例中，底填充層1901及底填充層1903可包括相同材料。在其他實施例中，底填充層1901及底填充層1903可包括不同材料。在其他實施例中，底填充層1903可省略。
在一些實施例中，包封體1905形成於工件1600上方以及IC晶粒1701及擬晶粒1501周圍。在一些實施例中，包封體1905可使用與上文參看圖7所描述的包封體701類似的材料及方法形成，且在本文中不重複描述。在一些實施例中，可對包封體1905執行平坦化製程以移除包封體1905的多餘部分，以使得在平坦化製程之後包封體1905的最頂部表面與擬晶粒1501的背側表面1501b及IC晶粒1701的最頂部表面實質上水平。在一些實施例中，平坦化製程可包括CMP製程、蝕刻製程、研磨、其組合或其類似製程。在IC晶粒1701的高度大於擬晶粒1501的高度的一些實施例中，平坦化製程亦可移除IC晶粒1701的一部分。
參看圖20，工件1600的背側1600b經薄化以暴露穿孔1603，且連接件2001形成於工件1600的背側1600b上與各別穿孔1603電接觸。在一些實施例中，工件1600的背側1600b可使用CMP製程、蝕刻製程、研磨、其組合或其類似製程來薄化。在一些實施例中，連接件2001可類似於連接件801，可使用與上文參看圖8所描述的材料及方法類似的材料及方法形成，且在本文中不重複描述。
進一步參看圖20，在形成連接件2001之後，對IC晶粒1701、擬晶粒1501以及包封體1905執行另一平坦化製程，以暴露安置於擬晶粒1501的開口109（參看圖12A及圖12B）中的絕緣材料201。在一些實施例中，在平坦化製程之後，擬晶粒1501的背側表面1501b與包封體1905的最頂部表面及IC晶粒1701的最頂部表面實質上水平。在一些實施例中，平坦化製程可包括CMP製程、蝕刻製程、研磨、其組合或其類似製程。在一些實施例中，安置於擬晶粒1501的開口109（參看圖12A及圖12B）中的絕緣材料201在平坦化製程期間保護工件1600免受污染。在工件1600為晶圓的一些實施例中，可執行單體化製程2003以將堆疊結構1700分成個別堆疊結構2000。單體化製程2003可包括鋸割、蝕刻、雷射剝蝕、其組合或其類似者。
參看圖21，使用連接件2001將堆疊結構2000以機械方式及電氣方式貼合至工件2101。在連接件2001由焊接材料形成的一些實施例中，可執行回焊製程以將堆疊結構2000接合至工件2101。在一些實施例中，工件2101可包括封裝基底、印刷電路板、陶瓷基底或其類似者。在一些實施例中，工件2101可包括工件2101中及/或上的互連件（諸如導電線及導通孔）。在一些實施例中，連接件2103形成於工件2101上與堆疊結構2000相反的側面上。在一些實施例中，連接件2103可類似於連接件903，可使用與上文參看圖9所描述的材料及方法類似的材料及方法形成，且在本文中不重複描述。在一些實施例中，底填充層2107形成於連接件2001周圍。在一些實施例中，底填充層2107可使用與上文參看圖5所描述的底填充層513類似的材料及方法形成，且在本文中不重複描述。在一些實施例中，可將環形結構2105貼合至工件2101上與堆疊結構2000相同的側面上，以使得堆疊結構2000安置於環形結構2105的開口內。在一些實施例中，環形結構2105可防止工件2101及所貼合的堆疊結構2000翹曲。在一些實施例中，環形結構2105可包括絕緣材料、不鏽鋼、黃銅、銅、其組合或其類似者。在其他實施例中，環形結構2105可省略。
參看圖22，在將堆疊結構2000貼合至工件2101之後，自擬晶粒1501的開口109（參看圖12A及圖12B）移除絕緣材料201（參看圖21）。在一些實施例中，使用雷射鑽孔製程2201移除絕緣材料201。在其他實施例中，舉例而言，可使用其他適合的移除製程（諸如蝕刻製程）移除絕緣材料201。在移除絕緣材料201之後，擬晶粒1501分成內部區域2203及環形區域2205。在一些實施例中，插塞1607可在移除絕緣材料201期間充當終止層。
參看圖23，移除擬晶粒1501（參看圖22）的內部區域2203以暴露擬晶粒1501的環形區域2205中的開口2301。在一些實施例中，使用取放型設備移除擬晶粒1501的內部區域2203。在其他實施例中，可手動或使用其他適合的移除方法移除擬晶粒1501的內部區域2203。在一些實施例中，導電層301可藉由在絕緣材料201與工件1600之間充當緩衝物及藉由防止絕緣材料201與工件1600之間的接合來輔助內部區域2203的移除製程。在一些實施例中，開口2301暴露工件1600的頂部表面。在一些實施例中，開口2301的寬度W4在約1毫米與約30毫米之間。在其他實施例中，寬度W4可大於約30毫米。
參看圖24，功能組件2401置放於開口2301中。在一些實施例中，功能組件2401可為類似於IC晶粒1701的IC晶粒。在這類實施例中，可使用連接件2403將功能組件2401以機械方式及電氣方式貼合至工件1600。在一些實施例中，連接件2403可使用與上文參看圖5所描述的連接件511類似的材料及方法形成，且在本文中不重複描述。在其他實施例中，可使用直接接合方法（諸如混合接合方法或其類似者）將功能組件2401以機械方式及電氣方式貼合至工件1600。在將所得封裝用於光子學應用中的一些實施例中，功能組件2401可包括光子纖維模組、LaMP、耦合器或其類似者。在這類實施例中，功能組件2401可僅以機械方式貼合至工件1600。
圖25繪示根據一些實施例的積體電路封裝2500的截面視圖。在一些實施例中，IC封裝2500可使用類似於上文參看圖1A、圖1B以及圖2至圖11所描述之方法的方法形成，且在本文中不重複描述。IC封裝2500包括工件2501。在一些實施例中，工件2501可類似於上文參看圖9所描述的工件901，且在本文中不重複描述。連接件2503形成於工件2501的底部表面上。在一些實施例中，連接件2503可類似於上文參看圖9所描述的連接件903，且在本文中不重複描述。將表面黏著裝置2505（Surface mount device；SMD）貼合至工件的頂部表面及/或工件的底部表面。使用連接件2507將工件2509貼合至工件2501。在一些實施例中，工件2509可類似於上文參看圖5所描述的工件501，且在本文中不重複描述。在一些實施例中，連接件2507可類似於上文參看圖8所描述的連接件801，且在本文中不重複描述。底填充層2515形成於連接件2507周圍。在一些實施例中，底填充層2515類似於上文參看圖9所描述的底填充層905，且在本文中不重複描述。使用連接件2511將IC晶粒2519、IC晶粒2521以及IC晶粒2523貼合至工件2509，且底填充層2513形成於連接件2511周圍。在一些實施例中，IC晶粒2519、IC晶粒2521以及IC晶粒2523類似於上文參看圖5所描述的IC晶粒507及IC晶粒509，且在本文中不重複描述。在一些實施例中，連接件2511類似於上文參看圖5所描述的連接件511，且在本文中不重複描述。在一些實施例中，底填充層2513可類似於上文參看圖5所描述的底填充層513，且在本文中不重複描述。IC晶粒2519及IC晶粒2523的最頂部表面高於IC晶粒2521的最頂部表面。使用黏著劑2527將環形結構2525貼合至IC晶粒2521。在一些實施例中，環形結構2525可使用類似於上文參看圖1A、圖1B以及圖2至圖11所描述之方法的方法形成，且在本文中不重複描述。包封體2517形成於IC晶粒2519、IC晶粒2521以及IC晶粒2523及環形結構2525周圍，使得環形結構2525的開口2529不含包封體2517。在一些實施例中，包封體2517類似於上文參看圖7所描述的包封體701，且在本文中不重複描述。IC晶粒2519及IC晶粒2523的最頂部表面以及環形結構2525的最頂部表面與包封體2517的最頂部表面實質上水平或共面。
圖26繪示根據一些實施例的積體電路封裝2600的截面視圖。在一些實施例中，IC封裝2600可使用類似於上文參看圖1A、圖1B以及圖2至圖11所描述之方法的方法形成，且在本文中不重複描述。為了突顯IC封裝2600與IC封裝2500（參看圖25）之間的差異，這些封裝的共同特徵藉由相同元件符號標記且在本文中不重複其描述。IC封裝2600類似於IC封裝2500（參看圖25），區別在於IC封裝2600包括IC晶粒2601、IC晶粒2603以及IC晶粒2605，以使得IC晶粒2601的最頂部表面與IC晶粒2603的最頂部表面、IC晶粒2603的最頂部表面以及包封體2517的最頂部表面實質上水平或共面。此外，IC晶粒2601及IC晶粒2605包括分別包封於包封體2607及包封體2609中的各別晶粒堆疊。在一些實施例中，IC晶粒2601及IC晶粒2605的晶粒堆疊包括彼此接合的多個晶粒。在一些實施例中，多個晶粒可使用直接接合方法（諸如混合接合方法或其類似者）彼此接合。在其他實施例中，多個晶粒可使用連接件彼此接合。在所繪示的實施例中，使用黏著劑2613將環形結構2611貼合至IC晶粒2601及IC晶粒2605，以使得環形結構2611的開口2615暴露IC晶粒2603的最頂部表面。在一些實施例中，環形結構2611可使用類似於上文參看圖1A、圖1B以及圖2至圖11所描述之方法的方法形成，且在本文中不重複描述。
圖27繪示根據一些實施例的積體電路封裝2700的截面視圖。在一些實施例中，IC封裝2700可使用類似於上文參看圖12A、圖12B、圖13至圖15、圖16A、圖16B以及圖17至圖24所描述之方法的方法形成，且在本文中不重複描述。為了突顯IC封裝2700與IC封裝2500（參看圖25）之間的差異，這些封裝的共同特徵藉由相同元件符號標記且在本文中不重複其描述。IC封裝2700類似於IC封裝2500（參看圖25），區別在於IC封裝2700包括IC晶粒2701及IC晶粒2703以及環形結構2705，以使得IC晶粒2701的最頂部表面與IC晶粒2703的最頂部表面、環形結構2705的最頂部表面以及包封體2517的最頂部表面實質上水平或共面。在所繪示的實施例中，使用黏著劑2707將環形結構2705貼合至工件2509，以使得環形結構2705的開口2709暴露工件2509的最頂部表面。在一些實施例中，環形結構2705可使用類似於上文參看圖12A、圖12B、圖13至圖15、圖16A、圖16B以及圖17至圖24所描述之方法的方法形成，且在本文中不重複描述。
圖28繪示根據一些實施例的積體電路封裝2800的截面視圖。在一些實施例中，IC封裝2800可藉由將功能組件2801置放於IC封裝2700（參看圖27）的環形結構2705的開口2709中且使用連接件2803將功能組件2801接合至工件2509而形成。隨後，底填充層2805形成於連接件2803周圍。在一些實施例中，底填充層2805可類似於上文參看圖5所描述的底填充層513，且在本文中不重複描述。在一些實施例中，功能組件2801可類似於上文參看圖24所描述的功能組件2401，且在本文中不重複描述。在所繪示的實施例中，功能組件2801的最頂部表面高於環形結構2705的最頂部表面。在其他實施例中，功能組件2801的最頂部表面可低於環形結構2705的最頂部表面。
圖29繪示根據一些實施例的積體電路封裝2900的截面視圖。在一些實施例中，IC封裝2900可使用類似於上文參看圖12A、圖12B、圖13至圖15、圖16A、圖16B及圖17至圖24所描述之方法的方法形成，且在本文中不重複描述。為了突顯IC封裝2900與IC封裝2700（參看圖27）之間的差異，這些封裝的共同特徵藉由相同元件符號標記且在本文中不重複其描述。IC封裝2900類似於IC封裝2700（參看圖27），區別在於插塞2901保留開口2709。在一些實施例中，插塞2901可使用與上文參看圖16A及圖16B所描述的插塞1607類似的材料及方法形成，且在本文中不重複描述。
圖30繪示根據一些實施例的積體電路封裝3000的截面視圖。在一些實施例中，IC封裝3000可使用類似於上文參看圖12A、圖12B、圖13至圖15、圖16A、圖16B以及圖17至圖24所描述之方法的方法形成，且在本文中不重複描述。為了突顯IC封裝3000與IC封裝2700（參看圖27）之間的差異，這些封裝的共同特徵藉由相同元件符號標記且在本文中不重複其描述。IC封裝3000類似於IC封裝2700（參看圖27），區別在於完全移除擬晶粒（諸如，圖4及圖15中分別繪示的擬晶粒401及擬晶粒1501）。在一些實施例中，可使用任何適合的移除製程移除擬晶粒以形成開口3001。開口3001暴露工件2509的頂部表面。
圖31繪示根據一些實施例的積體電路封裝3100的截面視圖。在一些實施例中，IC封裝3100可使用類似於上文參看圖12A、圖12B、圖13至圖15、圖16A、圖16B以及圖17至圖24所描述之方法的方法形成，且在本文中不重複描述。為了突顯IC封裝3100與IC封裝3000（參看圖30）之間的差異，這些封裝的共同特徵藉由相同元件符號標記且在本文中不重複其描述。IC封裝3100類似於IC封裝3000（參看圖30），區別在於，除了完全移除擬晶粒（諸如，圖4及圖15中分別繪示的擬晶粒401及擬晶粒1501）以外，亦移除包圍擬晶粒的底填充層2513及包封體2517的部分。在一些實施例中，可使用任何適合的移除製程移除擬晶粒以及底填充層2513及包封體2517的部分以形成開口3101。開口3101暴露工件2509的頂部表面。
圖32是繪示根據一些實施例的形成擬晶粒的方法3200的流程圖。方法3200開始於步驟3201，其中基底（諸如，圖1A及圖1B中所繪示的基底105）經圖案化以如上文參看圖1A及圖1B所描述在基底中形成開口（諸如，圖1A及圖1B中所繪示的開口109）。在步驟3203中，絕緣材料（諸如，圖2中所繪示的絕緣材料201）如上文參看圖2所描述沈積於開口中。在步驟3205中，導電材料（諸如，圖3中所繪示的導電層301）如上文參看圖3所描述沈積於基底上方。在步驟3207中，基底如上文參看圖4所描述經單體化成個別擬晶粒（諸如，圖4中所繪示的擬晶粒401）。
圖33是繪示根據一些實施例的形成積體電路封裝的方法3300的流程圖。方法3300開始於步驟3301，其中積體電路晶粒（諸如，圖5中所繪示的IC晶粒507）如上文參看圖5所描述貼合至基底（諸如，圖5中所繪示的工件501）。在步驟3303中，擬晶粒（諸如，圖6中所繪示的擬晶粒401）如上文參看圖6所描述貼合至積體電路晶粒。在步驟3305中，積體電路晶粒及擬晶粒如上文參看圖7所描述包封於包封體（諸如，圖6中所繪示的包封體701）中。在步驟3307中，移除擬晶粒的內部區域（諸如，圖10中所繪示的內部區域909），以使得擬晶粒的剩餘部分如上文參看圖8至圖10所描述形成環形結構（諸如，圖10中所繪示的環形區域911）。
圖34是繪示根據一些實施例的形成積體電路封裝的方法3400的流程圖。方法3400開始於步驟3401，其中積體電路晶粒（諸如，圖17中所繪示的IC晶粒1701）如上文參看圖17所描述貼合至基底（諸如，圖17中所繪示的工件1600）。在步驟3403中，擬晶粒（諸如，圖18中所繪示的擬晶粒1501）如上文參看圖18所描述貼合至基底。在步驟3405中，積體電路晶粒及擬晶粒如上文參看圖19所描述包封於包封體（諸如，圖19中所繪示的包封體1905）中。在步驟3407中，移除擬晶粒的內部區域（諸如，圖23中所繪示的內部區域2203），以使得擬晶粒的剩餘部分如上文參看圖20至圖23所描述形成環形結構（諸如，圖23中所繪示的環形區域2205）。
根據一實施例，方法包含：將積體電路晶粒貼合至第一基底；形成擬晶粒；將擬晶粒貼合至第一基底，與積體電路晶粒相鄰的；將包封體形成於第一基底上方且包圍擬晶粒及積體電路晶粒；使包封體、擬晶粒以及積體電路晶粒平坦化，包封體的最頂部表面與擬晶粒的最頂部表面及積體電路晶粒的最頂部表面實質上水平；以及移除擬晶粒的內部部分，擬晶粒的剩餘部分形成環形結構。在一實施例中，形成擬晶粒包含：使第二基底圖案化以在第二基底中形成開口，開口在平面視圖中具有環狀；以及將絕緣材料沈積於開口中。在一實施例中，使包封體、擬晶粒以及積體電路晶粒平坦化包含暴露絕緣材料。在一實施例中，移除擬晶粒的內部部分包含：移除絕緣材料，其中在移除絕緣材料之後，擬晶粒分成內部區域及周邊區域；以及自第一基底拾取內部區域，周邊區域形成環形結構。在一實施例中，移除絕緣材料包含使用雷射鑽孔方法移除絕緣材料。在一實施例中，擬晶粒使用黏著劑貼合至第一基底。在一實施例中，方法更包含：將功能組件置放於環形結構內；以及將功能組件接合至第一基底，其中功能組件及環形結構具有不同高度。
根據另一實施例，方法包含：將積體電路晶粒貼合至第一基底的第一側面；形成擬晶粒，擬晶粒包括擬晶粒內的第一環形結構；將擬晶粒貼合至第一基底的第一側面，與積體電路晶粒相鄰；將模製化合物形成於第一基底上方且包圍擬晶粒及積體電路晶粒，模製化合物的頂部表面與擬晶粒的最頂部表面、第一環形結構的最頂部表面以及積體電路晶粒的最頂部表面實質上水平；移除第一環形結構，擬晶粒在移除第一環形結構之後分成內部區域及周邊環形區域；使擬晶粒的內部區域自第一基底脫離，擬晶粒的周邊環形區域形成第二環形結構；將功能組件置放於第一基底的第一側面上第二環形結構內；以及將功能組件貼合至第一基底的第一側面。在一實施例中，形成擬晶粒包含：使第二基底圖案化以在第二基底中形成開口，開口在平面視圖中具有環狀；以及將絕緣材料沈積於開口中以形成第一環形結構。在一實施例中，移除第一環形結構包含執行雷射鑽孔製程。在一實施例中，擬晶粒使用黏著劑貼合至第一基底的第一側面。在一實施例中，功能組件及第二環形結構具有不同高度。在一實施例中，方法更包含在第一基底的第二側面上形成多個連接件，第一基底的第二側面與第一基底的第一側面相對。在一實施例中，第一基底包括插入件。
根據又一實施例，封裝包含：基底；接合至基底的第一側面的第一積體電路晶粒；接合至基底的第一側面、與第一積體電路晶粒相鄰的環形結構；基底上方的且包圍環形結構及第一積體電路晶粒的包封體，包封體的最頂部表面與環形結構的最頂部表面及第一積體電路晶粒的最頂部表面水平；以及環形結構內的功能組件，且功能組件接合至基底的第一側面。在一實施例中，封裝更包含置於基底的第一側面與環形結構之間的黏著劑。在一實施例中，封裝更包含基底的第二側面上的多個連接件，基底的第二側面與基底的第一側面相對。在一實施例中，基底包括插入件。在一實施例中，功能組件包括第二積體電路晶粒。在一實施例中，功能組件及環形結構具有不同高度。
亦可包含其他特徵及製程。舉例而言，可包含測試結構以輔助對3D封裝或3DIC裝置的驗證測試。測試結構可包含例如形成於重佈層中或基底上的測試墊，從而允許測試3D封裝或3DIC、探測器及/或探測卡的使用及其類似者。驗證測試可對中間結構以及最終結構執行。另外，本文中所揭露的結構及方法可結合併有對已知良好晶粒的中間驗證的測試方法使用，以提高良率及降低成本。
前文概述若干實施例的特徵以使得本領域的技術人員可更佳地理解本揭露的態樣。本領域的技術人員應理解，其可易於使用本揭露作為設計或修改用於實現本文中所引入的實施例的相同目的及/或達成相同優點的其他方法及結構的基礎。本領域的技術人員亦應認識到，這類等效構造並不背離本揭露的精神及範疇，且本領域的技術人員可在不背離本揭露的精神及範疇的情況下在本文中作出改變、替代及更改。
100、1200‧‧‧晶圓
101‧‧‧晶粒區域
103‧‧‧切割道
105、503、1601‧‧‧基底
107、109、1001、2301、2529、2615、2709、3001、3101‧‧‧開口
201‧‧‧絕緣材料
301‧‧‧導電層
305、405‧‧‧SAC
401、1501‧‧‧擬晶粒
401b‧‧‧背側表面
500、800、1700、2000‧‧‧堆疊結構
501、901、1600、2101、2501、2509‧‧‧工件
501b、1600b‧‧‧背側
505、1603‧‧‧穿孔（TV）
507、509、1701、2519、2521、2523、2601、2603、2605、2701、2703‧‧‧積體電路（IC）晶粒
511、801、903、1103、1605、2001、2103、2403、2503、2507、2511、2803‧‧‧連接件
5111、5112、16051‧‧‧金屬柱凸塊
5113、16052、16072‧‧‧焊接元件
513、905、1901、1903、2107、2513、2515、2805‧‧‧底填充層
601、1801、2527、2613、2707‧‧‧黏著劑
701、1905、2517、2607、2609‧‧‧包封體
803、2003‧‧‧單體化製程
907、2201‧‧‧雷射鑽孔製程
909、2203‧‧‧內部區域
911、2205、2525‧‧‧環形區域
1101、2401、2801‧‧‧功能組件
1301‧‧‧凹槽
1607、2901‧‧‧插塞
16071‧‧‧金屬底座
2105、2525、2611、2705‧‧‧環形結構
2500、2600、2700、2800、2900、3000、3100‧‧‧積體電路（IC）封裝
2505‧‧‧表面黏著裝置
3200、3300、3400‧‧‧方法
3201、3203、3205、3207、3301、3303、3305、3307、3401、3403、3405、3407‧‧‧步驟
D1、D2、D3‧‧‧深度
T1‧‧‧厚度
W1、W2、W3、W4‧‧‧寬度
結合附圖閱讀，根據以下詳細描述最佳地理解本揭露的態樣。應注意，根據業界中的標準慣例，各種特徵未按比例繪製。事實上，可出於論述清楚起見而任意地增大或減小各種特徵的尺寸。 圖1A、圖1B以及圖2至圖4繪示根據一些實施例的在製造擬晶粒期間的各種處理步驟的俯視圖及截面視圖。 圖5至圖11繪示根據一些實施例的在製造積體電路封裝期間的各種處理步驟的截面視圖。 圖12A、圖12B以及圖13至圖15繪示根據一些實施例的在製造擬晶粒期間的各種處理步驟的俯視圖及截面視圖。 圖16A、圖16B以及圖17至圖24繪示根據一些實施例的在製造積體電路封裝期間的各種處理步驟的俯視圖及截面視圖。 圖25繪示根據一些實施例的積體電路封裝的截面視圖。 圖26繪示根據一些實施例的積體電路封裝的截面視圖。 圖27繪示根據一些實施例的積體電路封裝的截面視圖。 圖28繪示根據一些實施例的積體電路封裝的截面視圖。 圖29繪示根據一些實施例的積體電路封裝的截面視圖。 圖30繪示根據一些實施例的積體電路封裝的截面視圖。 圖31繪示根據一些實施例的積體電路封裝的截面視圖。 圖32是繪示根據一些實施例的形成擬晶粒的方法的流程圖。 圖33是繪示根據一些實施例的形成積體電路封裝的方法的流程圖。 圖34是繪示根據一些實施例的形成積體電路封裝的方法的流程圖。

Claims (20)

  1. 一種方法，包括： 將積體電路晶粒貼合至第一基底； 形成擬晶粒； 將所述擬晶粒連接至所述第一基底，與所述積體電路晶粒相鄰； 使包封體形成於所述第一基底上方且包圍所述擬晶粒及所述積體電路晶粒； 使所述包封體、所述擬晶粒以及所述積體電路晶粒平坦化，所述包封體的最頂部表面與所述擬晶粒的最頂部表面及所述積體電路晶粒的最頂部表面實質上水平；以及 移除所述擬晶粒的內部部分，所述擬晶粒的剩餘部分形成環形結構。
  2. 如申請專利範圍第1項所述的方法，其中形成所述擬晶粒包括： 使第二基底圖案化以在所述第二基底中形成開口，所述開口在平面視圖中具有環狀；以及 將絕緣材料沈積於所述開口中。
  3. 如申請專利範圍第2項所述的方法，其中使所述包封體、所述擬晶粒以及所述積體電路晶粒平坦化包括暴露所述絕緣材料。
  4. 如申請專利範圍第2項所述的方法，其中移除所述擬晶粒的所述內部部分包括： 移除所述絕緣材料，其中所述擬晶粒在移除所述絕緣材料之後分成內部區域及周邊區域；以及 自所述第一基底拾取所述內部區域，所述周邊區域形成環形結構。
  5. 如申請專利範圍第4項所述的方法，其中移除所述絕緣材料包括使用雷射鑽孔方法移除所述絕緣材料。
  6. 如申請專利範圍第1項所述的方法，其中使用黏著劑將所述擬晶粒貼合至所述第一基底。
  7. 如申請專利範圍第1項所述的方法，更包括： 將功能組件置放於所述環形結構內；以及 將所述功能組件接合至所述第一基底，其中所述功能組件及所述環形結構具有不同高度。
  8. 一種方法，包括： 將積體電路晶粒貼合至第一基底的第一側面； 形成擬晶粒，所述擬晶粒包括所述擬晶粒內的第一環形結構； 將所述擬晶粒貼合至所述第一基底的所述第一側面，與所述積體電路晶粒相鄰； 使模製化合物形成於所述第一基底上方且包圍所述擬晶粒及所述積體電路晶粒，所述模製化合物的頂部表面與所述擬晶粒的最頂部表面、所述第一環形結構的最頂部表面以及所述積體電路晶粒的最頂部表面實質上水平； 移除所述第一環形結構，所述擬晶粒在移除所述第一環形結構之後分成內部區域及周邊環形區域； 使所述擬晶粒的所述內部區域自所述第一基底脫離，所述擬晶粒的所述周邊環形區域形成第二環形結構； 將功能組件置放於所述第一基底的所述第一側面上且於所述第二環形結構內；以及 將所述功能組件貼合至所述第一基底的所述第一側面。
  9. 如申請專利範圍第8項所述的方法，其中形成所述擬晶粒包括： 使第二基底圖案化以在所述第二基底中形成開口，所述開口在平面視圖中具有環狀；以及 將絕緣材料沈積於所述開口中以形成所述第一環形結構。
  10. 如申請專利範圍第8項所述的方法，其中移除所述第一環形結構包括執行雷射鑽孔製程。
  11. 如申請專利範圍第8項所述的方法，其中使用黏著劑將所述擬晶粒貼合至所述第一基底的所述第一側面。
  12. 如申請專利範圍第8項所述的方法，其中所述功能組件及所述第二環形結構具有不同高度。
  13. 如申請專利範圍第8項所述的方法，更包括在所述第一基底的第二側面上形成多個連接件，所述第一基底的所述第二側面與所述第一基底的所述第一側面相對。
  14. 如申請專利範圍第8項所述的方法，其中所述第一基底包括插入件。
  15. 一種封裝，包括： 基底； 第一積體電路晶粒，接合至所述基底的第一側面； 環形結構，接合至所述基底的所述第一側面，與所述第一積體電路晶粒相鄰； 包封體，位於所述基底上方且包圍所述環形結構及所述第一積體電路晶粒，所述包封體的最頂部表面與所述環形結構的最頂部表面及所述第一積體電路晶粒的最頂部表面實質上水平；以及 功能組件，位於所述環形結構內且接合至所述基底的所述第一側面。
  16. 如申請專利範圍第15項所述的封裝，更包括置於所述基底的所述第一側面與所述環形結構之間的黏著劑。
  17. 如申請專利範圍第15項所述的封裝，更包括所述基底的第二側面上的多個連接件，所述基底的所述第二側面與所述基底的所述第一側面相對。
  18. 如申請專利範圍第15項所述的封裝，其中所述基底包括插入件。
  19. 如申請專利範圍第15項所述的封裝，其中所述功能組件包括第二積體電路晶粒。
  20. 如申請專利範圍第15項所述的封裝，其中所述功能組件以及所述環形結構具有不同高度。
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