JP5052130B2 - 三次元積層構造を持つ半導体装置及びその製造方法 - Google Patents
三次元積層構造を持つ半導体装置及びその製造方法 Download PDFInfo
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- JP5052130B2 JP5052130B2 JP2006514146A JP2006514146A JP5052130B2 JP 5052130 B2 JP5052130 B2 JP 5052130B2 JP 2006514146 A JP2006514146 A JP 2006514146A JP 2006514146 A JP2006514146 A JP 2006514146A JP 5052130 B2 JP5052130 B2 JP 5052130B2
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Description
mechanical system,MEMS)に使用されるマイクロデバイスのセルフ・アッセンブリ技術が開示されている。この技術は、疎水性(hydrophobicity)と毛管力(capillary force)を利用して単一基板の上に複数の微小電子部品を搭載する技術である。その基板は、疎水性のアルカンチオールを被覆した金製の結合部位(biding sites)を複数個持っている。組立(アッセンブリ)時には、基板表面に塗布された炭化水素オイルが、水中で疎水性の結合部位以外の部分を濡らす。次に、微小電子部品は水中に投入され、炭化水素オイルで濡れた結合部位上にそれぞれ集められる。ここで、電気化学的な方法を用いて特定の結合部位を不活性化することにより、微小電子部品は毛管力によって所望の結合部位に集められる。これらの工程を繰り返すことにより、単一基板上に微小電子部品の種々のバッチ(群)を連続して組み立てることが可能となる。組立完了後、電気メッキ(electroplating)を行うことにより、組み立てられた微小電子部品と基板との間の電気的接続が行われる。
栗野ら、「三次元構造を持つインテリジェント・イメージセンサ・チップ」、1999アイ・イー・ディー・エム テクニカル・ダイジェストp.36.4.1〜36.4.4、1999年(H. Kurino et al.," Intelligent Image Sensor Chip with Three Dimensional Structure", 1999 IEDM Technical Digest, pp. 36.4.1 - 36.4.4, 1999) 李ら、「高度並列画像処理チップ用の三次元集積技術の開発」、「日本応用物理学会誌」第39巻、p.2473〜2477、第1部4B、2000年4月、(K.Lee et al.," Development of Three-Dimensional Integration Technology for HighlyParallel Image-Processing Chip", Jpn. J. Appl. Phys. Vol. 39, pp. 2474 - 2477, April 2000) ションら、「マイクロデバイスの制御されたマルチバッチ・セルフ・アッセンブリ」、ジャーナル・オブ・マイクロエレクトロメカニカル・システムズ、第12巻、第2号、p.117〜127、2003年4月」(X. Xiong et al.," Controlled Multibatch Self-Assembly of Microdevices", Journal of Michroelectromechanical Systems, Vol. 12, No. 2, pp. 117-127, April 2003)
支持基板と、
底部から頂部まで所定の積層方向に順に積み重ねられ且つ電気的絶縁性の接着剤を用いて一体化された第1〜第n(nは2以上の整数)の回路層を含む積層構造であって、前記底部において前記支持基板上に固定されたものとを備え、
前記積層構造内で互いに隣接する前記回路層は、それら回路層の間に形成された複数の接続部を介して機械的及び電気的に相互接続されていると共に、前記接続部以外の部分では前記接着剤によって電気的に絶縁されており、
前記第1〜第nの回路層の各々は、少なくとも一つの半導体回路を含んで形成されており、
前記第1〜第nの回路層の少なくとも一つは、その中に含まれる前記半導体回路の持つ前記積層方向に直交する平面内における物理寸法が、当該平面内における当該回路層の物理寸法よりも小さく、当該半導体回路の側面が前記接着剤によって覆われている、というものである。
前記支持基板の一面の所定箇所に、少なくとも一つの第1半導体回路を複数の第1接続部を介して機械的に接続する工程と、
機械的に接続された前記第1半導体回路と前記支持基板の間に生じる隙間に、第1電気的絶縁性接着剤を充填して硬化させる工程と、
前記第1接着剤の充填・硬化が行われた前記第1半導体回路の前記支持基板とは反対側の面を研磨することによって、前記第1半導体回路を所望厚さに調整し、もって前記積層構造を形成する第1回路層を形成する工程と、
前記第1回路層の表面の所定箇所に、少なくとも一つの第2半導体回路を複数の第2接続部を介して機械的及び電気的に接続する工程と、
機械的及び電気的に接続された前記第2半導体回路と前記第1回路層の間に生じる隙間に、第2電気的絶縁性接着剤を充填して硬化させる工程と、
前記第2接着剤の充填・硬化が行われた前記第2半導体回路の前記支持基板とは反対側の面を研磨することによって、前記第2半導体回路を所定厚さに調整し、もって前記積層構造を形成する第2回路層を形成する工程とを含む、というものである。
11 支持基板
11a 支持基板の搭載面
12 接続部
13 半導体チップ
14 接着剤
15 接続部
16 半導体チップ
17 接着剤
18 接続部
19 半導体チップ
20 接着剤
21 接続部
22 半導体チップ
23 接着剤
24 絶縁層
25 導電性プラグ
26 外部回路接続用マイクロバンプ電極
27 ハンダボール
30A、30B、30C、30A'、30B'、30C'、30D 半導体装置
31 支持基板
32 絶縁層
33 配線
34 導電性プラグ
35、36 マイクロバンプ電極
37 半導体チップ
37A 半導体ウェーハ
38、38a 接着剤
38aa フィラー入り接着剤
38b 充填材
38bb フィラー入り接着剤
39 絶縁層
40 導電性プラグ
41、42 マイクロバンプ電極
43 半導体チップ
44 接着剤
45 絶縁層
46 導電性プラグ
47、48 マイクロバンプ電極
49 半導体チップ
50 接着剤
51、53、55 絶縁層
52、54、56 導電材(埋込配線)
57、57a、57b、58、59 ストッパ
60 外部回路接続用マイクロバンプ電極
61 絶縁層
71 配線層
72 絶縁層
80、81、82 反り防止用接着剤
90 反り印加装置
91、92 押圧部材
100 構造体
101、102 押し付け板
103 支持棒
104 基板
104' 基板片
105 半導体ウェハー
105' 半導体ウェハー片
106 積層体
111 チャンバー
112 接着剤用容器
113 接着剤
114 ヒーター
120 接合用金属
121 クランプ部材
121a 注入孔
122 閉じた空間
131、132、133 キャリア基板
151、153 絶縁層
152 配線層
154 導電性プラグ
160 MOS型トランジスタ
161 ソース・ドレイン領域
162 ゲート絶縁層
163 ゲート電極
171、173 絶縁層
172 配線層
174 導電性プラグ
R1、R2 接続部
C 半導体チップに形成された半導体集積回路(半導体固体回路群)
L1 第1半導体回路層
L2 第2半導体回路層
L3 第3半導体回路層
L4 第4半導体回路層
図1〜図3は、本発明に係る三次元積層構造を持つ半導体装置の製造方法の基本概念を示す断面図である。
次に、本発明の第1実施形態に係る三次元積層構造を持つ半導体装置の製造方法について、図4〜図6を参照しながら説明する。この製造方法は、上述した本発明の基本概念に基づくものであり、図1〜図3で使用した「接続部」が導電性接触子(導電性コンタクト)、すなわちマイクロバンプ電極により実現される。
図7〜図9は、本発明の第2実施形態に係る三次元積層構造を持つ半導体装置の製造方法を工程毎に示す断面図である。
図13は、本発明の第3実施形態に係る三次元積層構造を持つ半導体装置の製造方法を工程毎に示す図である。第3実施形態の方法は、上述した第1実施形態の方法(図4〜図6参照)の変形例に相当するものであり、接着剤の充填方法を変えた以外は第1実施形態の方法と同じである。よって、第1実施形態において説明したのと同じ構成要素には同じ符号を付してその詳細な説明を省略する。
図14〜図16は、それぞれ、本発明の第4〜第6の実施形態に係る三次元積層構造を持つ半導体装置の製造方法を示す図である。
図17は、本発明の第7実施形態に係る三次元積層構造を持つ半導体装置の製造方法を工程毎に示す概念図であり、図4に対応するものである。この実施形態は、図4〜図6に示した第1実施形態において、図4の接着剤38と同じ材料からなる電気的絶縁性接着剤38aの硬化層に重ねて充填材38bの層を形成したものであり、それ以外は第1実施形態の方法と同じである。
図18は、本発明の第8実施形態に係る三次元積層構造を持つ半導体装置の製造方法を工程毎に示す概念図であり、図4に対応するものである。この実施形態は、第1実施形態において、接着剤38の硬化層に代えてフィラー入り接着剤38aaの硬化層を形成したものであり、それ以外は第1実施形態の方法と同じである。
図19は、本発明の第9実施形態に係る三次元積層構造を持つ半導体装置の製造方法を工程毎に示す概念図であり、図4に対応するものである。この実施形態は、図18の第8実施形態において、フィラー入り接着剤38aaの硬化層に重ねてフィラー入り充填材38bbを形成したものであり、それ以外は第8実施形態と同じである。
図20は、本発明の第10実施形態に係る三次元積層構造を持つ半導体装置の製造方法を工程毎に示す概念図であり、図4に対応するものである。この実施形態は、図18の第8実施形態において、フィラー入り接着剤38aaの硬化層に重ねてフィラーなし充填材38bを形成したものであり、それ以外は第8実施形態と同じである。
図21は、本発明の第11実施形態に係る三次元積層構造を持つ半導体装置の製造方法を工程毎に示す概念図であり、図4に対応するものである。この実施形態は、図17の第7実施形態において、フィラーなし接着剤38aの硬化層に重ねてフィラー入り充填材38bbを形成したものであり、それ以外は第7実施形態の方法と同じである。
図22〜図23は、本発明の第12実施形態に係る三次元積層構造を持つ半導体装置の製造方法を工程毎に示す概念図である。この実施形態は、図4〜図6に示した第1実施形態において、第1半導体回路層L1と第2半導体回路層L2の間に、配線層71と絶縁層72を追加形成したものであり、それ以外は第1実施形態と同じである。
図24〜図25は、本発明の第13実施形態に係る三次元積層構造を持つ半導体装置の製造方法を工程毎に示す概念図であり、図5〜図6に対応するものである。この実施形態は、第2半導体回路層L2が、複数の半導体チップ43ではなく単一の半導体ウェーハ43Aにより形成される点を除いて、それ以外は第1実施形態の方法と同じである。
図26は、本発明の第14実施形態に係る三次元積層構造を持つ半導体装置の製造方法を工程毎に示す概念図であり、図4に対応するものである。この実施形態は、第1実施形態の方法において、支持基板31側の接合領域R1を省略したものに相当する。このように、チップ37の接合は、チップ37側の接合領域R2のみでも行うことができる。
上述した第1〜第14実施形態では、いずれも、接着剤の充填を室温における「噴霧法」(または「塗布法」)(これを第1例とする)によって行っているが、本発明は「噴霧法」(または「塗布法」)に限定されず、他の方法も使用可能である。それを以下に示す。
図29は、上記第1〜第14の実施形態に使用可能な接着剤の充填方法の第3例を示す。
図30は、上記第1〜第14の実施形態に使用可能な接着剤の充填方法の第4例を示す。
図31〜図33は、上記第1〜第14の実施形態に使用可能な接着剤の充填方法の第5例を示す。
次に、接着剤の硬化工程で生じ得る支持基板31の反りの防止方法について説明する。
図37は、上記第1〜第14の実施形態に使用可能な支持基板31の反りの防止方法の第2例を示す。
図38は、上記第1〜第14の実施形態に使用可能な支持基板31の反りの防止方法の第3例を示す。
図40は、上記第1〜第14の実施形態に使用可能な支持基板31の反りの防止方法の第4例を示す。
次に、半導体チップ取り付け方法の変形例について説明する。
図42は、上記第1〜第14の実施形態に使用可能な支持基板31への半導体チップの取り付け方法の第2変形例を示す。
上述した第1〜第14実施形態及びそれらの変形例は本発明を具体化した例を示すものであり、したがって本発明はこれらの実施形態や変形例に限定されるものではなく、本発明の趣旨を外れることなく種々の変形が可能であることは言うまでもない。
Claims (31)
- 支持基板と、
底部から頂部まで所定の積層方向に順に積み重ねられ且つ電気的絶縁性の接着剤を用いて一体化された第1〜第n(nは2以上の整数)の回路層を含む積層構造とを備え、
前記積層構造は、その底部に位置する前記第1回路層において前記支持基板上に固定されることで、前記支持基板によって支持され、
前記積層構造の頂部に位置する前記第n回路層は、前記第1〜第nの回路層のうちの少なくとも一つに電気的に接続された外部回路接続用の複数の電極を有し、
前記第1〜第nの回路層の各々は、少なくとも一つの半導体回路を含んでいると共に、前記半導体回路はその厚さ方向に貫通する埋込配線を有し、
前記第1〜第nの回路層の各々とそれに隣接する他の前記回路層との間の隙間には、少なくとも一方の前記回路層から突出形成された複数の導電性接触子が配置されていると共に、前記接着剤が充填されていて、前記第1〜第nの回路層の各々とそれに隣接する他の前記回路層は、前記導電性接触子によって機械的及び電気的に相互接続されていると共に、前記接着剤によって機械的に相互接続されており、
前記第1〜第nの回路層の間の電気的接続は、前記埋込配線と前記導電性接触子とを用いて実現されており、
前記第1〜第nの回路層の少なくとも一つは、その中に含まれる前記半導体回路の持つ前記積層方向に直交する平面内における物理寸法が、当該平面内における当該回路層の物理寸法よりも小さく、当該半導体回路の側面が前記接着剤によって覆われており、
前記第1〜第nの回路層の少なくとも一つは、当該回路層の一面とそれに隣接する他の前記回路層または前記支持基板の対向面との間に延在し、且つ、当該回路層の一面とそれに隣接する他の前記回路層または前記支持基板の対向面との距離を所望値に規定する剛性部材を有していることを特徴とする、三次元積層構造を持つ半導体装置。 - 前記剛性部材が、当該回路層とそれに隣接する他の前記回路層または前記支持基板とを接続する際に、当該回路層とそれに隣接する他の前記回路層または前記支持基板との距離を前記所望値に設定するストッパとして機能する請求項1に記載の半導体装置。
- 前記導電性接触子が、互いに隣接する二つの前記回路層の各々から突出形成されており、それら導電性接触子が相互接続されることで、互いに隣接する二つの前記回路層が機械的及び電気的に相互接続されている請求項1または2に記載の半導体装置。
- 前記導電性接触子が、互いに隣接する二つの前記回路層のいずれか一方から突出形成されており、それら導電性接触子が他方の前記回路層に接続されることで、互いに隣接する二つの前記回路層が機械的及び電気的に相互接続されている請求項1または2に記載の半導体装置。
- 前記積層構造の側壁の全面が前記接着剤で覆われている請求項1〜4のいずれか1項に記載の半導体装置。
- 前記第1〜第nの回路層の少なくとも一つに含まれる前記半導体回路が、前記積層構造の側壁を覆う前記接着剤から露出している請求項1〜4のいずれか1項に記載の半導体装置。
- 前記第1〜第nの回路層の少なくとも一つが、前記積層方向に直交する面内で所定位置に配置された複数の半導体回路を含んでいる請求項1〜6のいずれか1項に記載の半導体装置。
- 当該回路層内の複数の前記半導体回路が、配線層を介して電気的に相互接続されている請求項7に記載の半導体装置。
- 前記配線層が、当該回路層とそれに隣接する他の回路層との間に配置されている請求項8に記載の半導体装置。
- 前記第1〜第nの回路層の少なくとも一つに含まれる前記半導体回路が、少なくとも一つのダミーの半導体回路を含んでいる請求項1〜9のいずれか1項に記載の半導体装置。
- 前記支持基板が内部回路または配線を有しており、その内部回路または配線が前記第1〜第nの回路層の少なくとも一つと電気的に接続されている請求項1〜10のいずれか1項に記載の半導体装置。
- 前記接着剤がフィラーを含んでいる請求項1〜11のいずれか1項に記載の半導体装置。
- 前記第1〜第nの回路層の少なくとも一つに含まれる前記半導体回路が、冗長構成を有している請求項1〜12のいずれか1項に記載の半導体装置。
- 支持基板と、
底部から頂部まで所定の積層方向に順に積み重ねられ且つ電気的絶縁性の接着剤を用いて一体化された第1〜第n(nは2以上の整数)の回路層を含む積層構造とを備え、
前記積層構造は、その底部に位置する前記第1回路層において前記支持基板上に固定され、
前記積層構造の頂部に位置する前記第n回路層は、前記第1〜第nの回路層のうちの少なくとも一つに電気的に接続された外部回路接続用の複数の電極を有し、
前記第1〜第nの回路層の各々は、少なくとも一つの半導体回路を含んでいると共に、前記半導体回路はその厚さ方向に貫通する埋込配線を有し、
前記第1〜第nの回路層の各々とそれに隣接する他の前記回路層との間の隙間には、少なくとも一方の前記回路層から突出形成された複数の導電性接触子が配置されていると共に、前記接着剤が充填されていて、前記第1〜第nの回路層の各々とそれに隣接する他の前記回路層は、前記導電性接触子によって機械的及び電気的に相互接続されていると共に、前記接着剤によって機械的に相互接続されており、
前記第1〜第nの回路層の間の電気的接続は、前記埋込配線と前記導電性接触子とを用いて実現されており、
前記第1〜第nの回路層の少なくとも一つは、その中に含まれる前記半導体回路の持つ前記積層方向に直交する平面内における物理寸法が、当該平面内における当該回路層の物理寸法よりも小さく、当該半導体回路の側面が前記接着剤によって覆われている、三次元積層構造を持つ半導体装置の製造方法であって、
前記支持基板または前記第(n−2)回路層の一面の所定箇所に、その厚さ方向に貫通しない第1埋込配線を有する少なくとも一つの第1半導体回路を、複数の第1導電性接触子を介して機械的及び電気的に接続する工程と、
機械的及び電気的に接続された前記第1半導体回路と前記支持基板または前記第(n−2)回路層の間に生じる隙間に、電気的絶縁性の第1接着剤を充填して硬化させる工程と、
前記第1接着剤の充填・硬化が行われた前記第1半導体回路の前記支持基板とは反対側の面を研磨することによって、前記第1半導体回路を所望厚さに調整すると共に、前記第1埋込配線を前記第1半導体回路の厚さ方向に貫通させ、もって前記支持基板または前記第(n−2)回路層上に前記第(n−1)回路層を形成する工程と、
前記第(n−1)回路層の表面の所定箇所に、その厚さ方向に貫通しない第2埋込配線を有する少なくとも一つの第2半導体回路を、複数の第2導電性接触子を介して機械的及び電気的に接続する工程と、
機械的及び電気的に接続された前記第2半導体回路と前記第(n−1)回路層の間に生じる隙間に、電気的絶縁性の第2接着剤を充填して硬化させる工程と、
前記第2接着剤の充填・硬化が行われた前記第2半導体回路の前記支持基板とは反対側の面を研磨することによって、前記第2半導体回路を所望厚さに調整すると共に、前記第2埋込配線を前記第2半導体回路の厚さ方向に貫通させ、もって前記第(n−1)回路層上に前記第n回路層を形成する工程とを含むことを特徴とする半導体装置の製造方法。 - 前記第(n−1)回路層上に前記第n回路層を形成する工程の後に、前記第n回路層上の所定箇所に外部回路接続用の複数の前記電極を形成する工程をさらに含む請求項14に記載の半導体装置の製造方法。
- 前記第1導電性接触子が、前記支持基板または前記第(n−2)回路層と、前記第1半導体回路とからそれぞれ突出形成されており、それら導電性接触子が相互接続されることで、前記支持基板または前記第(n−2)回路層と前記第(n−1)回路層とが機械的及び電気的に相互接続され、
前記第2導電性接触子が、前記第(n−1)回路層と、前記第2半導体回路とからそれぞれ突出形成されており、それら導電性接触子が相互接続されることで、前記第(n−1)回路層と前記第n回路層とが機械的及び電気的に相互接続される請求項14または15に記載の半導体装置の製造方法。 - 前記支持基板または前記第(n−2)回路層及び前記第1半導体回路の少なくとも一方が、その対向面に向かって突出する剛性部材を有しており、その剛性部材は、前記第1半導体回路の前記積層方向の位置決めを行うためのストッパとして使用され、
前記第(n−1)回路層と前記第2半導体回路との少なくとも一方が、その対向面に向かって突出する剛性部材を有しており、その剛性部材は、前記第2半導体回路の前記積層方向の位置決めを行うためのストッパとして使用される請求項14〜16のいずれか1項に記載の半導体装置の製造方法。 - 前記第1回路層が複数の前記第1半導体回路を含み、前記第2回路層が複数の前記第2半導体回路を含む請求項14〜17のいずれか1項に記載の半導体装置の製造方法。
- 前記第1回路層の前記積層方向に直交する平面内における物理寸法が、少なくとも一つの前記第1半導体回路の同平面内における物理寸法よりも大きく、前記第1半導体回路の側面は前記第1接着剤によって覆われ、前記第2回路層の前記積層方向に直交する平面内における物理寸法が、少なくとも一つの前記第2半導体回路の同平面内における物理寸法よりも大きく、前記第2半導体回路の側面は前記第2接着剤によって覆われる請求項14〜18のいずれか1項に記載の半導体装置の製造方法。
- 前記第1接着剤または前記第2接着剤の前記隙間への充填が、前記第1接着剤または前記第2接着剤を噴霧することによって行われる請求項14〜19のいずれか1項に記載の半導体装置の製造方法。
- 前記第1接着剤または前記第2接着剤の前記隙間への充填が、前記第1半導体回路を前記支持基板または前記第(n−2)回路層に固定した状態で、あるいは前記第2半導体回路と前記第1半導体回路とを固定した状態で、液状とした接着剤の中に浸漬することによって行われる請求項14〜19のいずれか1項に記載の半導体装置の製造方法。
- 前記第1接着剤または前記第2接着剤の前記隙間への充填が、前記支持基板または前記第(n−2)回路層及び前記第1半導体回路を一対の加圧部材によって挟んだ状態で、あるいは前記第1半導体回路及び前記第2半導体回路を一対の加圧部材によって挟んだ状態で、液状の前記接着剤中に浸漬することによって行われる請求項14〜19のいずれか1項に記載の半導体装置の製造方法。
- 前記第1接着剤または前記第2接着剤の前記隙間への充填が、前記支持基板または前記第(n−2)回路層及び前記第1半導体回路を、あるいは前記第1半導体回路及び前記第2半導体回路を、閉じた空間を有する部材の中に配置した状態で、液状の前記接着剤中を前記空間内に加圧注入することによって行われる請求項14〜19のいずれか1項に記載の半導体装置の製造方法。
- 前記第1接着剤または前記第2接着剤の前記隙間への充填が、複数の前記第1半導体回路または複数の前記第2半導体回路を、前記支持基板または前記第(n−2)回路層上、または前記第1回路層上に規則的に配置した後、それらの第1半導体回路または第2半導体回路の間の隙間と周辺に、前記第1接着剤及び前記第2接着剤の少なくとも一方をディスペンサを使用して塗布することによって行われる請求項14〜19のいずれか1項に記載の半導体装置の製造方法。
- 前記隙間に充填された前記第1接着剤を硬化させる際に、前記隙間に前記第1接着剤を充填する前に、前記支持基板または前記第(n−2)回路層の前記第1回路層とは反対側の面に、前記支持基板の反りを防止する層が配置される請求項14〜24のいずれか1項に記載の半導体装置の製造方法。
- 前記隙間に前記第1接着剤を充填して硬化させる際に、前記隙間に前記第1接着剤を充填した後に、前記支持基板または前記第(n−2)回路層の前記第1回路層とは反対側の面に、前記支持基板の反りを防止する反り防止層が配置される請求項14〜24のいずれか1項に記載の半導体装置の製造方法。
- 前記隙間に前記第1接着剤を充填する際またはそれを硬化させる際に、前記支持基板または前記第(n−2)回路層の前記第1回路層とは反対側の面に、前記支持基板の反りを防止する第1反り防止層が配置され、前記隙間に前記第2接着剤を充填する際またはそれを硬化させる際に、前記第1反り防止層の上に、前記支持基板の反りを防止する第2反り防止層が配置される請求項14〜24のいずれか1項に記載の半導体装置の製造方法。
- 前記支持基板または前記第(n−2)回路層上に前記第(n−1)回路層を形成する工程の後に、前記第1接着剤の硬化によって生じる前記支持基板の反りの向きとは反対側に、前記支持基板を湾曲させる工程を含んでいる請求項14〜24のいずれか1項に記載の半導体装置の製造方法。
- 前記第1接着剤及び前記第2接着剤の少なくとも一方がフィラーを含む請求項14〜28いずれか1項に記載の半導体装置の製造方法。
- 前記支持基板と前記積層構造を前記積層方向に平行な切断面によってダイシングし、複数の半導体装置を形成する工程をさらに含んでいる請求項14〜29のいずれか1項に記載の半導体装置の製造方法。
- 前記第1〜第nの回路層の少なくとも一つに含まれる前記半導体回路として、冗長構成を有するものを使用する請求項14〜30のいずれか1項に記載の半導体装置の製造方法。
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CN115116975A (zh) * | 2021-03-19 | 2022-09-27 | 苏州达晶半导体有限公司 | 功率半导体器件封装结构 |
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Also Published As
Publication number | Publication date |
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WO2005119776A1 (ja) | 2005-12-15 |
US20090115042A1 (en) | 2009-05-07 |
TW200610003A (en) | 2006-03-16 |
JPWO2005119776A1 (ja) | 2008-04-03 |
EP1775768A1 (en) | 2007-04-18 |
TWI426542B (zh) | 2014-02-11 |
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