JP5007127B2 - 自己組織化機能を用いた集積回路装置の製造方法及び製造装置 - Google Patents
自己組織化機能を用いた集積回路装置の製造方法及び製造装置 Download PDFInfo
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- JP5007127B2 JP5007127B2 JP2006553851A JP2006553851A JP5007127B2 JP 5007127 B2 JP5007127 B2 JP 5007127B2 JP 2006553851 A JP2006553851 A JP 2006553851A JP 2006553851 A JP2006553851 A JP 2006553851A JP 5007127 B2 JP5007127 B2 JP 5007127B2
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Description
mechanical system,MEMS)に使用されるマイクロデバイスのセルフ・アッセンブリ技術が開示されている。この技術は、疎水性(hydrophobicity)と毛管力(capillary force)を利用して単一基板の上に複数の微小電子部品を搭載する技術である。その基板は、疎水性のアルカンチオールを被覆した金(gold)製の結合部位(binding sites)を複数個持っている。組立(アッセンブリ)時には、基板表面に塗布された炭化水素オイルが、水中で疎水性の結合部位以外の部分を濡らす。次に、微小電子部品は水中に投入され、炭化水素オイルで濡れた結合部位上にそれぞれ集められる。ここで、電気化学的な方法を用いて特定の結合部位を不活性化することにより、微小電子部品は毛管力によって所望の結合部位に集められる。これらの工程を繰り返すことにより、単一基板上に微小電子部品の種々のバッチ(群)を連続して組み立てることが可能となる。組立完了後、電気メッキ(electroplating)を行うことにより、組み立てられた微小電子部品と基板との間の電気的・機械的接続が行われる。
栗野ら、「三次元構造を持つインテリジェント・イメージセンサ・チップ」、1999アイ・イー・ディー・エム テクニカル・ダイジェストp.36.4.1〜36.4.4、1999年(H. Kurino et al.," Intelligent Image Sensor Chip with Three Dimensional Structure", 1999 IEDM Technical Digest, pp. 36.4.1 - 36.4.4, 1999) 李ら、「高度並列画像処理チップ用の三次元集積技術の開発」、「日本応用物理学会誌」第39巻、p.2473〜2477、第1部4B、2000年4月、(K. Lee et al.," Development of Three-Dimensional Integration Technology for Highly Parallel Image-Processing Chip", Jpn. J. Appl. Phys. Vol. 39, pp. 2474 - 2477, April 2000) ションら、「マイクロデバイスの制御されたマルチバッチ・セルフ・アッセンブリ」、ジャーナル・オブ・マイクロエレクトロメカニカル・システムズ、第12巻、第2号、p.117〜127、2003年4月」(X. Xiong et al.," Controlled Multibatch Self-Assembly of Microdevices", Journal of Michroelectromechanical Systems, Vol. 12, No. 2, pp. 117-127, April 2003)
複数の回路層を支持基板上に積層してなる三次元積層構造を持つ集積回路装置の製造方法であって、
前記回路層のいずれか一つに含まれる複数のチップ状半導体回路を当該回路層に隣接する前記支持基板または前記回路層の他の一つの搭載面に所望レイアウトで固着する際に、
転写用支持部材の一面に少なくとも一つの仮接着領域を形成し、
前記チップ状半導体回路の各々の接続部とは反対側の端部に、前記仮接着領域に仮接着可能な仮接着部を形成し、
前記チップ状半導体回路の各々の前記仮接着部を前記仮接着領域に仮接着することにより、複数の前記チップ状半導体回路を前記転写用支持部材上に前記所望レイアウトの鏡像となるレイアウトで載置し、
前記チップ状半導体回路が載置された前記転写用支持部材を、前記支持基板または前記回路層の他の一つの前記搭載面に近接させることにより、前記チップ状半導体回路の前記接続部を前記搭載面の対応する所定箇所に一括して接触させ、
相互に接触せしめられた前記チップ状半導体回路の前記接続部とそれらの対応する前記所定箇所とを相互に固着することにより、複数の前記チップ状半導体回路を前記搭載面に前記所望レイアウトで配置し、
前記転写用支持部材を前記支持基板または前記回路層から離隔させることにより、前記転写用支持部材を前記チップ状半導体回路の前記仮接着部から離脱させる
ことを特徴とするものである。
複数の回路層を支持基板上に積層してなる三次元積層構造を持つ集積回路装置の製造方法であって、
前記回路層のいずれか一つに含まれる複数のチップ状半導体回路を当該回路層に隣接する前記支持基板または前記回路層の他の一つの搭載面に所望レイアウトで固着する際に、
前記搭載面に設定された、複数のチップ状半導体回路の接続部がそれぞれ固着されるべき複数の所定箇所の各々に、親液性領域を形成し、
複数の前記親液性領域のそれぞれに液体の膜を形成し、
複数の前記チップ状半導体回路の前記接続部と複数の前記親液性領域の対応するものとを、前記液体の膜を介在させた対向状態でそれぞれ連結し、
複数の前記接続部と複数の前記親液性領域の対応するものの間に押圧力を印加することによって、複数の前記接続部を複数の前記所定箇所の対応するものにそれぞれ接触させ、
相互に接触せしめられた複数の前記接続部とそれらの対応する前記所定箇所とを相互に固着することにより、複数の前記チップ状半導体回路を前記搭載面に前記所望レイアウトで配置する
ことを特徴とするものである。
上述した第1または第2の観点による集積回路装置の製造方法に使用されるものであって、
本体と、
転写用支持部材または支持基板を保持する被工作物保持機構と、
前記本体に設けられた、一括載置用トレイを保持するトレイ保持機構と、
前記被工作物保持機構及び前記トレイ保持機構の少なくとも一方を変位可能とする、前記本体に設けられた制御ステージと、
前記被工作物保持機構によって保持された転写用支持部材または支持基板と、前記トレイ保持機構によって保持された前記一括載置用トレイの位置合わせを光学的に行う位置合わせ手段と
を備えてなることを特徴とするものである。
11 支持基板
11a 支持基板の搭載面
12 接続部
12a、12b 仮接着部
13 半導体チップ
14 接着剤
15 接合領域
16 半導体チップ
17 接着剤
18 接合領域
19 半導体チップ
20 接着剤
21 接合領域
22 半導体チップ
23 接着剤
24 絶縁層
25 導電性プラグ
26 外部回路接続用マイクロバンプ電極
27 ハンダボール
30A、30B、30C、30A’、30B’、30C’ 集積回路装置
31 支持基板
32 絶縁層
33 配線
34 導電性プラグ
35、36 マイクロバンプ電極
36a マイクロバンプ電極の下層
36b マイクロバンプ電極の上層
37 半導体チップ
37a 仮接着部
38、38a 接着剤
39 絶縁層
40 導電性プラグ
41、42 マイクロバンプ電極
43 半導体チップ
44 接着剤
45 絶縁層
46 導電性プラグ
47、48 マイクロバンプ電極
49 半導体チップ
49a 仮接着部
50 接着剤
51、53、55 絶縁層
52、54、56 導電材
57、57a、57b、58、59 ストッパ
60 外部回路接続用マイクロバンプ電極
61 絶縁層
71,71a 接続部
72、72a 仮接着領域
73、73a キャリア基板
74 接続部
75 接続部
76 仮接着領域
77 キャリア基板
78 親水性領域
79 疎水性領域
81、82 水の膜
83 疎水性液体の膜
85a 接続部
86a 接続部
91a、92a、93a、94a、95a、96a 親水性領域
92 仮接着領域
93 キャリア基板
95 仮接着領域
95a 親水性領域
96 キャリア基板
96a 親水性領域
101 水の膜
120 接合用金属
151、153 絶縁層
152 配線層
154 導電性プラグ
160 MOS型トランジスタ
161 ソース・ドレイン領域
162 ゲート絶縁層
163 ゲート電極
171、173 絶縁層
172 配線層
174 導電性プラグ
180 押付け板
200、200a、200b 一括載置用トレイ
201 本体部
202 外壁
203 上壁
204 仕切壁
205 チップ載置領域
206小孔
207 内部空間
208 給排気口
300、300a 集積回路装置製造装置
301 本体
302 制御ステージ
303 支持台
304 赤外線ランプ
305 真空チャック
306、306a、306b CCDカメラ
307 コンピュータ
R1、R2 接続部
C 半導体チップに形成された半導体集積回路(半導体固体回路群)
L1 第1半導体回路層
L2 第2半導体回路層
L3 第3半導体回路層
L4 第4半導体回路層
図1〜図3は、本発明の三次元積層構造を持つ集積回路装置の製造方法の基本概念を示す概略断面図である。
次に、本発明の第1実施形態に係る三次元積層構造を持つ集積回路装置の製造方法について説明する。
続いて、本発明の第2実施形態に係る三次元積層構造を持つ集積回路装置の製造方法について、図6〜図7を参照しながら説明する。図6〜図7は、本発明の第2実施形態に係る集積回路装置の製造方法において、第1半導体回路層を構成する半導体チップ群をキャリア基板上に配置する工程を示す断面図である。第2実施形態も、第1実施形態と同様に「転写方式」である。
次に、本発明の第3実施形態に係る三次元積層構造を持つ集積回路装置の製造方法について、図8〜図10を参照しながら説明する。
ところで、図8〜図10と図11〜図13では、積層工程を分かりやすくするために半導体チップ37の構成が簡略化されて示されているので、半導体チップ37の実際構成との関係が分かりにくい点があると思われる。そこで、図27を参照しながらその点について説明する。図27は、上述した第3実施形態に係る集積回路装置に使用される半導体チップ37の詳細構成を示す概略断面図である。
上述した第1〜第3実施形態に係る集積回路装置の製造方法(図1〜図13参照)では、半導体回路層の形成に必要な半導体チップのすべてを、転写用支持部材である「キャリア基板」上にいったん配置し、その後、それら半導体チップを一括して支持基板または対応する半導体回路層の所定位置に対向・接触させて固着している。第4実施形態に係る集積回路装置の製造方法では、これとは異なり、「キャリア基板」を使用せずに、半導体回路層の形成に必要な半導体チップのすべてを直接、支持基板または対応する半導体回路層の所定位置に対向・接触させて固着する。半導体チップの転写が行われないこの方法を、本明細書では「無転写方式」と呼ぶ。この点以外は上述した第1実施形態に係る製造方法(図4〜図5を参照)と同一であるから、以下ではそれら同一工程に関する説明は省略し、異なる工程についてのみ詳述する。
図18〜図20は、本発明の第5実施形態に係る三次元積層構造を持つ集積回路装置の製造方法を示す断面図である。図18は支持基板への半導体チップの配置工程を示し、図19〜図20は第2半導体回路層への半導体チップの配置工程を示す。この第5実施形態の製造方法は、第4実施形態の場合と同様に「無転写方式」である。
図21〜図22は、本発明の第6実施形態に係る三次元積層構造を持つ集積回路装置の製造方法で使用される、第1半導体回路層を構成する半導体チップ群を支持基板上に配置する工程を詳細に示す断面図である。
図30〜図31は、本発明の第7実施形態に係る三次元積層構造を持つ集積回路装置の製造方法で使用される、第1半導体回路層を構成する半導体チップ群をキャリア基板上に配置する工程を詳細に示す断面図である。
トレイ200上でのチップ13の配置は、キャリア基板73a上でのレイアウトの鏡像となるレイアウト(すなわち、支持基板11上での所望レイアウト)が得られるように設定される。図31では、描画を簡単化するために、チップ載置領域205を碁盤状に配置した場合を示している。しかし、トレイ200上でのチップ13の配置は、必要なレイアウトに応じて適宜変更されることは言うまでもない。
図32は、本発明の第8実施形態に係る三次元積層構造を持つ集積回路装置の製造方法で使用される、第1半導体回路層を構成する半導体チップ群をキャリア基板上に配置する工程を詳細に示す断面図である。
図33〜図34は、本発明の第9実施形態に係る三次元積層構造を持つ集積回路装置の製造方法で使用される、半導体チップの位置修正方法を示す要部断面図である。この製造方法は、上述した第5実施形態に係る製造方法(図18〜図20を参照)の改良例に対応する。
図35は、本発明の第10実施形態に係る三次元積層構造を持つ集積回路装置の製造方法で使用される、半導体チップの位置修正方法を示す要部断面図である。この製造方法は、上述した第3実施形態に係る製造方法(図8〜図13を参照)の改良例に対応する。
図36〜図37は、本発明の第11実施形態に係る集積回路装置製造装置300を示す要部断面説明図である。この製造装置300は、一括載置用トレイを用いて、複数の半導体チップを一括してキャリア基板上に所望レイアウトで配置することができるものであり、上述した第1〜第10の実施形態の製造方法のいずれも実施可能である。
図38は、本発明の第12実施形態に係る集積回路装置製造装置300aを示す要部断面説明図である。この製造装置300aも、上記第1〜第10実施形態の製造方法の実施に使用されるものである。
上述した第1〜第12の実施形態は本発明を具体化した例を示すものであり、したがって本発明はこれらの実施形態に限定されるものではなく、本発明の趣旨を外れることなく種々の変形が可能であることは言うまでもない。例えば、上述した実施形態では、各半導体回路層中にはKGDである半導体チップを使用するように説明しているが、各半導体回路層中の半導体チップがすべてKGDである必要はない。他の部分の構成のために製造工程では省略することはできないが、回路機能としては不要な部分については、いわゆるダミーチップを使用してもよいことは言うまでもない。
Claims (33)
- 複数の回路層を支持基板上に積層してなる三次元積層構造を持つ集積回路装置の製造方法であって、
前記回路層のいずれか一つに含まれる複数のチップ状半導体回路を当該回路層に隣接する前記支持基板または前記回路層の他の一つの搭載面に所望レイアウトで固着する際に、
転写用支持部材の一面に少なくとも一つの仮接着領域を形成し、
前記チップ状半導体回路の各々の接続部とは反対側の端部に、前記仮接着領域に仮接着可能な仮接着部を形成し、
前記チップ状半導体回路の各々の前記仮接着部を前記仮接着領域に仮接着することにより、複数の前記チップ状半導体回路を前記転写用支持部材上に前記所望レイアウトの鏡像となるレイアウトで載置し、
前記チップ状半導体回路が載置された前記転写用支持部材を、前記支持基板または前記回路層の他の一つの前記搭載面に近接させることにより、前記チップ状半導体回路の前記接続部を前記搭載面の対応する所定箇所に一括して接触させ、
相互に接触せしめられた前記チップ状半導体回路の前記接続部とそれらの対応する前記所定箇所とを相互に固着することにより、複数の前記チップ状半導体回路を前記搭載面に前記所望レイアウトで配置し、
前記転写用支持部材を前記支持基板または前記回路層から離隔させることにより、前記転写用支持部材を前記チップ状半導体回路の前記仮接着部から離脱させ、
複数の前記所定箇所の各々には複数の導電性接触子が露出して形成されていて、それら導電性接触子を用いて、複数の前記半導体回路が前記支持基板または前記回路層の対応する所定箇所にそれぞれ固着せしめられ、
固着された複数の前記導電性接触子を加熱して溶融させることによって、それらの位置ずれを修正する工程を含んでいることを特徴とする集積回路装置の製造方法。 - 複数の前記導電性接触子の各々が、複数の前記所定箇所の対応するものを貫通して外方に突出している請求項1に記載の集積回路装置の製造方法。
- 複数の前記半導体回路の前記接続部の各々に複数の導電性接触子が露出して形成されており、それら導電性接触子を用いて、複数の前記半導体回路が前記支持基板または前記回路層の対応する所定箇所にそれぞれ固着せしめられる請求項1または2に記載の集積回路装置の製造方法。
- 複数の前記半導体回路を前記転写用支持部材上に載置する工程の前に、複数の前記半導体回路を前記所望レイアウトでトレイの上に載置する工程が実行され、複数の前記半導体回路が前記トレイから前記転写用支持部材上に一括して載置せしめられる請求項1〜3のいずれかに記載の集積回路装置の製造方法。
- 複数の回路層を支持基板上に積層してなる三次元積層構造を持つ集積回路装置の製造方法であって、
前記回路層のいずれか一つに含まれる複数のチップ状半導体回路を当該回路層に隣接する前記支持基板または前記回路層の他の一つの搭載面に所望レイアウトで固着する際に、
転写用支持部材の一面に少なくとも一つの仮接着領域を形成し、
前記チップ状半導体回路の各々の接続部とは反対側の端部に、前記仮接着領域に仮接着可能な仮接着部を形成し、
前記チップ状半導体回路の各々の前記仮接着部を前記仮接着領域に仮接着することにより、複数の前記チップ状半導体回路を前記転写用支持部材上に前記所望レイアウトの鏡像となるレイアウトで載置し、
前記チップ状半導体回路が載置された前記転写用支持部材を、前記支持基板または前記回路層の他の一つの前記搭載面に近接させることにより、前記チップ状半導体回路の前記接続部を前記搭載面の対応する所定箇所に一括して接触させ、
相互に接触せしめられた前記チップ状半導体回路の前記接続部とそれらの対応する前記所定箇所とを相互に固着することにより、複数の前記チップ状半導体回路を前記搭載面に前記所望レイアウトで配置し、
前記転写用支持部材を前記支持基板または前記回路層から離隔させることにより、前記転写用支持部材を前記チップ状半導体回路の前記仮接着部から離脱させ、
前記転写用支持部材の前記仮接着領域は、複数の前記半導体回路の総数と同数設けてあって、複数の前記半導体回路と前記仮接着領域とが一対一対応とされており、
前記転写用支持部材の前記仮接着領域に対する前記半導体回路の仮接着は、液体の吸着力を使用して行われることを特徴とする集積回路装置の製造方法。 - 前記液体に、表面張力を増加するための添加剤が添加されている請求項5に記載の集積回路装置の製造方法。
- 前記液体として水を使用する請求項5に記載の集積回路装置の製造方法。
- 前記水に、表面張力を増加するための添加剤が添加されている請求項7に記載の集積回路装置の製造方法。
- 前記半導体回路の前記仮接着領域に対する仮接着が、
複数の前記半導体回路の前記接続部とは反対側の前記端部と、当該端部に対応する前記仮接着領域の少なくとも一方に液体の膜を形成する工程と、
前記液体の膜を用いて複数の前記端部を複数の前記仮接着領域の対応するものに対向状態でそれぞれ連結する工程と、
複数の前記端部と複数の前記仮接着領域の対応するものとの間に押圧力を印加することによって、複数の前記端部を複数の前記仮接着領域の対応するものにそれぞれ接触させ、もって複数の前記半導体回路を複数の前記仮接着領域の対応するものに離脱可能に仮接着する工程と
を含んで実行される請求項5に記載の集積回路装置の製造方法。 - 前記仮接着領域が、前記液体に対して親液性のある材料または前記液体に対して親液性のない材料を用いて、前記転写用支持部材の一面に選択的に形成された膜によって画定される請求項5に記載の集積回路装置の製造方法。
- 複数の前記所定箇所の各々に複数の導電性接触子が露出して形成されており、それら導電性接触子を用いて、複数の前記半導体回路が前記支持基板または前記回路層の対応する所定箇所にそれぞれ固着せしめられる請求項5に記載の集積回路装置の製造方法。
- 複数の前記導電性接触子の各々が、複数の前記所定箇所の対応するものを貫通して外方に突出している請求項11に記載の集積回路装置の製造方法。
- 前記半導体回路と前記支持基板または前記回路層との前記導電性接触子を用いた固着が、接合用金属を用いる接合、接合用金属を用いない圧接による接合、または接合用金属を用いない溶着による接合によって行われる請求項11に記載の集積回路装置の製造方法。
- 複数の前記半導体回路の前記接続部の各々に複数の導電性接触子が露出して形成されており、それら導電性接触子を用いて、複数の前記半導体回路が前記支持基板または前記回路層の対応する所定箇所にそれぞれ固着せしめられる請求項5に記載の集積回路装置の製造方法。
- 複数の前記導電性接触子の各々が、複数の前記所定箇所の対応するものを貫通して外方に突出している請求項14に記載の集積回路装置の製造方法。
- 前記半導体回路と前記支持基板または前記回路層との前記導電性接触子を用いた固着が、接合用金属を用いる接合、接合用金属を用いない圧接による接合、または接合用金属を用いない溶着による接合によって行われる請求項14に記載の集積回路装置の製造方法。
- 固着された複数の前記導電性接触子を加熱して溶融させ、もってそれらの位置ずれを修正する工程を含んでいる請求項11に記載の集積回路装置の製造方法。
- 複数の前記半導体回路を前記転写用支持部材上に載置する工程の前に、複数の前記半導体回路を前記所望レイアウトでトレイの上に載置する工程が実行され、複数の前記半導体回路が前記トレイから前記転写用支持部材上に一括して載置せしめられる請求項5に記載の集積回路装置の製造方法。
- 複数の回路層を支持基板上に積層してなる三次元積層構造を持つ集積回路装置の製造方法であって、
前記回路層のいずれか一つに含まれる複数のチップ状半導体回路を当該回路層に隣接する前記支持基板または前記回路層の他の一つの搭載面に所望レイアウトで固着する際に、
前記搭載面に設定された、複数のチップ状半導体回路の接続部がそれぞれ固着されるべき複数の所定箇所の各々に、親液性領域を形成し、
複数の前記親液性領域のそれぞれに液体の膜を形成し、
複数の前記チップ状半導体回路の前記接続部と複数の前記親液性領域の対応するものとを、前記液体の膜を介在させた対向状態でそれぞれ連結し、
複数の前記接続部と複数の前記親液性領域の対応するものの間に押圧力を印加することによって、複数の前記接続部を複数の前記所定箇所の対応するものにそれぞれ接触させ、
相互に接触せしめられた複数の前記接続部とそれらの対応する前記所定箇所とを相互に固着することにより、複数の前記チップ状半導体回路を前記搭載面に前記所望レイアウトで配置する
ことを特徴とする集積回路装置の製造方法。 - 複数の前記親液性領域が、複数の前記半導体回路の総数と同数設けてあって、複数の前記半導体回路と前記親液性領域とが一対一対応とされている請求項19に記載の集積回路装置の製造方法。
- 複数の前記半導体回路の前記接続部の各々に、前記液体に対して親液性を有する親液性領域が形成されている請求項19に記載の集積回路装置の製造方法。
- 複数の前記親液性領域が、前記液体に対して親液性を持つ材料または前記液体に対して親液性を持たない材料を用いて、前記支持基板または前記回路層の一面に選択的に形成された膜によって画定される請求項19に記載の集積回路装置の製造方法。
- 複数の前記親液性領域の各々に、複数の導電性接触子が露出して形成されており、それら導電性接触子を用いて、複数の前記半導体回路の各々が前記支持基板または前記回路層の対応する所定箇所にそれぞれ固着せしめられる請求項19に記載の集積回路装置の製造方法。
- 複数の前記導電性接触子の各々が、複数の前記親液性領域の対応するものを貫通して外方に突出している請求項23に記載の集積回路装置の製造方法。
- 前記半導体回路と前記支持基板または前記回路層との前記導電性接触子を用いた固着が、接合用金属を用いる接合、接合用金属を用いない圧接による接合、または接合用金属を用いない溶着による接合によって行われる請求項23に記載の集積回路装置の製造方法。
- 複数の前記半導体回路の前記接続部の各々に、複数の導電性接触子が露出して形成されており、それら導電性接触子を用いて、複数の前記半導体回路が前記支持基板または前記回路層の対応する所定箇所にそれぞれ固着せしめられる請求項25に記載の集積回路装置の製造方法。
- 複数の前記導電性接触子の各々が、複数の前記接続部の各々に形成された親液性領域の対応するものを貫通して外方に突出している請求項25に記載の集積回路装置の製造方法。
- 前記半導体回路と前記支持基板または前記回路層との前記導電性接触子を用いた固着が、接合用金属を用いる接合、接合用金属を用いない圧接による接合、または接合用金属を用いない溶着による接合によって行われる請求項26に記載の集積回路装置の製造方法。
- 固着された複数の前記導電性接触子を加熱して溶融させ、もってそれらの位置ずれを修正する工程を含む請求項23に記載の集積回路装置の製造方法。
- 前記液体の膜を用いて、複数の前記半導体回路の前記接続部を複数の前記親液性領域の対応するものに対向状態でそれぞれ連結する工程の前に、複数の前記半導体回路を前記所望レイアウトでトレイの上に載置する工程が実行され、複数の前記半導体回路が前記トレイから前記支持基板または前記回路層の上に一括して載置せしめられる請求項19に記載の集積回路装置の製造方法。
- 複数の回路層を支持基板上に積層してなる三次元積層構造を持つ集積回路装置の製造方法において、前記回路層のいずれか一つに含まれる複数のチップ状半導体回路を当該回路層に隣接する前記支持基板または前記回路層の他の一つの搭載面に所望レイアウトで固着する際に使用されるものであって、
本体と、
転写用支持部材または支持基板を保持する被工作物保持機構と、
前記本体に設けられた、一括載置用トレイを保持するトレイ保持機構と、
前記被工作物保持機構及び前記トレイ保持機構の少なくとも一方を変位可能とする、前記本体に設けられた制御ステージと、
前記被工作物保持機構によって保持された転写用支持部材または支持基板と、前記トレイ保持機構によって保持された前記一括載置用トレイの位置合わせを光学的に行う位置合わせ手段とを備え、
前記一括載置用トレイには、複数の前記半導体回路の総数と同数のチップ載置領域が設けてあって、複数の前記半導体回路と前記チップ載置領域とが一対一対応とされていることを特徴とする集積回路装置の製造装置。 - 前記位置合わせ手段が、光源と、前記光源から出射される光線を前記被工作物保持機構及び前記トレイ保持機構を介して受光して撮像を行う撮像装置と、前記撮像装置から得られる画像データを用いて演算を行う演算装置とを備え、前記演算装置を用いて前記転写用支持部材または前記支持基板と前記一括載置用トレイの位置合わせが実行される請求項31に記載の集積回路装置の製造装置。
- 前記位置合わせ手段が、前記被工作物保持機構によって保持された前記転写用支持部材または前記支持基板と前記トレイ保持機構によって保持された前記一括載置用トレイとを撮像する撮像装置と、前記撮像装置から得られる画像データを用いて演算を行う演算装置とを備え、前記演算装置を用いて前記転写用支持部材または前記支持基板と前記一括載置用トレイの位置合わせが実行される請求項31に記載の集積回路装置の製造装置。
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Also Published As
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US20090023243A1 (en) | 2009-01-22 |
TWI395253B (zh) | 2013-05-01 |
US8722460B2 (en) | 2014-05-13 |
TW200710923A (en) | 2007-03-16 |
US20130045569A1 (en) | 2013-02-21 |
US8283208B2 (en) | 2012-10-09 |
US20110249113A1 (en) | 2011-10-13 |
JPWO2006077739A1 (ja) | 2008-06-19 |
WO2006077739A1 (ja) | 2006-07-27 |
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