CN109216219B - 具有双侧金属布线的半导体封装件 - Google Patents

具有双侧金属布线的半导体封装件 Download PDF

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Publication number
CN109216219B
CN109216219B CN201810455793.4A CN201810455793A CN109216219B CN 109216219 B CN109216219 B CN 109216219B CN 201810455793 A CN201810455793 A CN 201810455793A CN 109216219 B CN109216219 B CN 109216219B
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conductive
die
redistribution structure
substrate
molding material
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CN109216219A (zh
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郑心圃
陈硕懋
刘献文
庄博尧
许峯诚
林柏尧
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

方法包括在载体上方形成再分布结构，再分布结构具有位于再分布结构的远离载体的表面上的导电部件；在再分布结构的表面上方形成导电柱；将管芯附接至再分布结构的邻近导电柱的表面，其中，管芯的管芯连接件电连接至再分布结构的导电部件；以及通过导电接头将预制衬底附接至导电柱，其中，导电接头位于导电柱上并且包括与导电柱不同的材料，其中，导电接头和导电柱将再分布结构电连接至预制衬底。本发明的实施例还涉及具有双侧金属布线的半导体封装件。

Description

具有双侧金属布线的半导体封装件
技术领域
本发明的实施例涉及具有双侧金属布线的半导体封装件。
背景技术
由于各个电组件(例如，晶体管、二极管、电阻器、电容器等)的集成密度的持续改进，半导体工业已经经历了快速增长。对于大部分而言，这种集成密度的改进来自于最小部件尺寸的连续减小，这使得更多的组件集成到给定的区域。随着近来对更小的电子器件的需求的增长，对半导体管芯的更小且更具创造性的封装技术的需求也已增长。
这些封装技术的一个实例是叠层封装(POP)技术。在PoP封装件中，顶部半导体封装件堆叠在底部半导体封装件的顶部上以允许高集成度和组件密度。另一个实例是多芯片模块(MCM)技术，其中，多个半导体管芯被封装在一个半导体封装件中以提供具有集成功能的半导体器件。
先进封装技术的高集成度使得能够生产具有增强的功能和小的覆盖区的半导体器件，这对于诸如移动电话、平板电脑和数字音乐播放器的小型器件是有利的。另一个优势是缩短连接半导体封装件内的互操作部分的导电路径的长度。这提高了半导体器件的电性能，因为电路之间互连的较短布线产生更快的信号传播并且减少了噪声和串扰。
发明内容
本发明的实施例提供了一种形成半导体器件的方法，包括：在载体上方形成再分布结构，所述再分布结构具有位于所述再分布结构的远离所述载体的表面上的导电部件；在所述再分布结构的所述表面上方形成导电柱；将管芯附接至所述再分布结构的邻近所述导电柱的表面，其中，所述管芯的管芯连接件电连接至所述再分布结构的导电部件；以及通过导电接头将预制衬底附接至所述导电柱，其中，所述导电接头位于所述导电柱上并且包括与所述导电柱不同的材料，其中，所述导电接头和所述导电柱将所述再分布结构电连接至所述预制衬底。
本发明的另一实施例提供了一种形成半导体器件的方法，包括：在载体上方形成再分布结构，所述再分布结构具有位于所述再分布结构的远离所述载体的表面上的导电焊盘；将管芯的管芯连接件接合至所述导电焊盘；在所述载体上方和所述管芯周围形成模制材料；通过粘合层将预制衬底附接至所述模制材料和所述管芯，所述预制衬底具有电隔离的伪金属部件；在附接所述预制衬底之后，使所述再分布结构的介电层凹进以暴露所述再分布结构的导电部件；以及在暴露的导电部件上形成导电凸块。
本发明的又一实施例提供了一种半导体器件，包括：第一管芯，嵌入在第一模制材料内，所述第一管芯具有位于所述第一管芯的第一侧处的管芯连接件；第一导电柱，嵌入在所述第一模制材料内并且与所述第一管芯横向间隔开；再分布结构，位于所述第一管芯的第一侧处，通过焊料接头将所述管芯连接件电连接至所述再分布结构的导电部件，所述导电部件位于所述再分布结构的面向所述第一管芯的表面上；衬底，位于所述第一管芯的与所述第一侧相对的第二侧处；以及第一焊料区域，插入在所述第一导电柱和所述衬底之间，其中，所述第一焊料区域和所述第一导电柱将所述再分布结构电连接至所述衬底。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该指出，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1至图5、图6A和图6B示出了根据实施例的处于各个制造阶段的半导体器件的截面图。
图7示出了根据实施例的半导体器件的截面图。
图8示出了根据实施例的半导体器件的截面图。
图9示出了根据实施例的半导体器件的截面图。
图10至图15示出了根据实施例的处于各个制造阶段的半导体器件的截面图。
图16示出了根据实施例的半导体器件的截面图。
图17示出了根据实施例的半导体器件的截面图。
图18示出了根据实施例的半导体器件的截面图。
图19至图22示出了根据实施例的处于各个制造阶段的半导体器件的截面图。
图23示出了根据实施例的半导体器件的截面图。
图24至图27示出了根据实施例的处于各个制造阶段的半导体器件的截面图。
图28示出了根据实施例的半导体器件的截面图。
图29至图32示出了根据实施例的处于各个制造阶段的半导体器件的截面图。
图33示出了根据实施例的半导体器件的截面图。
图34至图37示出了根据实施例的处于各个制造阶段的半导体器件的截面图。
图38示出了根据一些实施例的用于形成半导体器件的方法的流程图。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其它方式定向(旋转90度或在其它方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。
在各个实施例中提供半导体器件和形成半导体器件的方法。在一些实施例中，半导体器件包括再分布结构、一个或多个半导体管芯(其中，半导体管芯的前侧附接至再分布结构，)以及附接至一个或多个半导体管芯的背侧的衬底。在一些实施例中，衬底包括用于重新路由电信号的一个或多个再分布层，并且电连接至再分布结构和/或一个或多个半导体管芯。在其它实施例中，衬底包括电隔离的伪金属图案。附接至一个或多个半导体管芯的背侧的衬底可以帮助平衡半导体管芯的两侧(例如，前侧和背侧)上的金属密度，从而减少半导体器件的翘曲。
图1至图5、图6A和图6B示出了根据实施例的处于各个制造阶段的半导体器件100的截面图。在图1中，在载体101上方形成再分布结构150。再分布结构150包括形成在一个或多个介电层中的导电部件(例如，导线和通孔)。导电柱149形成在再分布结构150的上表面上方并且电连接至再分布结构150。
载体101可以由诸如硅、聚合物、聚合物复合材料、金属箔、陶瓷、玻璃、玻璃环氧树脂、氧化铍、带或用于结构支撑的其它合适材料的材料制成。再分布结构150形成在载体101上方。再分布结构150包括导电部件，诸如一层或多层导线(例如，113、123)和通孔(例如，125、145)以及一个或多个介电层(例如，107、110、120、130、140)。在一些实施例中，一个或多个介电层107/110/120/130/140由诸如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等的聚合物形成。在其它实施例中，介电层107/110/120/130/140由氮化物，诸如氮化硅；氧化物，诸如氧化硅、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)；等形成。可以通过诸如旋涂、化学汽相沉积(CVD)、层压等或它们的组合的任何可接受的沉积工艺形成一个或多个介电层107/110/120/130/140。
在一些实施例中，再分布结构150的导电部件包括由诸如铜、钛、钨、铝等的合适的导电材料形成的导线(例如，113、123)、导电通孔(例如，125、145)。导电部件也可以包括用于连接至电组件或器件的导电焊盘(例如，147)(例如，见图2)。之后导电通孔115被暴露(例如，见图5)并且用作连接至电组件或器件的导电焊盘，因此也可以称为导电焊盘115。在一些实施例中，通过在介电层110中形成开口，在介电层110上方和开口中形成晶种层(未示出)，在晶种层上方形成具有设计图案的图案化的光刻胶(未示出)，将导电材料镀(例如，电镀或化学镀)至设计图案中和晶种层上方，以及去除光刻胶和晶种层的其上未形成导电材料的部分来形成导线113和导电焊盘115。
注意，在图1示出的实例中，在形成介电层110之前在载体101上方形成可以用作缓冲层的介电层107。在其它实施例中，介电层107不在介电层110之前形成，而是形成为介电层110的部分。换句话说，图1中示出的介电层107和介电层110可以是以相同的沉积工艺形成的一个连续的介电层110，此时介电层110中的开口不会延伸穿过介电层110，因此介电层110的部分设置在导电焊盘115的底面与载体101之间。
在一些实施例中，在形成再分布结构150之前，在载体101上方沉积或层压粘合层(未示出)。粘合层可以是感光的并且可以通过在随后的载体脱粘工艺中对载体101照射例如紫外(UV)光而容易地从载体101脱离。例如，粘合层可以是由明尼苏达州圣保罗的3M公司制造的光热转换(LTHC)涂层。
在形成导线113和导电焊盘115之后，可以通过实施与上面描述的用于形成介电层110和导电部件(例如，113和115)类似的工艺来形成附加介电层和附加导电部件。介电层110上方的通孔(例如，125、145)电连接至相应的下面的导电部件。图1也示出了形成在再分布结构150的上表面上方(例如，介电层140的上表面上方)的导电焊盘147，其可以用于连接至例如半导体管芯221(见图2)。虽然在图1中示出了四个介电层，但是对再分布结构150可以使用多于或少于四个介电层。
仍然参照图1，在再分布结构150上方形成导电柱149。导电柱149可以通过以下步骤形成：在再分布结构150上方形成晶种层；在晶种层上方形成图案化的光刻胶，其中，图案化的光刻胶中的每个开口均对应于将形成的导电柱149的位置；使用例如电镀或化学镀用诸如铜的导电材料填充开口；使用例如灰化或剥离工艺去除光刻胶；以及去除晶种层的其上未形成导电柱149的部分。注意，在图1的实例中，导电柱149的高度H1形成为较小，从而使得导电柱149的上表面低于(例如，更接近再分布结构150)随后附接至再分布结构150的半导体管芯221(见图2)的上表面。
下一步，在图2中，一个或多个半导体管芯221(也可以称为管芯或集成电路(IC)管芯)机械和电连接至再分布结构150的上表面上的导电焊盘147。可以是铜柱或其它合适的连接件的半导体管芯221的导电凸块225(也可以称为管芯连接件)经由导电区域223机械和电连接至导电焊盘147。在一些实施例中，导电区域223是焊料区域(例如，焊料凸块)。
在附接至再分布结构150之前，可以根据可应用的制造工艺处理管芯221以在管芯221中形成集成电路。例如，管芯221每个均可以包括掺杂或未掺杂的半导体衬底(诸如硅)或绝缘体上半导体(SOI)衬底的有源层。半导体衬底可以包括其它半导体材料，例如锗；化合物半导体，包括碳化硅、砷化镓、磷化镓、氮化镓、磷化铟、砷化铟和/或锑化铟；合金半导体，包括SiGe、GaAsP、Al InAs、AlGaAs、GaInAs、GaInP和/或GaInAsP；或它们的组合。也可以使用诸如多层衬底或梯度衬底的其它衬底。诸如晶体管、二极管、电容器、电阻器等的器件可以形成在半导体衬底中和/或上，并且可以通过由例如半导体衬底上的一个或多个介电层中的金属化图案形成的互连结构互连以形成集成电路。
管芯221还包括制成外部连接的焊盘(未示出)，诸如铝焊盘。焊盘位于可以称为管芯221的有源侧或前侧的位置上。在管芯221上和部分焊盘上形成钝化膜(未示出)。开口穿过钝化膜至焊盘。诸如导电柱(例如，包括诸如铜的金属)的管芯连接件225位于穿过钝化膜的开口中并且机械地和电连接至相应的焊盘。可以通过例如镀等形成管芯连接件225。管芯连接件225电连接至管芯221的集成电路。
在管芯221的有源侧上(诸如在钝化膜和/或管芯连接件225上)形成介电材料(图2中未示出，例如，见图19中的228)。介电材料横向密封管芯连接件225，并且介电材料与相应的管芯221横向相连。介电材料可以是聚合物，诸如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等；氮化物，诸如氮化硅等；氧化物，诸如氧化硅、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)等；或它们的组合，并且可以例如通过旋涂、层压、CVD等形成。
如图2示出的，在管芯221附接至再分布结构150之后，形成底部填充材料227以填充半导体管芯221和再分布结构150之间的间隙。底部填充材料227也可以填充或部分填充半导体管芯221之间的间隙以及导电柱149和半导体管芯221之间的间隙。底部填充材料227的示例性材料包括但不限于聚合物和其它合适的非导电材料。可以使用例如针或喷射分配器将底部填充材料227分配在半导体管芯221和再分布结构150之间的间隙中。可以实施固化工艺以固化底部填充材料227。
虽然在图2中示出了两个管芯221，但是可以使用多于或少于两个管芯221来形成半导体器件100。此外，尽管导电柱149示出为沿着半导体器件100的周边形成，但是导电柱149可以形成在管芯221之间。这些和其它变型均完全旨在包括在本发明的范围内。
下一步，在图3中，通过导电接头323将衬底350(预制的)附接至导电柱149。在一些实施例中，衬底350是印刷电路板(PCB)。在其它实施例中，衬底350是中介层。
在图3示出的实例中，衬底350包括由诸如树脂或玻璃纤维的介电材料形成的芯310。例如，芯310可以包括双马来酰亚胺三嗪(BT)树脂，FR-4(由编织玻璃纤维布与阻燃性的环氧树脂粘合剂组成的复合材料)、陶瓷、玻璃、塑料、带、膜或其它支撑材料。诸如铜线和/或铜焊盘的导电部件313和315形成在芯310的相对侧上，并且可以用作再分布层以将电信号从衬底350的第一位置重新路由至衬底350的第二位置。导电通孔317延伸穿过芯310，并且电连接至导电部件313/315。图3也示出了位于芯310的上表面上和导电部件313上方的介电层320(例如，阻焊层)。可以在介电层320中形成开口，该开口暴露导电部件313的部分。诸如焊料凸块的外部连接件325可以形成在开口中并且电连接至导电部件313。外部连接件325可以用于将衬底350连接至另一器件，诸如存储器芯片。图3还示出了位于芯310的下表面上和导电部件315上方的介电层330(例如，阻焊层)。在介电层330中形成开口，该开口暴露导电部件315的部分。在示出的实施例中，衬底350不具有有源组件(例如，晶体管)。
在一些实施例中，导电接头323是焊料区域。例如，可以在导电柱149(例如，铜柱)上和/或在衬底350的相应的暴露的导电部件315上形成焊膏；通过焊膏将衬底350附接至导电柱149；以及之后实施回流工艺以熔化焊膏以形成焊料区域323。因此，在一些实施例中，焊料区域323从导电柱149穿过介电层330延伸至衬底350的导电部件315。在图3示出的实例中，在形成焊料区域323之后，衬底350的下表面在管芯221的上表面之上并且不接触管芯221。
图3中的衬底350的结构是用于说明目的而不用于限制。衬底350可以具有其它结构。例如，衬底350的芯310可以不是图3中示出的单层芯，相反，芯310可以包括多个介电层，并且可以在多个介电层中形成导线和/或通孔的多层。衬底350的这些和其它变型均完全旨在包括在本发明的范围内。
下一步，在图4中，形成模制材料327以填充衬底350和管芯221/再分布结构150之间的间隔。例如，模制材料327可以包括环氧树脂、有机聚合物、添加或不添加二氧化硅基或玻璃填料的聚合物或其它材料。在一些实施例中，模制材料327包括当施加时为凝胶型液体的液体模塑料(LMC)。当施加时，模制材料327也可以包括液体或固体。可选地，模制材料327可以包括其它绝缘和/或密封材料。在一些实施例中，使用晶圆级模制工艺来施加模制材料327。模制材料327可以使用例如压缩模制、传递模制或其它方法来模制。
下一步，在一些实施例中，使用固化工艺来固化模制材料327。固化工艺可以包括使用退火工艺或其它加热工艺将模制材料327加热至预定温度预定时间段。固化工艺也可以包括紫外(UV)曝光工艺、红外(IR)能量曝光工艺、它们的组合或它们与加热工艺的组合。可选地，可以使用其它方法来固化模制材料327。在一些实施例中，不包括固化工艺。在示出的实施例中，模制材料327与底部填充材料227不同。
下一步，在图5中，翻转半导体器件100，并且将外部连接件325附接至由框架410支撑的带413。带413可以是粘性的切割带，用于在随后的工艺中保持半导体器件100位于适当的位置。下一步，通过脱粘工艺使载体101从半导体器件100脱离(脱粘)。脱粘工艺可以使用任何合适的工艺(诸如蚀刻、研磨和机械剥离)去除载体101。在载体101和再分布结构150之间使用诸如LTHC膜的粘合层的实施例中，载体101通过在载体101的表面上方照射激光或UV光而脱粘。激光或UV光破坏结合至载体101的粘合层的化学键，并且之后可以容易地使载体101脱离。
下一步，使介电层110(或介电层107，如果形成的话)凹进以暴露导电焊盘115。在一些实施例中，诸如化学机械抛光(CMP)工艺等或它们的组合的蚀刻工艺可以用于暴露导电焊盘115。在其它实施例中，激光钻孔工艺、光刻和/或蚀刻工艺等可以用于暴露导电焊盘115。之后，在导电焊盘115上方形成外部连接件153。在一些实施例中，外部连接件153是诸如微凸块的导电凸块，并且可以包括诸如锡的材料或诸如银或铜的其它合适的材料。在外部连接件153是锡焊料凸块的实施例中，可以通过首先由诸如蒸发、电镀、印刷、焊料转移或球植的任何合适方法形成锡层来形成外部连接件153。一旦在结构上形成了锡层，则实施回流以将材料成形为具有例如约20μm的直径的期望的凸块形状，但是可以可选地利用任何合适的尺寸。
然而，本领域普通技术人员将意识到，虽然上面已经将外部连接件153描述为微凸块，但是这些仅仅旨在说明并且不旨在限制实施例。而且，可以可选地利用任何合适类型的外部连接件，诸如可控塌陷芯片连接(C4)凸块、铜柱、铜层、镍层、无铅(LF)层、化学镀镍化学镀钯浸金(ENEPIG)层、Cu/LF层、Sn/Ag层、Sn/Pb、这些的组合等。任何合适的外部连接件以及用于形成外部连接件的任何合适的工艺都可以用于外部连接件153，并且所有这种外部连接件均完全旨在包括在实施例的范围内。
虽然未示出，但是可以在形成外部连接件153之后实施切割工艺，以将半导体器件100与在与半导体器件100相同的工艺步骤中形成的其它相邻半导体器件(未示出)分离，从而形成多个单独的半导体器件。图6A示出了切割工艺之后的半导体器件100。
下一步，如图6B所示，可以将诸如存储器器件的半导体器件500附接至图6A所示的半导体器件100以形成图6B中的半导体器件100，从而形成具有叠层封装(PoP)结构的半导体封装件。如图6B中示出的，半导体器件500具有衬底510和附接至衬底510的上表面的一个或多个半导体管芯517。
在一些实施例中，衬底510包括硅、砷化镓、绝缘体上硅(“SOI”)或其它类似的材料。在一些实施例中，衬底510是多层电路板。在一些实施例中，衬底510包括双马来酰亚胺三嗪(BT)树脂，FR-4(由编织玻璃纤维布与阻燃性的环氧树脂粘合剂组成的复合材料)、陶瓷、玻璃、塑料、带、膜或其它支撑材料。衬底510可以包括形成在衬底510中/上的导电部件(例如，导线和通孔，未示出)。如图6B中示出的，衬底510具有形成在衬底510的上表面和下表面上的导电焊盘513，导电焊盘513电连接至衬底510的导电部件。一个或多个半导体管芯517通过例如接合线515电连接至导电焊盘513。在衬底510上方和半导体管芯517周围形成可以包括环氧树脂、有机聚合物、聚合物等的模制材料530。通过导电接头525将半导体器件500电和机械连接至衬底350，导电接头525可以通过将半导体器件500的外部连接件与衬底350的外部连接件325接合形成。在一些实施例中，导电接头525包括焊料区域、导电柱(例如，铜柱)或任何其它合适的导电接头。虽然未示出，但半导体器件500可以与其它实施例的器件(诸如在下文中讨论的半导体器件200、300和400)接合，以如图6B中示出的类似的方式形成各个PoP封装件。
图7至图9示出了在各个实施例中的与半导体器件100类似并且可以使用图1至图6A中示出的类似的工艺形成的但具有修改的半导体器件的截面图。例如，可以在一个工艺步骤中使用模制底部填充物(MUF)来填充管芯221和再分布结构150之间的间隙，并且填充再分布结构150/管芯221和衬底350之间的间隔(见图7和图9)，从而减少工艺时间和成本。如另一实例，可以简化衬底350的设计以在芯310的一侧而不是芯310的两侧上具有再分布层(例如，导线)。下面进一步讨论了图7至图9中的半导体器件的细节。
参照图7，示出了与图6A中示出的半导体器件100类似但没有底部填充材料227的半导体器件100A的实施例。具体地，为了形成半导体器件100A，没有在图2的工艺步骤中形成底部填充材料227。而是，在将衬底350附接至导电柱149(见图3)之后，使用模制底部填充(MUF)材料作为模制材料327以在图4所示的工艺步骤中填充管芯221和再分布结构150之间的间隙，并且填充再分布结构150/管芯221和衬底350之间的间隔，从而在一个工艺步骤中填充上述的间隙和间隔，由此减少工艺时间和制造成本。
在一些实施例中，图7的MUF材料327与图4的底部填充材料227不同在于，MUF材料327中的填料比底部填充材料227中的填料更细(例如，具有更小的尺寸)以促进MUF流入较小的间隙。此外，MUF材料也可以比底部填充材料227具有更高百分比的填料以控制(例如，降低)MUF材料的热膨胀系数(CTE)。
图8示出了半导体器件100B的另一实施例，半导体器件100B与图6A中的半导体器件100类似，但是衬底350具有不同的结构。具体地，图8中的衬底350的芯310的仅一侧(例如，上侧)具有形成在其上的导电部件(例如，313)，并且不沿着芯310的另一侧(例如，下侧)形成导电部件。导电通孔317电连接至导电部件313并且延伸穿过芯310。
图9示出了半导体器件100C的另一实施例，半导体器件100C与图8中的半导体器件100B类似，但是在管芯221和再分布结构150之间没有底部填充材料227。在一些实施例中，图9中的模制材料327是MUF材料。
图10至图15示出了根据实施例的处于各个制造阶段的半导体器件200的截面图。除非另有说明，否则图10至图15中相同的标号是指图1至图6A中相同的部分。例如，具有相同标号的组件可以由相同或类似的材料形成，并且可以使用相同或类似的形成方法形成。为了简单起见，可能不再重复细节。
首先参照图10，在载体101上方形成再分布结构150。导电柱148形成在再分布结构150上方，并且机械地和电连接至再分布结构150。在一些实施例中，导电柱148包括与图1中的导电柱149相同的材料并且可以使用相同的方法形成，但是具有更大的高度H2。高度H2可以等于或大于管芯221(见图11)的上表面和再分布结构150的上表面之间的距离。
下一步，在图11中，将一个或多个管芯221附接至再分布结构150的导电焊盘147。例如，通过实施回流工艺，管芯221的管芯连接件225通过焊料区域223连接至导电焊盘147。在将管芯221附接至再分布结构150之后，形成底部填充材料227以填充管芯221和再分布结构150之间的间隙。
下一步，在管芯221、导电柱148和底部填充材料227周围的再分布结构150的上表面上方形成模制材料337。例如，模制材料337可以包括环氧树脂、有机聚合物、添加或不添加二氧化硅基或玻璃填料的聚合物或其它材料。在一些实施例中，模制材料337包括当施加时为凝胶型液体的液体模塑料(LMC)。当施加时，模制材料337也可以包括液体或固体。可选地，模制材料337可以包括其它绝缘和/或密封材料。在一些实施例中，使用晶圆级模制工艺来施加模制材料337。模制材料337可以使用例如压缩模制、传递模制或其它方法来模制。
下一步，在一些实施例中，使用固化工艺来固化模制材料337。固化工艺可以包括使用退火工艺或其它加热工艺将模制材料337加热至预定温度预定时间段。固化工艺也可以包括紫外(UV)曝光工艺、红外(IR)能量曝光工艺、它们的组合或它们与加热工艺的组合。可选地，可以使用其它方法来固化模制材料337。在一些实施例中，不包括固化工艺。在一些实施例中，模制材料337与底部填充材料227不同。
在形成模制材料337之后，可以实施诸如CMP的平坦化工艺以去除模制材料337的上部，以实现管芯221、导电柱148和模制材料337之间的共面上表面。平坦化工艺也可以去除导电柱148的顶部和/或管芯221的顶部(例如，管芯221的减薄)。
下一步，参照图12，通过导电接头323将预制衬底350机械和电连接至导电柱148。例如，可以实施回流工艺以在导电柱148和衬底350之间形成焊料区域作为导电接头323。
下一步，在图13中，形成模制材料327以填充管芯221和衬底350之间以及模制材料337和衬底350之间的间隔。在一些实施例中，模制材料327与模制材料337不同。此外，在一些实施例中，模制材料327与底部填充材料227不同。
下一步，参照图14，在形成模制材料327之后，翻转半导体器件200，并且将衬底350的外部连接件325附接至由框架410支撑的带413。下一步，使载体101脱粘，并且使介电层110凹进以暴露导电焊盘115。之后，在暴露的导电焊盘115上方形成外部连接件153。
虽然未示出，但是可以实施切割以将半导体器件200与其它相邻半导体器件(未示出)分离。在切割之后，形成图15中示出的半导体器件200。
图16至图18示出了各个实施例中的与半导体器件200类似并且可以使用图10至图15中示出的类似的工艺形成的但具有修改的半导体器件的截面图。下面进一步讨论了图16至图18中的半导体器件的细节。
参照图16，示出了与半导体器件200类似但没有底部填充材料227的半导体器件200A的实施例。具体地，为了形成半导体器件200A，没有形成图11中的底部填充材料227。而是，在图1所示的工艺步骤中使用模制底部填充(MUF)材料作为模制材料337，从而使得模制材料337填充管芯221和再分布结构150之间的间隙，并且围绕管芯221和导电柱148，从而减少工艺时间和制造成本。在一些实施例中，模制材料337与模制材料327不同。
图17示出了半导体器件200B的另一实施例，半导体器件200B与图15中的半导体器件200类似，但是衬底350具有不同的结构。具体地，图17中的衬底350的芯310的仅一侧(例如，上侧)具有形成在其上的导电部件(例如，313)，并且不沿着芯310的另一侧(例如，下侧)形成导电部件。导电通孔317电连接至导电部件313并且延伸穿过芯310。虽然外部连接件325示出为位于图17中的导电柱148正上方，但是导电部件313(例如，导线)可以将电信号再分布至其它位置，并且因此外部连接件325可以设置在其它位置。
图18示出了半导体器件200C的另一实施例，半导体器件200C与图17中的半导体器件200B类似，但是在管芯221和再分布结构150之间没有底部填充材料227。在一些实施例中，图18中的模制材料337是MUF材料。在一些实施例中，模制材料337与模制材料327不同。虽然外部连接件325示出为位于图18中的导电柱148正上方，但是导电部件313可以将电信号再分布至其它位置，并且因此外部连接件325可以设置在其它位置。
图19至图22示出了根据实施例的处于各个制造阶段的半导体器件300的截面图。除非另有说明，否则图19至图22中相同的标号是指图1至图6A和/或图10至图15中相同的部分。例如，具有相同标号的组件可以由相同或类似的材料形成，并且可以使用相同或类似的形成方法形成。为了简单起见，可能不再重复细节。
如图19中示出的，在载体101上方形成可以是缓冲层的介电层103。在一些实施例中，介电层103由诸如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等的聚合物形成。在其它实施例中，介电层103由氮化物，诸如氮化硅；氧化物，诸如氧化硅、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)；等形成。可以通过诸如旋涂、化学汽相沉积(CVD)、层压等或它们的组合的合适的沉积工艺形成介电层103。
下一步，在介电层103上方形成导电柱148，诸如铜柱。通过粘合层105将一个或多个管芯221附接至介电层103，该粘合层105可以是合适的介电膜，诸如管芯附接膜(DAF)。图19也示出了管芯221的管芯连接件225以及管芯221的围绕管芯连接件225的介电层228(例如，聚合物层)。
下一步，在图20中，在介电层103上方的管芯221周围和导电柱148周围形成模制材料337。在形成模制材料337之后，可以实施诸如CMP的平坦化工艺来去除模制材料337的顶部以暴露管芯221的管芯连接件225。下一步，在管芯221、导电柱148和模制材料337上方形成再分布结构150。再分布结构150电连接至管芯221和导电柱148。
图20也示出了形成在再分布结构150上方并且电连接至再分布结构150的凸块下金属(UBM)结构146。在实施例中，UBM结构146包括三个导电材料层，诸如钛层、铜层和镍层。然而，诸如铬/铬-铜合金/铜/金的布置、钛/钛钨/铜的布置或铜/镍/金的布置的许多合适的材料和层的布置适用于形成UBM结构146。可以用于UBM结构146的任何合适的材料或材料层均完全旨在包括在本发明的范围内。一旦形成UBM结构146，则在UBM结构146上方形成诸如焊料凸块的外部连接件153。
现在参照图21，翻转图20中示出的半导体器件300，并且将外部连接件153附接至由框架410支撑的带413。下一步，将载体101从半导体器件300脱粘。之后，在介电层103中形成开口102。可以通过光刻和/或蚀刻工艺形成开口102，但是也可以使用诸如激光钻孔的其它合适的方法。如图21中示出的，开口102暴露导电柱148。
下一步，在图22中，将预制衬底350附接至导电柱148。在导电柱148和衬底350之间形成诸如焊料区域的导电接头323，以将衬底350机械和电连接至导电柱148。下一步，形成模制材料327以填充介电层103和衬底350之间的间隔。在一些实施例中，模制材料327与模制材料337不同。
虽然未示出，但是接下来可以实施切割工艺以将半导体器件300与在与半导体器件300相同的工艺步骤中形成的其它相邻半导体器件(未示出)分离，从而形成多个单独的半导体器件300。
图23示出了半导体器件300A的另一实施例，半导体器件300A与图22中的半导体器件300类似，但是衬底350具有不同的结构。具体地，图23中的衬底350的芯310的仅一侧(例如，上侧)具有形成在其上的导电部件(例如，313)，并且不沿着芯310的另一侧(例如，下侧)形成导电部件。导电通孔317电连接至导电部件313并且延伸穿过芯310。虽然外部连接件325示出为位于图23中的导电柱148正上方，但是导电部件313可以将电信号再分布至其它位置，并且因此外部连接件325可以设置在其它位置。
图24至图27示出了根据实施例的处于各个制造阶段的半导体器件400的截面图。除非另有说明，否则图24至图27中相同的标号是指图1至图6A和/或图10至图15中相同的部分。例如，具有相同标号的组件可以由相同或类似的材料形成，并且可以使用相同或类似的形成方法形成。为了简单起见，可能不再重复细节。
参照图24，通过粘合层104将预制衬底350附接至载体101。粘合层104可以是感光的并且可以通过在随后的载体脱粘工艺中对载体101照射例如紫外(UV)光而容易地从载体101脱离。例如，粘合层可以是由明尼苏达州圣保罗的3M公司制造的光热转换(LTHC)涂层。
如图24示出的，衬底350在介电层330中具有开口321并且在介电层320中具有开口321’。开口321将用于与再分布结构150(见图26)电连接，并且开口321’将用于形成外部连接件325(见图27)。
下一步，参照图25，在衬底350上方形成介电层322。介电层322可以包括诸如氧化硅、氮化硅、氮氧化硅等或它们的组合的合适的材料，并且可以是通过物理汽相沉积(PVD)、CVD或其它合适的方法形成。介电层322可以与下面的层共形。如图25中示出的，例如使用激光钻孔或其它合适的方法在介电层322中形成开口来暴露衬底350的导电部件315的部分。
下一步，在图26中，导电柱148形成在介电层322上方并且电连接至衬底350。如图26中示出的，导电通孔329形成在开口321(见图24)中并且电连接在导电柱148和衬底350之间。下一步，通过粘合层105(例如，DAF)将一个或多个管芯221的背侧附接至介电层322。管芯221的前侧上的管芯连接件225朝向远离衬底350。
下一步，在介电层322上方和管芯221/导电柱148周围形成模制材料337。可以实施诸如CMP的平坦化工艺，以实现导电柱148、模制材料337和管芯221之间的平坦上表面。在平坦化工艺之后，在模制材料337的上表面处暴露管芯连接件225。
下一步，在管芯221、导电柱148和模制材料337上方形成再分布结构150。再分布结构150机械地和电连接至管芯221和导电柱148。在UBM结构146上方形成外部连接件153，UBM结构146位于再分布结构150上方并且电连接至再分布结构150。
现在参照图27，翻转图26所示的半导体器件400，并且将外部连接件153附接至由框架410支撑的带413。下一步，将载体101从半导体器件400脱粘。在载体脱粘工艺之后去除粘合层104(见图26)。可以在载体脱粘工艺之后实施清洗工艺以去除开口321’(见图26)中和/或介电层320上方的残留物。
下一步，在开口312’(见图26)中形成诸如焊料凸块的外部连接件325，以连接至衬底350的导电部件。下一步，可以实施切割工艺(未示出)以将半导体器件400与相邻半导体器件分离。
图28示出了半导体器件400A的另一实施例，半导体器件400A与图27中的半导体器件400类似，但是衬底350具有不同的结构。具体地，图28中的衬底350的芯310的仅一侧(例如，上侧)具有形成在其上的导电部件(例如，313)，并且不沿着芯310的另一侧(例如，下侧)形成导电部件。导电通孔317电连接至导电部件313并且延伸穿过芯310。虽然外部连接件325示出为位于图28中的导电柱148正上方，但是导电部件313可以将电信号再分布至其它位置，并且因此外部连接件325可以设置在其它位置。
图29至图32示出了根据实施例的处于各个制造阶段的半导体器件500的截面图。除非另有说明，否则图29至图32中相同的标号是指图1至图6A和/或图10至图15中相同的部分。例如，具有相同标号的组件可以由相同或类似的材料形成，并且可以使用相同或类似的形成方法形成。为了简单起见，可能不再重复细节。
参照图29，在载体101上方形成再分布结构150。再分布结构150的形成方法与图1中的相同或类似，因此此处不再重复。
下一步，在图30中，将一个或多个管芯221附接至再分布结构150。在示出的实例中，管芯221的管芯连接件225通过焊料区域223连接至再分布结构150的导电焊盘147。一旦附接管芯221，则在管芯221和再分布结构150之间的间隙中形成底部填充材料227。下一步，在管芯221和底部填充材料227周围形成模制材料337。可以实施诸如CMP的平坦化工艺，以实现管芯221和模制材料337之间的共面上表面。在一些实施例中，模制材料337与底部填充材料227不同。
下一步，参照图31，通过粘合层328将预制衬底350附接至管芯221和模制材料337的背侧。粘合层328可以是诸如胶层、DAF等的合适的介电层。
如图31中示出的，管芯221和衬底350之间没有电连接，并且再分布结构150和衬底350之间没有电连接。在图29至图32示出的实施例中，衬底350用于增加半导体器件500的机械稳定性(例如，刚性)。此外，衬底350的导电部件(例如，313)用于平衡管芯221的相对侧(例如，前侧和背侧)上的金属密度(例如，铜密度)，以减少半导体器件500的翘曲。例如，可以实施模拟和/或实验以确定衬底350的导电部件的数量和位置以补偿由例如管芯221和再分布结构150之间的CTE失配引起的翘曲。
在一些实施例中，衬底350仅在芯310的一侧上具有导电部件(例如，313)。在芯310的另一侧上没有导电通孔317(见图4)或导电部件315(见图4)。因此，图31中的衬底的导电部件(例如，313)是伪金属图案。换句话说，图31的导电部件(例如，313)是电隔离的金属图案。在芯310的一侧上形成导电部件简化了设计，从而降低了成本。
下一步，在图32中，将半导体器件500的衬底350附接至由框架410支撑的带413，并且使载体101脱粘。之后，使再分布结构150的介电层110凹进以暴露导电焊盘115，并且在暴露的导电焊盘115上方形成外部连接件153。虽然未示出，但是可以实施切割以将半导体器件500与其它相邻半导体器件分离。
图29至图32的实施例的变型是可能的。例如，伪导电部件可以形成在芯310的下侧(见图32中虚线所示的导电部件313’)，但不形成在芯310的上侧上。在另一实施例中，伪导电部件可以形成在形成在芯310的上侧(例如，图32中的313)和下侧(例如，图32中的313’)上。这些和其它变型均完全旨在包括在本发明的范围内。
图33示出了半导体器件500A的另一实施例，半导体器件500A与图32中的半导体器件500类似，但是在管芯221和再分布结构150之间没有底部填充材料227。在一些实施例中，图33中的模制材料337是MUF材料。在一些实施例中，模制材料337与粘合层328不同。如上所述，伪导电部件313可以形成在芯310的上侧、下侧或上侧和下侧上。
图34至图37示出了根据实施例的处于各个制造阶段的半导体器件600的截面图。除非另有说明，否则图34至图37中相同的标号是指图1至图6A和/或图10至图15中相同的部分。例如，具有相同标号的组件可以由相同或类似的材料形成，并且可以使用相同或类似的形成方法形成。为了简单起见，可能不再重复细节。
参照图34，通过粘合层326将衬底350(可以是预制的)附接至载体101。粘合层326可以与图24中的粘合层104相同，因此此处不再重复。
衬底350用于与半导体器件500(见图32)中的衬底350相同的目的，并且因此包括诸如导电部件313的伪金属图案。在图33的实例中，仅在芯310的接触介电层320的一侧上形成伪金属图案。虽然未示出，但是伪金属图案可以仅形成在芯310的接触介电层330的另一侧上或形成在芯310的两侧上。这些和其它变型均完全旨在包括在本发明的范围内。
下一步，在图35中，通过粘合层105(例如，DAF)将一个或多个管芯221附接至衬底350。管芯221的具有管芯连接件225的前侧朝向远离衬底350。
下一步，在图36中，在衬底350上方和管芯221周围形成模制材料337。可以实施诸如CMP的平坦化工艺，以实现管芯221和模制材料337之间的共面上表面。下一步，在管芯221和模制材料337上方形成再分布结构150。再分布结构150电连接至管芯221。下一步，在电连接至再分布结构150的UBM结构146上方形成外部连接件153。
下一步，参照图37，将半导体器件600的外部连接件153附接至由框架410支撑的带413，使载体101脱粘，并且去除粘合层326。随后可以实施切割工艺以将半导体器件600与形成的其它相邻器件分离。
实施例可以实现许多优势。例如，与衬底350设置在管芯221和再分布结构150之间的半导体器件相比，本发明中的半导体器件(例如，100、200、300、400、500和600)在管芯221和外部连接件153之间具有更短的信号路径。具有更短的信号路径减少了信号延迟(例如，RC延迟)并且改进了半导体器件的性能。此外，通过将衬底350和再分布结构150定位在管芯221的相对侧上，可以实现金属密度的平衡，这减少了半导体器件(例如，100、200、300、400、500和600)的翘曲，而不管衬底350的导电部件是否是伪金属图案。
图38示出了根据一些实施例的制造半导体器件的方法的流程图。应该理解，图38所示的实施例方法仅仅是许多可能的实施例方法的实例。本领域普通技术人员将意识到许多变化、替换和修改。例如，可以添加、去除、替换、重新排列和重复图38中示出的各个步骤。
参照图38，在步骤1010中，在载体上方形成再分布结构，再分布结构具有位于再分布结构的远离载体的表面上的导电部件。在步骤1020中，在再分布结构的表面上方形成导电柱。在步骤1030中，将管芯附接至再分布结构的邻近导电柱的表面，其中，管芯的管芯连接件电连接至再分布结构的导电部件。在步骤1040中，通过导电接头将预制衬底附接至导电柱，其中，导电接头位于导电柱上并且包括与导电柱不同的材料，其中，导电接头和导电柱将再分布结构电连接至预制衬底。
在实施例中，方法包括在载体上方形成再分布结构，再分布结构具有位于再分布结构的远离载体的表面上的导电部件；在再分布结构的表面上方形成导电柱；将管芯附接至再分布结构的邻近导电柱的表面，其中，管芯的管芯连接件电连接至再分布结构的导电部件；以及通过导电接头将预制衬底附接至导电柱，其中，导电接头位于导电柱上并且包括与导电柱不同的材料，其中，导电接头和导电柱将再分布结构电连接至预制衬底。在实施例中，导电接头是焊料区域。在实施例中，该方法还包括在附接预制衬底之后，将半导体器件附接至预制衬底的远离再分布结构的表面。在实施例中，导电柱的远离再分布结构的表面比管芯的远离再分布结构的表面更接近再分布结构。在实施例中，该方法还包括在附接预制衬底之后，使用第一模制材料填充预制衬底和再分布结构之间的间隔。在实施例中，该方法还包括在附接管芯之后并且在附接预制衬底之前，在管芯和再分布结构之间的间隙中形成与第一模制材料不同的第二模制材料。在实施例中，该方法还包括在附接管芯之后并且在附接预制衬底之前，在管芯周围和导电柱周围形成第一模制材料；以及在附接预制衬底之后，使用与第一模制材料不同的第二模制材料填充第一模制材料和预制衬底之间的间隔，其中，导电接头由第二模制材料围绕。在实施例中，该方法还包括从再分布结构去除载体；使再分布结构的介电层凹进，其中，介电层的凹进暴露再分布结构的导电部件；以及在暴露的导电部件上方形成导电凸块。
在实施例中，方法包括在载体上方形成再分布结构，再分布结构具有位于再分布结构的远离载体的表面上的导电焊盘；将管芯的管芯连接件接合至导电焊盘；在载体上方和管芯周围形成模制材料；通过粘合层将预制衬底附接至模制材料和管芯，预制衬底具有电隔离的伪金属部件；在附接预制衬底之后，使再分布结构的介电层凹进以暴露再分布结构的导电部件；以及在暴露的导电部件上形成导电凸块。在实施例中，管芯的管芯连接件通过焊料区域接合至导电焊盘。在实施例中，预制衬底包括介电芯，并且伪金属部件设置在介电芯的至少一侧上。在实施例中，方法还包括在附接预制衬底之后并且在使介电层凹进之前：将预制衬底附接至带；以及将载体从再分布结构脱粘。
在实施例中，半导体器件包括嵌入在第一模制材料内的第一管芯，第一管芯具有位于第一管芯的第一侧处的管芯连接件；嵌入在第一模制材料内并且与第一管芯横向间隔开的第一导电柱；位于第一管芯的第一侧处的再分布结构，通过焊料接头将管芯连接件电连接至再分布结构的导电部件，导电部件位于再分布结构的面向第一管芯的表面上；位于第一管芯的与第一侧相对的第二侧处的衬底；以及插入在第一导电柱和衬底之间的第一焊料区域，其中，第一焊料区域和第一导电柱将再分布结构电连接至衬底。在实施例中，第一导电柱的远离再分布结构的表面比第一管芯的第二侧更接近再分布结构。在实施例中，第一模制材料从再分布结构连续延伸至衬底，并且其中，第一焊料区域嵌入在第一模制材料内。在实施例中，半导体器件还包括位于第一管芯和再分布结构之间的底部填充材料，其中，底部填充材料与第一模制材料不同。在实施例中，半导体器件还包括位于第一模制材料和衬底之间的第二模制材料，其中，第二模制材料与第一模制材料不同。在实施例中，第一导电柱的上表面与第一管芯的第二侧和第一模制材料的上表面齐平。在实施例中，衬底包括介电芯、延伸穿过介电芯的导电通孔以及位于介电芯的至少一侧上的导线。在实施例中，半导体器件还包括位于衬底的远离第一管芯的侧上的焊料凸块。
上面概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解，它们可以容易地使用本发明作为基础来设计或修改用于实施与本人所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。

Claims (4)

1.一种形成半导体器件的方法，包括：
在载体上方形成再分布结构，所述再分布结构具有位于所述再分布结构的远离所述载体的表面上的导电焊盘；
将管芯的管芯连接件接合至所述导电焊盘；
在所述载体上方和所述管芯周围形成模制材料；
通过粘合层将预制衬底附接至所述模制材料和所述管芯，所述预制衬底具有电隔离的伪金属部件；
在附接所述预制衬底之后，使所述再分布结构的介电层凹进以暴露所述再分布结构的导电部件；以及
在暴露的导电部件上形成导电凸块，
其中，所述模制材料从所述管芯连续延伸至所述模制材料的距离所述管芯最远的边界而没有任何界面，
其中，整个所述预制衬底不包含任何电连接件，
其中，所述预制衬底包括介电芯，并且所述伪金属部件设置在所述介电芯的远离所述管芯的一侧上。
2.根据权利要求1所述的方法，其中，所述伪金属部件嵌入在所述预制衬底内。
3.根据权利要求1所述的方法，其中，所述模制材料包括围绕管芯的第一模制材料和与所述第一模制材料不同的第二模制材料。
4.根据权利要求1所述的方法，还包括，在附接所述预制衬底之后并且在使所述介电层凹进之前：
将所述预制衬底附接至带；以及
将所述载体从所述再分布结构脱粘。
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