TW201907500A - 半導體元件及其形成方法 - Google Patents

半導體元件及其形成方法 Download PDF

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TW201907500A
TW201907500A TW107123348A TW107123348A TW201907500A TW 201907500 A TW201907500 A TW 201907500A TW 107123348 A TW107123348 A TW 107123348A TW 107123348 A TW107123348 A TW 107123348A TW 201907500 A TW201907500 A TW 201907500A
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Taiwan
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conductive
die
redistribution structure
substrate
molding material
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TW107123348A
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TWI713129B (zh
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鄭心圃
許峯誠
劉獻文
林柏堯
陳碩懋
莊博堯
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台灣積體電路製造股份有限公司
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Abstract

一種形成半導體元件的方法，包含：在載體上方形成重佈線結構，所述重佈線結構在重佈線結構之遠離載體的表面上具有導電特徵；在重佈線結構之表面上方形成導電柱；將晶粒貼合至與導電柱鄰近之重佈線結構的表面，其中晶粒之晶粒連接件電性耦接至重佈線結構之導電特徵；以及將預製基底經由導電接頭貼合至導電柱，其中導電接頭在導電柱上且包括與導電柱不同的材料，其中導電接頭及導電柱將重佈線結構電性耦接至預製基底。

Description

半導體元件及其形成方法
半導體行業由於各種電子組件（例如電晶體、二極體、電阻器、電容器等）之積體密度的持續改良而經歷快速增長。在大多數情況下，積體密度之此種改良來自於最小特徵尺寸之反覆減小，此允許將更多組件整合至給定區域中。隨著近年來對甚至更小的電子裝置之需求增長，對半導體晶粒之更小及更具創造性之封裝技術的需要也隨著增長。
此等封裝技術之實例為疊層封裝（Package-on-Package，POP）技術。在疊層封裝中，頂部半導體封裝堆疊於底部半導體封裝之頂部上，以提供高位準之整合及組件密度。另一實例為多晶片模組（Multi-Chip-Module，MCM）技術，其中多個半導體晶粒封裝於一個半導體封裝中，以提供具有整合功能之半導體元件。
進階封裝技術之高整合位準能夠產生具有增強型功能及小佔據面積的半導體元件，此有利於諸如行動電話、平板電腦以及數位音樂播放器之小外觀尺寸元件。另一優點為連接半導體封裝內之互操作部件的導電路徑之長度縮短。此改良半導體元件之電學效能，因為電路之間的內連線之較短佈線產生較快訊號傳播以及減小的雜訊及串話。
以下揭示內容提供用於實施本發明之不同特徵的許多不同實施例或實例。下文描述組件及配置之特定實例以簡化本發明。當然，此等組件及配置僅為實例且並不意欲為限制性的。舉例而言，在以下描述中，第一構件於第二構件上方或上之形成可包含第一構件及第二構件直接接觸地形成之實施例，且亦可包含其他構件可在第一構件與第二構件之間形成使得第一構件與第二構件可不直接接觸之實施例。
另外，在本文中為了易於描述，可使用諸如「在...下方」、「下方」、「下部」、「在...上方」、「上部」以及其類似術語之空間相對術語來描述如在圖式中所說明的一個元件或構件與另一元件或構件的關係。除圖式中所描繪之定向外，空間相對術語意欲涵蓋元件在使用或操作中之不同定向。設備可以其他方式定向（旋轉90度或處於其他定向）且本文中所使用之空間相對描述詞可同樣相應地進行解釋。
半導體元件及形成半導體元件之方法提供於不同實施例中。在一些實施例中，半導體元件包含重佈線結構、一或多個半導體晶粒以及基底，其中半導體晶粒之前側貼合至重佈線結構，基底貼合至一或多個半導體晶粒之背側。在一些實施例中，基底包含一或多個用於重新分配電訊號之重佈線層，且電性耦接至重佈線結構及/或一或多個半導體晶粒。在其他實施例中，基底包含電性隔離之虛設金屬圖案。貼合至一或多個半導體晶粒之背側的基底可有助於使半導體晶粒之兩側（例如前側及背側）上的金屬密度平衡，藉此減少半導體元件之翹曲。
圖1至圖5、圖6A以及圖6B說明根據一實施例在各個製造階段上之半導體元件100的橫截面視圖。在圖1中，重佈線結構150形成於載體101上方。重佈線結構150包括在一或多個介電層中形成的導電特徵（例如導線及通孔）。導電柱149形成於重佈線結構150之上部表面上方且電性耦接至重佈線結構150。
載體101可由諸如矽、聚合物、聚合物複合物、金屬箔、陶瓷、玻璃、玻璃環氧樹脂、氧化鈹、膠帶之材料或用於結構支撐的其他適合之材料製成。重佈線結構150形成於載體101上方。重佈線結構150包括諸如一或多層導線（例如導線113、導線123）及通孔（例如通孔125、通孔145）之導電特徵，以及一或多個介電層（例如介電層107、介電層110、介電層120、介電層130、介電層140）。在一些實施例中，一或多個介電層107/介電層110/介電層120/介電層130/介電層140是由諸如聚苯并噁唑（polybenzoxazole；PBO）、聚醯亞胺、苯并環丁烯（benzocyclobutene；BCB）或類似者之聚合物形成。在其他實施例中，介電層107/介電層110/介電層120/介電層130/介電層140是由諸如氮化矽之氮化物、諸如氧化矽之氧化物、磷矽酸鹽玻璃（phosphosilicate glass；PSG）、硼矽酸鹽玻璃（borosilicate glass；BSG）、摻硼磷矽酸鹽玻璃（boron-doped phosphosilicate glass；BPSG）或類似者形成。一或多個介電層107/介電層110/介電層120/介電層130/介電層140可藉由任何可接受的沈積方法，諸如旋轉塗佈、化學氣相沈積（chemical vapor deposition；CVD）、疊層、類似者或其組合形成。
在一些實施例中，重佈線結構150之導電特徵包括由諸如銅、鈦、鎢、鋁或類似者之合適的導電材料形成之導線（例如導線113、導線123）、導通孔（例如導通孔125、導通孔145）。導電特徵亦可包含用於連接至電子組件或電子裝置（參見例如圖2）之導電墊（例如導電墊147）。導通孔115隨後暴露（參見例如圖5）且用作連接至電子組件或電子裝置之導電墊，由此亦可被稱作導電墊115。在一些實施例中，導線113及導電墊115藉由以下來形成：在介電層110中形成開口，在介電層110上方且在開口中形成晶種層（未圖示），利用所設計圖案在晶種層上方形成圖案化光阻（未圖示），將導電材料鍍覆（例如電鍍或無電電鍍）於所設計圖案中及晶種層上方，以及移除光阻及晶種層上未形成導電材料之部分。
應注意，在圖1之所說明實施例中，可充當緩衝層之介電層107是在介電層110形成之前形成於載體101上方。在其他實施例中，介電層107不在介電層110之前形成，且實際上是形成為介電層110之部分。換言之，圖1中所說明之介電層107及介電層110可為以相同沈積方法形成之一個連續的介電層110，在此情況下，介電層110中之開口並未延伸穿過介電層110，由此介電層110之部分設置於導電墊115之底部表面與載體101之間。
在一些實施例中，黏著層（未圖示）是在重佈線結構150形成之前沈積或疊層在載體101上方。黏著層可為感光性的且可藉由例如在後續載體剝離（de-bonding）方法中在載體101上照射紫外線（ultra-violet，UV）光而易於自載體101分離。舉例而言，黏著層可為由明尼蘇達州聖保羅之3M公司（3M Company of St. Paul, Minnesota）製備的光-熱轉換（light-to-heat-conversion；LTHC）塗層。
導線113及導電墊115形成之後，其他介電層及其他導電特徵可藉由執行如上文所描述之用於形成介電層110及導電特徵（例如導線113及導電墊115）之類似處理形成。介電層110上方之通孔（例如通孔125、通孔145）電性耦接至對應的下方導電特徵。圖1亦說明形成於重佈線結構150之上部表面上方（例如介電層140之上部表面上方）的導電墊147，其可用於連接至例如半導體晶粒221（參見圖2）。儘管在圖1中說明了四個介電層，但多於或少於四個介電層可用於重佈線結構150。
仍參考圖1，導電柱149形成於重佈線結構150上方。導電柱149可藉由以下來形成：在重佈線結構150上方形成晶種層；在晶種層上方形成圖案化光阻，其中圖案化光阻中之開口中之每一者對應於待形成之導電柱149之位置；使用例如電鍍或無電電鍍以諸如銅之導電材料填充開口；使用例如灰化製程或剝除（stripping）製程移除光阻；以及移除晶種層上未形成導電柱149之部分。應注意，在圖1之實例中，導電柱149之高度H1 形成得小，使得導電柱149之上部表面低於（例如更接近重佈線結構150）隨後貼合至重佈線結構150的半導體晶粒221之上部表面（參見圖2）。
接著，在圖2中，一或多個半導體晶粒221（亦可被稱作晶粒或積體電路（integrated circuit；IC）晶粒）機械且電性耦接至重佈線結構150之上部表面上的導電墊147。半導體晶粒221之導電凸塊225（亦可被稱作晶粒連接件）可為銅柱或其他合適的連接件，其經由導電區223機械且電性耦接至導電墊147。在一些實施例中，導電區223是焊料區（例如焊料凸塊）。
在黏附至重佈線結構150之前，晶粒221可根據可應用的製造方法處理以在晶粒221中形成積體電路。舉例而言，晶粒221可各自包含諸如摻雜矽或未摻雜矽之半導體基底或絕緣層上半導體（semiconductor-on-insulator；SOI）基底之主動層。半導體基底可包含其他半導體材料，諸如鍺；化合物半導體，包含碳化矽、砷化鎵、磷化鎵、氮化鎵、磷化銦、砷化銦及/或銻化銦；合金半導體，包含矽鍺（SiGe）、磷化鎵砷（GaAsP）、砷化銦鋁（AlInAs）、砷化鎵鋁（AlGaAs）、砷化銦鎵（GaInAs）、磷化銦鎵（GaInP）及/或磷砷化銦鎵（GaInAsP）；或其組合。亦可使用其他基底，諸如多層基底或梯度基底（gradient substrate）。諸如電晶體、二極體、電容器、電阻器等的元件可形成於半導體基底中及/或形成於半導體基底上，且可藉由例如半導體基底上的一或多個介電層中之金屬化圖案所形成之互連結構互連，以形成積體電路。
晶粒221更包括外部連接件連接之襯墊（未圖示），諸如鋁墊。襯墊在可被稱作晶粒221之主動側或前側上。鈍化膜（未圖示）形成於晶粒221上以及襯墊之部分上。開口穿過鈍化膜至襯墊。晶粒連接件225，諸如導電柱（例如包括諸如銅之金屬）在穿過鈍化膜之開口中，且機械且電性耦接至對應襯墊。晶粒連接件225可藉由例如鍍覆或類似者形成。晶粒連接件225電性耦接至晶粒221之積體電路。
介電材料（圖2中未展示，參見例如圖19中之介電層228）形成於晶粒221之主動側上，諸如鈍化膜及/或晶粒連接件225上。介電材料側向包封晶粒連接件225，且介電材料與對應的晶粒221側向上具有共同邊界。介電材料可為：聚合物，諸如聚苯并噁唑（PBO）、聚醯亞胺、苯并環丁烯（BCB）或類似者；氮化物，諸如氮化矽或類似者；氧化物，諸如氧化矽、磷矽酸鹽玻璃（PSG）、硼矽酸鹽玻璃（BSG）、摻硼磷矽酸鹽玻璃（BPSG）或類似者；或其組合，且可例如藉由旋轉塗佈、疊層、CVD或類似者形成。
如圖2中所說明，在將晶粒221貼合至重佈線結構150之後，形成底填充材料227以填充半導體晶粒221與重佈線結構150之間的間隙。底填充材料227亦可填充或部分填充半導體晶粒221之間的間隙以及導電柱149與半導體晶粒221之間的間隙。底填充材料227之實例材料包含但不限於聚合物及其他合適的非導電材料。底填充材料227可使用例如針或噴射分配器分配於半導體晶粒221與重佈線結構150之間的間隙中。可執行固化製程以固化底填充材料227。
儘管圖2中說明了兩個晶粒221，但多於或少於兩個晶粒221可用於形成半導體元件100。另外，儘管說明導電柱149是沿半導體元件100之周邊形成，但導電柱149可形成於晶粒221之間。此等及其他變化全部意欲包含於本發明之範疇內。
接著，在圖3中，預製基底350藉由導電接頭323貼合至導電柱149。在一些實施例中，基底350為印刷電路板（printed circuit board；PCB）。在其他實施例中，基底350為中介物（interposer）。
在圖3之所說明實施例中，基底350包含芯體310，其由諸如樹脂或纖維玻璃之介電材料形成。舉例而言，芯體310可包含雙馬來亞醯胺三嗪（bismaleimide triazine；BT）樹脂、FR-4（由編織玻璃纖維布與環氧樹脂接合劑組成之耐火的複合材料）、陶瓷、玻璃、塑膠、膠帶、膜或其他支撐材料。諸如銅線及/或銅墊之導電特徵313及導電特徵315形成於芯體310之相對側上，且可充當重佈線層以將電訊號自基底350之第一位置重新分配至基底350之第二位置。導通孔317延伸穿過芯體310，且電性耦接至導電特徵313/導電特徵315。圖3亦說明芯體310之上部表面上及導電特徵313上方之介電層320（例如阻焊層）。開口可形成於介電層320中，所述開口暴露導電特徵313之部分。諸如焊料凸塊之外部連接件325可形成於開口中且電性耦接至導電特徵313。外部連接件325可用於將基底350連接至另一元件，諸如記憶體晶片。圖3另外說明在芯體310之下部表面上及導電特徵315上方之介電層330（例如阻焊層）。開口形成於介電層330中，所述開口暴露導電特徵315之部分。在所說明之實施例中，基底350並不具有主動組件（例如電晶體）。
在一些實施例中，導電接頭323為焊料區。舉例而言，焊料膏可形成於導電柱149（例如銅柱）上及/或基底350之對應的經暴露導電特徵315上；基底350藉由焊料膏貼合至導電柱149；以及接著執行回焊製程以使焊料膏熔化以形成焊料區323。因此，在一些實施例中，焊料區323自導電柱149穿過介電層330延伸至基底350之導電特徵315。在圖3之所說明實施例中，焊料區323形成之後，基底350之下部表面在晶粒221之上部表面上方且並不接觸晶粒221。
圖3中之基底350之結構是出於說明目的且非限制性的。基底350可具有其他結構。舉例而言，基底350之芯體310可以不是如圖3中所說明之單層芯體，實際上，芯體310可包括多個介電層，且多層導線及/或通孔可形成於多個介電層中。基底350之此等及其他變化全部意欲包含於本發明之範疇內。
接著，在圖4中，形成模製材料327以填充基底350與晶粒221/重佈線結構150之間的空隙。作為實例，模製材料327可包括環氧樹脂、有機聚合物、添加或不添加二氧化矽基或玻璃填充劑之聚合物，或其他材料。在一些實施例中，模製材料327包括在應用時為凝膠型液體之液體模製化合物（liquid molding compound；LMC）。模製材料327在應用時亦可包括液體或固體。替代地，模製材料327可包括其他絕緣及/或包封材料。在一些實施例中，使用晶圓級模製製程來應用模製材料327。模製材料327可使用例如壓縮模製、轉移模製或其他方法來模製。
接著，在一些實施例中，使用固化製程來固化模製材料327。固化製程可包括使用退火製程或其他加熱製程在預定時間段將模製材料327加熱至預定溫度。固化製程亦可包括紫外線（UV）曝光製程、紅外線（infrared；IR）能量曝光製程、其組合或其與加熱製程之組合。可替代地，可使用其他方法來固化模製材料327。在一些實施例中，不包含固化製程。在所說明之實施例中，模製材料327不同於底填充材料227。
接著，在圖5中，翻轉半導體元件100，且外部連接件325貼合至由支架410支持的膠帶413。膠帶413可為在後續處理中用於將半導體元件100保持在原位的分割帶，其可為黏著劑。接著，載體101經由剝離製程而自半導體元件100分離（剝離）。剝離製程可使用任何合適之方法，諸如蝕刻、磨光以及機械剝落（peel off）來移除載體101。在諸如LTHC膜之黏著層使用於載體101與重佈線結構150之間的實施例中，載體101藉由在載體101之表面上方照射雷射或UV光來剝離。雷射或UV光破壞接合至載體101之黏著層的化學接合，且載體101接著可易於分離。
接著，使介電層110（或介電層107，若形成）凹陷以暴露導電墊115。在一些實施例中，蝕刻製程，諸如化學機械研磨（chemical mechanical polish；CMP）製程、類似製程或其組合可用於暴露導電墊115。在其他實施例中，雷射鑽孔製程、微影及/或蝕刻製程或類似者可用於暴露導電墊115。此後，外部連接件153形成於導電墊115上方。在一些實施例中，外部連接件153為諸如微凸塊之導電凸塊，且可包括諸如錫之材料或諸如銀或銅之其他合適的材料。在外部連接件153為錫焊料凸塊（solder bump）之實施例中，外部連接件153可藉由首先經由諸如蒸鍍、電鍍、印刷、焊料轉移或植球（ball placement）之任何合適的方法形成錫層來形成。一旦錫層已形成於所述結構上，則執行回焊以便將材料塑形為具有約例如20微米直徑之所要凸塊形狀，但可替代地使用任何合適之尺寸。
然而，如於本領域具通常知識者將認識到，雖然上文已將外部連接件153描述為微凸塊，但此等者僅意欲為例示性的且不意欲限制實施例。相反，可替代地使用任何合適類型之外部連接件，諸如受控塌陷晶粒連接（controlled collapse chip connection；C4）凸塊、銅柱、銅層、鎳層、無鉛（lead free；LF）層、化學鍍鎳鈀浸金（electroless nickel electroless palladium immersion gold；ENEPIG）層、Cu/LF層、Sn/Ag層、Sn/Pb、此等之組合或類似者。用於形成外部連接件之任何合適的外部連接件及任何合適的方法可用於外部連接件153，且所有此類外部連接件全部意欲包含於實施例之範疇內。
儘管未展示，但分割處理可在外部連接件153形成之後執行以將半導體元件100自以與半導體元件100相同的處理步驟形成之其他鄰近半導體元件（未圖示）分隔開，藉此形成多個個別半導體元件。圖6A說明分割處理之後的半導體元件100。
接著，如圖6B中所展示，諸如記憶體元件的半導體元件500可貼合至圖6A中所展示之半導體元件100以形成圖6B中之半導體元件100，藉此形成具有疊層封裝（PoP）結構之半導體封裝。如圖6B中所說明，半導體元件500具有基底510及貼合至基底510之上部表面的一或多個半導體晶粒517。
在一些實施例中，基底510包含矽、砷化鎵、絕緣層上矽（silicon on insulator；「SOI」）或其他類似材料。在一些實施例中，基底510為多層電路板。在一些實施例中，基底510包含雙馬來亞醯胺三嗪（BT）樹脂、FR-4（由編織玻璃纖維布與耐火的環氧樹脂接合劑形成之複合材料）、陶瓷、玻璃、塑膠、膠帶、膜或其他支撐材料。基底510可包含形成於基底510中/基底510上之導電特徵（例如導線及通孔，未圖示）。如圖6B中所說明，基底510具有形成於基底510之上部表面及下部表面上的導電墊513，其中導電墊513電性耦接至基底510之導電特徵。一或多個半導體晶粒517藉由例如接線515電性耦接至導電墊513。可包括環氧樹脂、有機聚合物、聚合物或類似者之模製材料530形成於基底510上方及半導體晶粒517周圍。半導體元件500由導電接頭525電性及機械耦接至基底350，其可藉由接合半導體元件500之外部連接件與基底350之外部連接件325而形成。在一些實施例中，導電接頭525包括焊料區、導電柱（例如銅柱）或任何其他合適之導電接頭。儘管未說明，但半導體元件500可以如圖6B中所說明之類似方法與其他實施例元件，諸如下文中論述之半導體元件200、半導體元件300以及半導體元件400接合以形成各種疊層封裝。
圖7至圖9說明在各種實施例中之與半導體元件100類似且可使用如圖1至圖6A中所說明之類似處理形成（但具有修改）的半導體元件之橫截面視圖。舉例而言，在一個處理步驟中，模製底填充料（molded underfill；MUF）可用於填充晶粒221與重佈線結構150之間的間隙，且用於填充重佈線結構150/晶粒221與基底350之間的空隙（參見圖7及圖9），藉此減少處理時間及成本。作為另一實例，可簡化基底350之設計以在芯體310之一側而非芯體310之兩側上具有重佈線層（例如導線）。下文將論述圖7至圖9中之半導體元件之其他細節。
參考圖7，展示與如圖6A中所說明之半導體元件100類似但不具有底填充材料227之實施例半導體元件100A。特定而言，為形成半導體元件100A，底填充材料227未形成於圖2之處理步驟中。實際上，在基底350貼合至導電柱149（參見圖3）之後，在圖4中所展示之處理步驟中，模製底填充料（MUF）材料用作模製材料327以填充晶粒221與重佈線結構150之間的間隙以及填充重佈線結構150/晶粒221與基底350之間的空隙，由此在一個處理步驟中填充上文所描述之間隙及空隙，藉此減少處理時間及製造成本。
在一些實施例中，圖7之MUF材料327不同於圖4之底填充材料227，此是因為MUF材料327中之填充劑比底填充材料227中之填充劑更細（例如，具有較小尺寸）從而有助於MUF流入小的間隙中。另外，MUF材料亦可具有比底填充材料227高的填充劑百分比以控制（例如降低）MUF材料之熱膨脹係數（coefficient of thermal expansion；CTE）。
圖8說明與圖6A中之半導體元件100類似但具有不同結構的基底350之另一實施例半導體元件100B。特定而言，圖8中之基底350之芯體310的僅一側（例如上部側）具有在其上所形成之導電特徵（例如導電特徵313），且無導電特徵沿芯體310之另一側（例如下部側）形成。導通孔317電性耦接至導電特徵313且延伸穿過芯體310。
圖9說明與圖8中之半導體元件100B類似但在晶粒221與重佈線結構150之間不具有底填充材料227之另一實施例半導體元件100C。在一些實施例中，圖9中之模製材料327為MUF材料。
圖10至圖15說明根據一實施例在各個製造階段上之半導體元件200的橫截面視圖。除非另外指明，否則圖10至圖15中之相同標號是指圖1至圖6A中之相同部件。舉例而言，具有相同標號之組件可由相同或類似材料形成，且可使用相同或類似的形成方法形成。為簡單起見，細節可能不會重複。
首先參考圖10，重佈線結構150形成於載體101上方。導電柱148形成於重佈線結構150上方，且機械及電性耦接至重佈線結構150。在一些實施例中，導電柱148包括與圖1中之導電柱149相同的材料且可使用相同方法形成，但具有較高高度H2 。高度H2 可等於或大於晶粒221之上部表面（參見圖11）與重佈線結構150之上部表面之間的距離。
接著，在圖11中，一或多個晶粒221貼合至重佈線結構150之導電墊147。舉例而言，晶粒221之晶粒連接件225藉由執行回焊製程經由焊料區223耦接至導電墊147。在將晶粒221貼合至重佈線結構150之後，形成底填充材料227以填充晶粒221與重佈線結構150之間的間隙。
接著，模製材料337形成於晶粒221、導電柱148以及底填充材料227周圍之重佈線結構150之上部表面上方。作為實例，模製材料337可包括環氧樹脂、有機聚合物、添加或不添加二氧化矽基或玻璃填充劑之聚合物，或其他材料。在一些實施例中，模製材料337包括在應用時為凝膠型液體之液體模製化合物（LMC）。模製材料337在應用時亦可包括液體或固體。替代地，模製材料337可包括其他絕緣及/或包封材料。在一些實施例中，使用晶圓級模製製程來應用模製材料337。模製材料337可使用例如壓縮模製、轉移模製或其他方法來模製。
接著，在一些實施例中，使用固化製程來固化模製材料337。固化製程可包括使用退火製程或其他加熱製程在預定時間段將模製材料337加熱至預定溫度。固化製程亦可包括紫外線（UV）曝光製程、紅外線（IR）能量曝光製程、其組合或其與加熱製程之組合。可替代地，可使用其他方法來固化模製材料337。在一些實施例中，不包含固化製程。在一些實施例中，模製材料337不同於底填充材料227。
在模製材料337形成之後，可執行諸如CMP之平坦化製程以將模製材料337之上部部分移除從而在晶粒221、導電柱148以及模製材料337之間獲得共面的上部表面。平坦化製程亦可移除導電柱148之頂部部分及/或晶粒221之頂部部分（例如薄化晶粒221）。
接著參考圖12，預製基底350由導電接頭323機械且電性耦接至導電柱148。舉例而言，可執行回焊製程以在導電柱148與基底350之間形成作為導電接頭323之焊料區。
接著，在圖13中，形成模製材料327以填充晶粒221與基底350之間以及模製材料337與基底350之間的空隙。在一些實施例中，模製材料327不同於模製材料337。另外，在一些實施例中，模製材料327不同於底填充材料227。
接著參考圖14，模製材料327形成之後，翻轉半導體元件200，且基底350之外部連接件325貼合至由支架410支持的膠帶413。接著，將載體101剝離，且使介電層110凹陷以暴露導電墊115。接著，外部連接件153形成於暴露的導電墊115上方。
儘管未展示，但可執行分割以將半導體元件200與其他鄰近半導體元件（未圖示）分隔開。分割之後，形成如圖15中所說明之半導體元件200。
圖16至圖18說明在各種實施例中之與半導體元件200類似且可使用如圖10至圖15中所說明之類似處理形成（但具有修改）的半導體元件之橫截面視圖。下文將論述圖16至圖18中之半導體元件之其他細節。
首先參考圖16，展示與半導體元件200類似但不具有底填充材料227之實施例半導體元件200A。特定而言，為形成半導體元件200A，底填充材料227未在圖11中形成。實際上，在圖1所展示之處理步驟中，模製底填充料（MUF）材料用作模製材料337，使得模製材料337填充晶粒221與重佈線結構150之間的間隙，且包圍晶粒221及導電柱148，藉此減少處理時間及製造成本。在一些實施例中，模製材料337不同於模製材料327。
圖17說明與圖15中之半導體元件200類似但具有不同結構的基底350之另一實施例半導體元件200B。特定而言，圖17中之基底350之芯體310的僅一側（例如上部側）具有在其上形成之導電特徵（例如導電特徵313），且無導電特徵沿芯體310之另一側（例如下部側）形成。導通孔317電性耦接至導電特徵313且延伸穿過芯體310。儘管外部連接件325說明為圖17中之導電柱148的正上方，但導電特徵313（例如導線）可將電訊號重新分配至其他位置，且因此外部連接件325可設置於其他位置處。
圖18說明與圖17中之半導體元件200B類似但在晶粒221與重佈線結構150之間不具有底填充材料227之另一實施例半導體元件200C。在一些實施例中，圖18中之模製材料337為MUF材料。在一些實施例中，模製材料337不同於模製材料327。儘管外部連接件325說明為圖18中之導電柱148的正上方，但導電特徵313可將電訊號重新分配至其他位置，且因此外部連接件325可設置於其他位置處。
圖19至圖22說明根據一實施例在各個製造階段上之半導體元件300的橫截面視圖。除非另外指明，否則圖19至圖22中之相同標號是指圖1至圖6A及/或圖10至圖15中之相同部件。舉例而言，具有相同標號之組件可由相同或類似材料形成，且可使用相同或類似的形成方法形成。為簡單起見，細節可能不會重複。
如圖19中所說明，可為緩衝層之介電層103形成於載體101上方。在一些實施例中，介電層103由諸如聚苯并噁唑（PBO）、聚醯亞胺、苯并環丁烯（BCB）或類似者之聚合物形成。在其他實施例中，介電層103是由諸如氮化矽之氮化物、諸如氧化矽之氧化物、磷矽酸鹽玻璃（PSG）、硼矽酸鹽玻璃（BSG）、摻硼磷矽酸鹽玻璃（BPSG）或類似者形成。介電層103可藉由合適之沈積方法，諸如旋轉塗佈、化學氣相沈積（CVD）、疊層、類似者或其組合形成。
接著，諸如銅柱之導電柱148形成於介電層103上方。一或多個晶粒221藉由黏著層105貼合至介電層103，其可為合適之介電膜，諸如晶粒貼合膜（die attaching film；DAF）。圖19亦說明晶粒221之晶粒連接件225，及包圍晶粒連接件225之晶粒221的介電層228（例如聚合物層）。
接著，在圖20中，模製材料337形成於晶粒221周圍以及導電柱148周圍之介電層103上方。模製材料337形成之後，可執行諸如CMP之平坦化製程以將模製材料337之頂部部分移除從而暴露晶粒221之晶粒連接件225。接著，重佈線結構150形成於晶粒221、導電柱148以及模製材料337上方。重佈線結構150電性耦接至晶粒221及導電柱148。
圖20亦說明凸塊下金屬（under bump metallization；UBM）結構146，其形成於重佈線結構150上方且電性耦接至所述重佈線結構150。在一實施例中，UBM結構146包括三種導電材料層，諸如鈦層、銅層以及鎳層。然而，存在多種合適之材料及層配置，諸如鉻/鉻銅合金/銅/金配置、鈦/鈦鎢/銅配置或銅/鎳/金配置，所述材料及層配置適合於形成UBM結構146。可用於UBM結構146之任何合適之材料或材料層全部意欲包含於本發明之範疇內。一旦形成UBM結構146，則諸如焊料凸塊的外部導體153形成於UBM結構146上方。
現參考圖21，翻轉圖20中所說明之半導體元件300，且外部連接件153貼合至由支架410支持的膠帶413。接著，載體101自半導體元件300剝離。此後，開口102形成於介電層103中。開口102可藉由微影及/或蝕刻製程形成，但亦可使用其他合適之方法，諸如雷射鑽孔。如圖21中所說明，開口102暴露導電柱148。
接著，在圖22中，將預製基底350貼合至導電柱148。導電接頭323，諸如焊料區形成於導電柱148與基底350之間以將基底350機械及電性耦接至導電柱148。接著，形成模製材料327以填充介電層103與基底350之間的空隙。在一些實施例中，模製材料327不同於模製材料337。
儘管未展示，但可執行分割處理，緊接著將半導體元件300自以與半導體元件300相同的處理步驟形成之其他鄰近半導體元件（未圖示）分隔開，藉此形成多個個別半導體元件300。
圖23說明與圖22中之半導體元件300類似但具有不同結構的基底350之另一實施例半導體元件300A。特定而言，圖23中之基底350之芯體310的僅一側（例如上部側）具有在其上形成之導電特徵（例如導電特徵313），且無導電特徵沿芯體310之另一側（例如下部側）形成。導通孔317電性耦接至導電特徵313且延伸穿過芯體310。儘管外部連接件325說明為圖23中之導電柱148的正上方，但導電特徵313可將電訊號重新分配至其他位置，且因此外部連接件325可設置於其他位置處。
圖24至圖27說明根據一實施例在各個製造階段上之半導體元件400的橫截面視圖。除非另外指明，否則圖24至圖27中之相同標號是指圖1至圖6A及/或圖10至圖15中之相同部件。舉例而言，具有相同標號之組件可由相同或類似材料形成，且可使用相同或類似的形成方法形成。為簡單起見，細節可能不會重複。
參考圖24，預製基底350由黏著層104貼合至載體101。黏著層104可為感光性的且可藉由例如在後續載體剝離方法中在載體101上照射紫外線（UV）光而易於自載體101分離。舉例而言，黏著層可為由明尼蘇達州聖保羅之3M公司製備的光-熱轉換（LTHC）塗層。
如圖24中所說明，基底350在介電層330中具有開口321且在介電層320中具有開口321'。開口321將用於與重佈線結構150電性連接（參見圖26），且開口321'將用於形成外部連接件325（參見圖27）。
接下來參考圖25，介電層322形成於基底350上方。介電層322可包括諸如氧化矽、氮化矽、氮氧化矽、類似者或其組合之合適的材料，且可藉由物理氣相沈積（physical vapor deposition；PVD）、CVD或其他合適之方法形成。介電層322可與下層共形。開口例如使用雷射鑽孔或其他合適之方法形成於介電層322中，以暴露基底350之導電特徵315之部分，如圖25中所說明。
接著，在圖26中，導電柱148形成於介電層322上方，且電性耦接至基底350。如圖26中所說明，導通孔329形成於開口321中（參見圖24），且電性耦接在導電柱148與基底350之間。接著，一或多個晶粒221之背側由黏著層105（例如DAF）貼合至介電層322。晶粒221之前側上的晶粒連接件225面朝上遠離基底350。
接著，模製材料337形成於介電層322上方及晶粒221/導電柱148周圍。可執行諸如CMP之平坦化製程以在導電柱148、模製材料337以及晶粒221之間獲得平坦的上部表面。晶粒連接件225是在平坦化製程之後暴露在模製材料337之上部表面處。
接著，重佈線結構150形成於晶粒221、導電柱148以及模製材料337上方。重佈線結構150機械及電性耦接至晶粒221及導電柱148。外部連接件153形成於UBM結構146上方，其中UBM結構146在重佈線結構150上方且電性耦接至所述重佈線結構150。
現參考圖27，翻轉圖26中所展示之半導體元件400，且外部連接件153貼合至由支架410支持的膠帶413。接著，載體101自半導體元件400剝離。黏著層104（參見圖26）是在載體剝離製程之後移除。清潔製程可在載體剝離製程之後執行以移除開口321'（參見圖26）中及/或介電層320上方之殘餘物。
接著，諸如焊料凸塊之外部連接件325形成於開口321'（參見圖26）中以連接至基底350之導電特徵。可執行分割製程（未圖示），緊接著將半導體元件400自鄰近半導體元件分隔開。
圖28說明與圖27中之半導體元件400類似但具有不同結構的基底350之另一實施例半導體元件400A。特定而言，圖28中之基底350之芯體310的僅一側（例如上部側）具有在其上形成之導電特徵（例如導電特徵313），且無導電特徵沿芯體310之另一側（例如下部側）形成。導通孔317電性耦接至導電特徵313且延伸穿過芯體310。儘管外部連接件325說明為圖28中之導電柱148的正上方，但導電特徵313可將電訊號重新分配至其他位置，且因此外部連接件325可設置於其他位置處。
圖29至圖32說明根據一實施例在各個製造階段上之半導體元件500的橫截面視圖。除非另外指明，否則圖29至圖32中之相同標號是指圖1至圖6A及/或圖10至圖15中之相同部件。舉例而言，具有相同標號之組件可由相同或類似材料形成，且可使用相同或類似的形成方法形成。為簡單起見，細節可能不會重複。
參考圖29，重佈線結構150形成於載體101上方。重佈線結構150之形成方法與圖1中之重佈線結構的形成方法相同或類似，由此不在本文中重複。
接著，在圖30中，一或多個晶粒221貼合至重佈線結構150。在所說明實例中，晶粒221之晶粒連接件225由焊料區223耦接至重佈線結構150之導電墊147。在貼合晶粒221之後，底填充材料227形成於晶粒221與重佈線結構150之間的間隙中。接著，模製材料337形成於晶粒221及底填充材料227周圍。可執行諸如CMP之平坦化製程以在晶粒221與模製材料337之間獲得共平面的上部表面。在一些實施例中，模製材料337不同於底填充材料227。
接下來參考圖31，預製基底350由黏著層328貼合至晶粒221及模製材料337之背側。328可為合適之介電層，諸如膠層、DAF或類似者。
如圖31中所說明，晶粒221與基底350之間不存在電連接，且重佈線結構150與基底350之間不存在電連接。在圖29至圖32中所說明之實施例中，基底350用於增加半導體元件500之機械穩定性（例如剛度）。另外，基底350之導電特徵（例如導電特徵313）用於使晶粒221之相對側（例如前側及背側）上的金屬密度（例如銅之密度）平衡以減少半導體元件500之翹曲的目的。舉例而言，可執行模擬及/或實驗以確定基底350之導電特徵的量及位置來抵消由例如晶粒221與重佈線結構150之間的CTE不匹配而誘發的翹曲。
在一些實施例中，基底350在芯體310之一側上僅具有導電特徵（例如導電特徵313）。在芯體310之另一側上不存在導通孔317（參見圖4）或導電特徵315（參見圖4）。圖31中之基底的導電特徵（例如導電特徵313）因此是虛設金屬圖案。換言之，圖31之導電特徵（例如導電特徵313）是經電性隔離之金屬圖案。在芯體310之一側上形成導電特徵簡化了設計，由此減少成本。
接著，在圖32中，半導體元件500之基底350貼合至由支架410支持的膠帶413，且載體101剝離。接著，使重佈線結構150之介電層110凹陷以暴露導電墊115，且外部連接件153形成於經暴露的導電墊115上方。儘管未展示，但可執行分割以將半導體元件500自其他鄰近半導體元件分隔開。
圖29至圖32之實施例的變化是有可能的。舉例而言，虛設導電特徵可形成於芯體310之下部側上（參見圖32中之幻影中所展示之導電特徵313'）而非芯體310之上部側上。在另一實施例中，虛設導電特徵可形成於芯體310之上部側（例如圖32中之導電特徵313）及下部側（例如圖32中之導電特徵313'）兩側上。此等及其他變化全部意欲包含於本發明之範疇內。
圖33說明與圖32中之半導體元件500類似但在晶粒221與重佈線結構150之間不具有底填充材料227之另一實施例半導體元件500A。在一些實施例中，圖33中之模製材料337為MUF材料。在所說明之實施例中，模製材料337不同於黏著層328。如上文所論述，虛設導電特徵313可形成於芯體310之上部側、下部側、或上部側及下部側兩側上。
圖34至圖37說明根據一實施例在各個製造階段上之半導體元件600的橫截面視圖。除非另外指明，否則圖34至圖37中之相同標號是指圖1至圖6A及/或圖10至圖15中之相同部件。舉例而言，具有相同標號之組件可由相同或類似材料形成，且可使用相同或類似的形成方法形成。為簡單起見，細節可能不會重複。
參考圖34，可預製基底350由黏著層326貼合至載體101。黏著層326可與圖24中之黏著層104相同，由此不在本文中重複細節。
基底350提供與半導體元件500（參見圖32）中之基底350相同的目的，且因此包括諸如導電特徵313之虛設金屬圖案。在圖34之實例中，虛設金屬圖案僅形成於芯體310的接觸介電層320之一側上。儘管未說明，但虛設金屬圖案可僅形成於接觸介電層330之芯體310之另一側上或芯體310之兩側上。此等及其他變化全部意欲包含於本發明之範疇內。
接著，在圖35中，一或多個晶粒221由黏著層105（例如DAF）貼合至基底350。晶粒221之前側的晶粒連接件225面朝上遠離基底350。
接著，在圖36中，模製材料337形成於基底350上方及晶粒221周圍。可執行諸如CMP之平坦化製程以在晶粒221與模製材料337之間獲得共平面的上部表面。接著，重佈線結構150形成於晶粒221及模製材料337上方。重佈線結構150電性耦接至晶粒221。接著，外部連接件153形成於電性耦接至重佈線結構150之UBM結構146之上方。
接下來參考圖37，半導體元件600之外部連接件153貼合至由支架410支持的膠帶413，載體101剝離，且移除黏著層326。可執行分割製程，隨後將半導體元件600自所形成之其他鄰近元件分隔開。
實施例可實現優點。舉例而言，與基底350設置於晶粒221與重佈線結構150之間的半導體元件相比較，本揭露之半導體元件（例如半導體元件100、半導體元件200、半導體元件300、半導體元件400、半導體元件500以及半導體元件600）在晶粒221與外部連接件153之間具有較短訊號路徑。具有較短訊號路徑減少了訊號延遲（例如RC延遲）且改善半導體元件之效能。另外，藉由將基底350及重佈線結構150置放於晶粒221之相對側上，可實現金屬密度之平衡，這減少了半導體元件（例如半導體元件100、半導體元件200、半導體元件300、半導體元件400、半導體元件500以及半導體元件600）之翹曲，無論基底350之導電特徵是否為虛設金屬圖案。
圖38說明根據一些實施例製造半導體元件之方法之流程圖。應理解，圖38中所展示之實施例方法僅為多個可能實施例方法之實例。於本領域具有通常知識者將認識到許多變體、替代物以及修改。舉例而言，可添加、移除、置換、重新配置以及重複如圖38中所說明之各種步驟。
參考圖38，在步驟1010處，重佈線結構形成於載體上方，所述重佈線結構在重佈線結構之遠離載體的表面上具有導電特徵。在步驟1020處，導電柱形成於重佈線結構之表面上方。在步驟1030處，晶粒貼合至與導電柱鄰近之重佈線結構的表面，其中晶粒之晶粒連接件電性耦接至重佈線結構之導電特徵。在步驟1040處，預製基底經由導電接頭貼合至導電柱，其中導電接頭在導電柱上且包括與導電柱不同之材料，其中導電接頭及導電柱將重佈線結構電性耦接至預製基底。
在一實施例中，一種形成半導體元件的方法包含：在載體上方形成重佈線結構，所述重佈線結構在重佈線結構之遠離載體的表面上具有導電特徵；在重佈線結構之表面上方形成導電柱；將晶粒貼合至與導電柱鄰近之重佈線結構的表面，其中晶粒之晶粒連接件電性耦接至重佈線結構之導電特徵；以及預製基底經由導電接頭貼合至導電柱，其中導電接頭在導電柱上且包括與導電柱不同之材料，其中導電接頭及導電柱將重佈線結構電性耦接至預製基底。在一實施例中，導電接頭為焊料區。在一實施例中，所述方法更包含在貼合所述預製基底之後，將頂部半導體元件貼合至預製基底之遠離重佈線結構的表面。在一實施例中，導電柱之遠離重佈線結構的表面比晶粒之遠離重佈線結構的表面更接近於重佈線結構。在一實施例中，所述方法更包含在貼合預製基底之後，使用第一模製材料填充預製基底與重佈線結構之間的空隙。在一實施例中，所述方法更包含在貼合晶粒之後且在貼合預製基底之前，在晶粒與重佈線結構之間的間隙中形成不同於第一模製材料的第二模製材料。在一實施例中，所述方法更包含在貼合晶粒之後且在貼合預製基底之前，在晶粒周圍及導電柱周圍形成第一模製材料；以及在貼合預製基底之後，使用不同於第一模製材料的第二模製材料填充第一模製材料與預製基底之間的空隙，其中導電接頭被第二模製材料包圍。在一實施例中，所述方法更包含將載體自重佈線結構移除；使重佈線結構之介電層凹陷，其中介電層之凹陷暴露重佈線層之導電特徵；以及在經暴露的導電特徵上方形成導電凸塊。
在一實施例中，一種形成半導體元件的方法包含：在載體上方形成重佈線結構，重佈線結構在重佈線結構之遠離載體的第一表面上具有導電墊；將晶粒之晶粒連接件接合至導電墊；在載體上方及晶粒周圍形成模製材料；預製基底經由黏著層貼合至模製材料及晶粒，預製基底具有電性隔離之虛設金屬特徵；在貼合預製基底之後，使重佈線結構之介電層凹陷以暴露重佈線結構之導電特徵；以及在經暴露的導電特徵上形成導電凸塊。在一實施例中，晶粒之晶粒連接件由焊料區接合至導電墊。在一實施例中，預製基底包括介電芯體，且虛設金屬特徵設置於介電芯體之至少一側上。在一實施例中，所述方法更包含在貼合預製基底之後且在使介電層凹陷之前：將預製基底貼合至膠帶；以及將載體自重佈線結構剝離。
在一實施例中，一種半導體元件包含：第一晶粒，嵌入於第一模製材料中，第一晶粒在第一晶粒之第一側具有晶粒連接件；第一導電柱，嵌入於第一模製材料中且與第一晶粒側向間隔開；重佈線結構，在第一晶粒之第一側，晶粒連接件由焊料接頭（solder joint）電性耦接至重佈線結構之導電特徵，導電特徵在重佈線結構之面向第一晶粒的表面上；基底，在第一晶粒相對第一側之第二側處；以及第一焊料區，插入於第一導電柱與基底之間，其中第一焊料區及第一導電柱將重佈線結構電性耦接至基底。在一實施例中，第一導電柱之遠離重佈線結構的表面比第一晶粒之第二側更接近於重佈線結構。在一實施例中，第一模製材料自重佈線結構連續延伸至基底，且其中第一焊料區嵌入於第一模製材料中。在一實施例中，半導體元件更包含第一晶粒與重佈線結構之間的底填充材料，其中底填充材料不同於第一模製材料。在一實施例中，半導體元件更包含第一模製材料與基底之間的第二模製材料，其中第二模製材料不同於第一模製材料。在一實施例中，第一導電柱之上部表面與第一晶粒之第二側及第一模製材料之上部表面齊平。在一實施例中，基底包含介電芯體、延伸穿過介電芯體之導通孔以及介電芯體之至少一側上的導線。在一實施例中，半導體元件更包含在基底之背離第一晶粒之一側上的焊料凸塊。
前文概述若干實施例之特徵，從而使得本領域的技術人員可較好地理解本發明之態樣。本領域的技術人員應理解，其可易於使用本發明作為設計或修改用於實現本文中所引入之實施例的相同目的及/或達成相同優點的其他方法及結構之基礎。本領域的技術人員亦應認識到，此類等效構造並不脫離本發明之精神及範疇，且本領域的技術人員可在不脫離本發明之精神及範疇之情況下在本文中作出各種改變、替代及更改。
100、100A、100B、100C、200、200A、200B、200C、300、300A、400、400A、500、500A、600‧‧‧半導體元件
101‧‧‧載體
102、321、321'‧‧‧開口
104、105、326、328‧‧‧黏著層
103、107、110、120、130、140、320、322、330‧‧‧介電層
113、123‧‧‧導線
115‧‧‧導通孔/導電墊
125、145‧‧‧通孔
146‧‧‧凸塊下金屬
147、513‧‧‧導電墊
148、149‧‧‧導電柱
150‧‧‧重佈線結構
153、325‧‧‧外部連接件
221‧‧‧晶粒
223‧‧‧導電區/焊料區
225‧‧‧導電凸塊/晶粒連接件
227‧‧‧底填充材料
228‧‧‧介電層
310‧‧‧芯體
313、313'、315‧‧‧導電特徵
317、329‧‧‧導通孔
323‧‧‧導電接頭/焊料區
327、337、530‧‧‧模製材料
350、510‧‧‧基底
410‧‧‧支架
413‧‧‧膠帶
515‧‧‧接線
517‧‧‧半導體晶粒
525‧‧‧導電接頭
1010、1020、1030、1040‧‧‧步驟
H1、H2‧‧‧高度
當結合附圖閱讀時，自以下實施方式最佳地理解本發明之態樣。應注意，根據業界中之標準慣例，各種特徵未按比例繪製。事實上，為論述清楚起見，可任意地增加或縮減各種特徵之尺寸。 圖1至圖5、圖6A以及圖6B說明根據一實施例在各個製造階段上之半導體元件的橫截面視圖。 圖7說明根據一實施例的半導體元件之橫截面視圖。 圖8說明根據一實施例的半導體元件之橫截面視圖。 圖9說明根據一實施例的半導體元件之橫截面視圖。 圖10至圖15說明根據一實施例在各個製造階段上之半導體元件的橫截面視圖。 圖16說明根據一實施例的半導體元件之橫截面視圖。 圖17說明根據一實施例的半導體元件之橫截面視圖。 圖18說明根據一實施例的半導體元件之橫截面視圖。 圖19至圖22說明根據一實施例在各個製造階段上之半導體元件的橫截面視圖。 圖23說明根據一實施例的半導體元件之橫截面視圖。 圖24至圖27說明根據一實施例在各個製造階段上之半導體元件的橫截面視圖。 圖28說明根據一實施例的半導體元件之橫截面視圖。 圖29至圖32說明根據一實施例在各個製造階段上之半導體元件的橫截面視圖。 圖33說明根據一實施例的半導體元件之橫截面視圖。 圖34至圖37說明根據一實施例在各個製造階段上之半導體元件的橫截面視圖。 圖38說明根據一些實施例的用於形成半導體元件之方法的流程圖。

Claims (20)

  1. 一種形成半導體元件的方法，包括： 在載體上方形成重佈線結構，所述重佈線結構在所述重佈線結構之遠離所述載體的表面上具有導電特徵； 在所述重佈線結構之所述表面上方形成導電柱； 將晶粒貼合至與所述導電柱鄰近之所述重佈線結構的所述表面，其中所述晶粒之晶粒連接件電性耦接至所述重佈線結構之所述導電特徵；以及 將預製基底經由導電接頭貼合至所述導電柱，其中所述導電接頭在所述導電柱上且包括與所述導電柱不同之材料，其中所述導電接頭及所述導電柱將所述重佈線結構電性耦接至所述預製基底。
  2. 如申請專利範圍第1項所述之方法，其中所述導電接頭為焊料區。
  3. 如申請專利範圍第2項所述之方法，更包括在貼合所述預製基底之後，將頂部半導體元件貼合至所述預製基底之遠離所述重佈線結構的表面。
  4. 如申請專利範圍第2項所述之方法，其中所述導電柱之遠離所述重佈線結構的表面比所述晶粒之遠離所述重佈線結構的表面更接近於所述重佈線結構。
  5. 如申請專利範圍第4項所述之方法，更包括在貼合所述預製基底之後，使用第一模製材料填充所述預製基底與重佈線結構之間的空隙。
  6. 如申請專利範圍第5項所述之方法，更包括在貼合所述晶粒之後且在貼合所述預製基底之前，在所述晶粒與所述重佈線結構之間的間隙中形成不同於所述第一模製材料的第二模製材料。
  7. 如申請專利範圍第1項所述之方法，更包括： 在貼合所述晶粒之後且在貼合所述預製基底之前，在所述晶粒周圍及所述導電柱周圍形成第一模製材料；以及 在貼合所述預製基底之後，使用不同於所述第一模製材料的第二模製材料填充所述第一模製材料與所述預製基底之間的空隙，其中所述導電接頭被所述第二模製材料包圍。
  8. 如申請專利範圍第1項所述之方法，更包括： 將所述載體自所述重佈線結構移除； 使所述重佈線結構之介電層凹陷，其中所述介電層之所述凹陷暴露所述重佈線層之所述導電特徵；以及 在經暴露的所述導電特徵上方形成導電凸塊。
  9. 一種形成半導體元件的方法，包括： 在載體上方形成重佈線結構，所述重佈線結構在所述重佈線結構之遠離所述載體的第一表面上具有導電墊； 將晶粒之晶粒連接件接合至所述導電墊； 在所述載體上方及所述晶粒周圍形成模製材料； 將預製基底經由黏著層貼合至所述模製材料及所述晶粒，所述預製基底具有電性隔離之虛設金屬特徵； 在貼合所述預製基底之後，使所述重佈線結構之介電層凹陷以暴露所述重佈線結構之導電特徵；以及 在經暴露的所述導電特徵上形成導電凸塊。
  10. 如申請專利範圍第9項所述之方法，其中所述晶粒之所述晶粒連接件由焊料區接合至所述導電墊。
  11. 如申請專利範圍第9項所述之方法，其中所述預製基底包括介電芯體，且所述虛設金屬特徵設置於所述介電芯體之至少一側上。
  12. 如申請專利範圍第9項所述之方法，更包括在貼合所述預製基底之後且在使所述介電層凹陷之前： 將所述預製基底貼合至膠帶；以及 將所述載體自所述重佈線結構剝離。
  13. 一種半導體元件，包括： 第一晶粒，嵌入於第一模製材料中，所述第一晶粒在所述第一晶粒之第一側具有晶粒連接件； 第一導電柱，嵌入於所述第一模製材料中且與所述第一晶粒側向間隔開； 重佈線結構，在所述第一晶粒之所述第一側，所述晶粒連接件由焊料接頭電性耦接至所述重佈線結構之導電特徵，所述導電特徵在所述重佈線結構之面向所述第一晶粒的表面上； 基底，在所述第一晶粒之相對所述第一側的第二側處；以及 第一焊料區，插入於所述第一導電柱與所述基底之間，其中所述第一焊料區及所述第一導電柱將所述重佈線結構電性耦接至所述基底。
  14. 如申請專利範圍第13項所述之半導體元件，其中所述第一導電柱之遠離所述重佈線結構的表面比所述第一晶粒之所述第二側更接近於所述重佈線結構。
  15. 如申請專利範圍第14項所述之半導體元件，其中所述第一模製材料自所述重佈線結構連續延伸至所述基底，且其中所述第一焊料區嵌入於所述第一模製材料中。
  16. 如申請專利範圍第13項所述之半導體元件，更包括在所述第一晶粒與所述重佈線結構之間的底填充材料，其中所述底填充材料不同於所述第一模製材料。
  17. 如申請專利範圍第13項所述之半導體元件，更包括在所述第一模製材料與所述基底之間的第二模製材料，其中所述第二模製材料不同於所述第一模製材料。
  18. 如申請專利範圍第17項所述之半導體元件，其中所述第一導電柱之上部表面與所述第一晶粒之所述第二側及所述第一模製材料之上部表面齊平。
  19. 如申請專利範圍第13項所述之半導體元件，其中所述基底包括介電芯體、延伸穿過所述介電芯體之導通孔以及在所述介電芯體之至少一側上的導線。
  20. 如申請專利範圍第19項所述之半導體元件，更包括在基底之背離所述第一晶粒之一側上的焊料凸塊。
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