TW201824486A - 封裝結構 - Google Patents

封裝結構 Download PDF

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Publication number
TW201824486A
TW201824486A TW106113547A TW106113547A TW201824486A TW 201824486 A TW201824486 A TW 201824486A TW 106113547 A TW106113547 A TW 106113547A TW 106113547 A TW106113547 A TW 106113547A TW 201824486 A TW201824486 A TW 201824486A
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TW
Taiwan
Prior art keywords
die
package
integrated passive
layer
component
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TW106113547A
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English (en)
Inventor
陳潔
余振華
葉德強
陳憲偉
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台灣積體電路製造股份有限公司
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Publication of TW201824486A publication Critical patent/TW201824486A/zh

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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
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Abstract

一種封裝結構及其形成方法。封裝結構包括第一封裝件、第一積體被動元件、第二積體被動元件以及底部填充體。第一封裝件包括第一晶粒、與第一晶粒相鄰的孔、包覆孔並圍繞第一晶粒的周界以至少橫向地包覆第一晶粒的模製化合物以及在第一晶粒及模製化合物之上延伸的第一重佈線結構。第一積體被動元件貼附至第一重佈線結構，第一積體被動元件靠近第一晶粒的周界安置。第二積體被動元件貼附至第一重佈線結構，第二積體被動元件遠離第一晶粒的周界安置。底部填充體安置於第一積體被動元件與第一重佈線結構之間，第二積體被動元件不含有底部填充體。

Description

封裝結構
本發明實施例是有關於一種封裝結構及其形成方法。
由於不同電子組件（例如，電晶體、二極管、電阻器、電容器等）的積體密度的持續增進，半導體行業已經歷快速增長。在很大程度上，積體密度的增進來自於最小特徵尺寸(feature size) 上不斷地縮減，這允許更多的組件能夠積體到給定區域內。隨著對縮小電子元件的需求的增長，需要更小且更具創造性的半導體晶粒封裝技術。這種封裝系統的一個實例是疊層封裝（Package-on-Package，PoP）技術。在疊層封裝元件中，頂部半導體封裝件被堆疊於底部半導體封裝件的頂面上，以提供高積體水平及組件密度。疊層封裝技術一般能夠生產功能性得到增強且在印刷電路板（printed circuit board，PCB）上佔用空間小的半導體元件。
一種封裝結構包括第一封裝件、第一積體被動元件、第二積體被動元件以及底部填充體。第一封裝件包括第一晶粒、與第一晶粒相鄰的孔、包覆孔並圍繞第一晶粒的周界以至少橫向地包覆第一晶粒的模製化合物以及在第一晶粒及模製化合物之上延伸的第一重佈線結構。第一積體被動元件貼附至第一重佈線結構，第一積體被動元件靠近第一晶粒的周界安置。第二積體被動元件貼附至第一重佈線結構，第二積體被動元件遠離第一晶粒的周界安置。底部填充體安置於第一積體被動元件與第一重佈線結構之間，第二積體被動元件不含有底部填充體。
以下公開內容提供用於實作所提供主題的不同特徵的許多不同的實施例或實例。以下闡述元件及排列的具體實例以簡化本公開內容。當然，這些僅為實例且不旨在進行限制。例如，以下說明中將第一特徵形成在第二特徵“的上方”或第二特徵“上”可包括其中第一特徵及第二特徵被形成為直接接觸的實施例，且也可包括其中第一特徵與第二特徵之間可形成有附加特徵、進而使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。另外，本公開內容可能在各種實例中重複使用參考編號及/或字母。這種重複使用是出於簡潔及清晰的目的，而不是自身表示所論述的各種實施例及/或配置之間的關係。
此外，為易於說明，本文中可能使用例如“之下（beneath）”、“下面（below）”、“下部的（lower）”、“上方（above）”、“上部的（upper）”等空間相對性用語來闡述圖中所示的一個元件或特徵與另一（其他）元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的取向外還囊括裝置/元件在使用或操作中的不同取向。裝置可具有其他取向（旋轉90度或處於其他取向）且本文中所用的空間相對性描述語可同樣相應地進行解釋。
根據各種實施例提供一種封裝結構及其形成方法。具體來說，形成包括晶粒的封裝結構，且在所述封裝結構上形成積體被動元件（integrated passive device，IPD）。在積體被動元件的子集（subset）與封裝結構的重佈線結構（redistribution structure）之間形成底部填充體（underfill）。僅對定位於封裝結構上的特定位置中的積體被動元件形成底部填充體。例如，可對位於靠近封裝結構中的晶粒的周界的積體被動元件形成底部填充體。其他積體被動元件不具有底部填充體。選擇性地形成底部填充體可在降低製造成本的同時提高最終結構的可靠性。對各實施例的一些變型進行論述。所屬領域中的普通技術人員將易於理解可預期落於其他實施例範圍內的其他變動。
圖1至圖10是根據一些實施例中形成第一元件封裝件200的製程期間各中間步驟的各種圖​​。圖1至圖8A以及圖9至圖10是剖視圖。圖8B是沿來自圖8A的參考橫截面A-A進行說明的平面圖。
在圖1中，示出處於處理的中間階段的第一元件封裝件200，第一元件封裝件200包括形成於載體基板100上的離型層（release layer）102。用於形成第一元件封裝件200的第一封裝區600也被示出。儘管僅示出一個封裝區600，然而也可形成有多個封裝區。
載體基板100可為玻璃載體基板、陶瓷載體基板或類似物等。載體基板100可為晶圓，進而使得可在載體基板100上同時形成多個封裝件。離型層102可由聚合物系材料形成，所述聚合物系材料可與載體基板100一起從將在後續步驟中形成的上覆結構上被移除。在某些實施例中，離型層102是會在受熱時失去其粘著特性的環氧樹脂系熱釋放材料，例如光熱轉換（light-to-heat-conversion，LTHC）釋放塗層。在其他實施例中，離型層102可為會在被暴露至紫外光時失去其粘著特性的紫外光（ultra-violet，UV）膠。離型層102可作為液體進行分配並進行固化，離型層102可為被積層至載體基板100上的積層體膜（laminate film），或可為其他形式。離型層102的頂表面可以是等高（leveled）且離型層102的頂表面可具有高共面程度（degree of coplanarity）。
在圖2中，形成介電層104及金屬化圖案106（metallization pattern）。如圖2所示，在離型層102上形成介電層104。介電層104的底表面可接觸離型層102的頂表面。在某些實施例中，介電層104是由例如聚苯並噁唑（polybenzoxazole，PBO）、聚酰亞胺（polyimide）、苯並環丁烯（benzocyclobutene，BCB）或類似物等聚合物形成。在其他實施例中，介電層104是由以下材料形成：氮化物，例如氮化矽；氧化物，例如氧化矽、磷矽酸鹽玻璃（phosphosilicate glass，PSG）、硼矽酸鹽玻璃（borosilicate glass，BSG）、摻雜硼的磷矽酸鹽玻璃（boron-doped phosphosilicate glass，BPSG）或類似物等；或者類似材料。通過例如旋轉塗佈（spin coating）、化學氣相沉積（chemical vapor deposition，CVD）、積層（laminating）、類似製程、或其組合等任何可接受的沉積製程來形成介電層104。
在介電層104上形成金屬化圖案106。作為形成金屬化圖案106的實例，在介電層104之上形成晶種層（未示出）。在某些實施例中，晶種層為金屬層，其可為單一層或包括由不同材料形成的多個子層的複合層。在某些實施例中，晶種層包括鈦層及位於所述鈦層之上的銅層。可使用例如物理氣相沉積（physical vapor deposition，PVD）或類似製程等來形成晶種層。接著形成光阻（photo resist）並將所述光阻圖案化於晶種層上。可通過旋轉塗佈或類似製程等來形成光阻並可將所述光阻暴露於光以進行圖案化。光阻的圖案對應於金屬化圖案106。所述圖案化會形成穿過光阻以暴露出晶種層的開口。在光阻的開口中且在晶種層的暴露的部分上形成導電材料。可通過電鍍（例如，電鍍（electroplating）、無電電鍍（electroless plating）或類似製程等）來形成導電材料。導電材料可包括金屬，如銅、鈦、鎢、鋁或類似物等。接著，移除光阻以及部分上方未形成有導電材料的晶種層。通過可接受的灰化製程（ashing process）或剝除製程（stripping process）來移除光阻，例如使用氧等離子體或類似製程等。一旦光阻被移除，則例如使用可接受的蝕刻製程（如通過濕式蝕刻（wet etching）或乾式蝕刻（dry etching））來移除被暴露的部分晶種層。晶種層的其餘部分及導電材料會形成金屬化圖案106。
在圖3中，在金屬化圖案106及介電層104上形成介電層108。在某些實施例中，介電層108是由可使用光罩（lithography mask）進行圖案化的聚合物形成，所述聚合物可為例如聚苯並噁唑、聚酰亞胺、苯並環丁烯或類似物等感光性材料。在其他實施例中，介電層108是由以下材料形成：氮化物，例如氮化矽；氧化物，例如氧化矽、磷矽酸鹽玻璃、硼矽酸鹽玻璃、摻雜硼的磷矽酸鹽玻璃或類似物；或者類似材料。可通過旋轉塗佈、積層、化學氣相沉積、類似製程、或其組合來形成介電層108。接著將介電層108圖案化以形成暴露出金屬化圖案106的某些部分的開口。通過可接受的製程來進行所述圖案化，例如當介電層為感光性材料時通過將介電層108暴露於光來進行所述圖案化，或者通過使用例如非等向性蝕刻（anisotropic etch ）進行蝕刻來進行所述圖案化。
可將介電層104及108以及金屬化圖案106稱作背側重佈線結構（back-side redistribution structure）110。如圖式所示，背側重佈線結構110包括所述兩個介電層104及108及一個金屬化圖案106。在其他實施例中，背側重佈線結構110可包括任何數目的介電層、金屬化圖案、及孔。可通過重複進行所述形成金屬化圖案106及介電層108的製程而在背側重佈線結構110中形成一個或多個額外的金屬化圖案及介電層。可在所述形成金屬化圖案期間通過在位於下方的介電層的開口中形成所述金屬化圖案的晶種層及導電材料來形成孔。所述孔可因此對不同金屬化圖案進行內連及電耦合。在某些實施例（在圖13及圖14示出），背側重佈線結構110為可選的。如此一來，可不形成金屬化圖案106及位於介電層108中的開口。在某些實施例中，可僅當金屬化圖案106具有高於預定閾值（predefined threshold）的圖案密度時，形成背側重佈線結構110。在此類實施例中，可從介電層進行增層而形成第一元件封裝件200。
在圖3中，形成穿孔112。作為形成穿孔112的實例，在背側重佈線結構110（例如，所示介電層108及金屬化圖案106被暴露出來的部分）之上形成晶種層。在某些實施例中，晶種層為金屬層，其可為單一層或包括由不同材料形成的多個子層的複合層。在某些實施例中，晶種層包括鈦層及位於所述鈦層之上的銅層。可使用例如物理氣相沉積或類似製程等來形成晶種層。形成光阻並將所述光阻圖案化於晶種層上。可通過旋轉塗佈或類似製程等來形成光阻並可將所述光阻暴露於光以進行圖案化。光阻的圖案對應於穿孔。所述圖案化會形成穿過光阻以暴露出晶種層的開口。在光阻的開口中且在晶種層的暴露的部分上形成導電材料。可通過電鍍（例如，電鍍、無電電鍍或類似製程等）來形成導電材料。導電材料可包括金屬，如銅、鈦、鎢、鋁或類似物等。移除光阻以及晶種層的部分上方未形成有導電材料的晶種層。通過可接受的灰化製程或剝除製程來移除光阻，例如使用氧等離子體或類似製程等。一旦光阻被移除，則例如使用可接受的蝕刻製程（例如通過濕式蝕刻或乾式蝕刻）來移除被暴露的部分晶種層。晶種層的其餘部分及導電材料會形成穿孔112。
在圖4中，通過粘合劑116將積體電路晶粒114粘合至介電層108。如圖4所示，將一個積體電路晶粒114粘合於第一封裝區600中，且在其他實施例（將在以下圖11A至圖11B中論述）中，可在每一區中粘附更多或更少的積體電路晶粒114。積體電路晶粒114可為邏輯晶粒（例如，中央處理單元（central processing unit）、微控制器等）、記憶體晶粒（例如，動態隨機存取記憶體（dynamic random access memory，DRAM）晶粒、靜態隨機存取記憶體（static random access memory，SRAM）晶粒等）、電力管理晶粒（例如，電力管理積體電路（power management integrated circuit，PMIC）晶粒）、射頻（radio frequency ，RF）晶粒、感測晶粒、微機電系統（micro-electro-mechanical-system，MEMS）晶粒、信號處理晶粒（例如，數字信號處理（digital signal processing，DSP）晶粒）、前端晶粒（例如，模擬前端（analog front-end，AFE）晶粒）、類似的晶粒、或其組合。此外，在某些實施例中，積體電路晶粒114可為不同大小（例如，不同高度及/或表面積），且在其他實施例中，積體電路晶粒114可為相同大小（例如，相同高度及/或表面積）。
在粘附至介電層108之前，可根據適用於在積體電路晶粒114中形成積體電路的製造製程來加工積體電路晶粒114。例如，積體電路晶粒114各自分別包括半導體基板118，例如經摻雜的或未經摻雜的矽、或絕緣體上半導體（semiconductor-on-insulator，SOI）基板的作用層。半導體基板可包含：其他半導體材料，例如鍺；化合物半導體，包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、及/或銻化銦；合金半導體，包括SiGe、GaAsP、 AlInAs、AlGaAs、GaInAs、GaInP、及/或GaInAsP；或者其組合。也可使用例如多層式基板（multi-layered substrate）或梯度基板（gradient substrate）等其他基板。可在半導體基板118中及/或半導體基板118上形成例如電晶體、二極管、電容器、電阻器等元件且可通過由例如位於半導體基板118上的一個或多個介電層中的金屬化圖案所形成的內連線結構120將各所述元件進行互連以形成積體電路。
積體電路晶粒114進一步包括進行外部連接的襯墊122（例如鋁襯墊）。墊122位於可被稱為積體電路晶粒114的相應作用側的部位上。鈍化膜（passivation film）124位於積體電路晶粒114上且位於襯墊122的部分上。開口穿過鈍化膜124到達襯墊122。例如導電柱（例如，包含例如銅等金屬）等晶粒連接件126位於穿過鈍化膜124的開口中，並且機械至且電耦合至相對應的襯墊122。可通過例如電鍍或類似方法等來形成晶粒連接件126。晶粒連接件126電耦合積體電路晶粒114的相應積體電路。
介電質材料128位於積體電路晶粒114的作用側（active side）上，例如位於鈍化膜124及晶粒連接件126上。介電質材料128橫向地（laterally）包覆晶粒連接件126，且介電質材料128橫向地與相應積體電路晶粒114相接。可將介電質材料128初始地形成為掩埋或覆蓋晶粒連接件126；當晶粒連接件126被掩埋時，介電質材料128的頂表面可具有不均勻拓撲（topology）。介電質材料128可為聚合物（例如聚苯並噁唑、聚酰亞胺、苯並環丁烯或類似物等）、氮化物（例如氮化矽或類似物等），氧化物（例如氧化矽、磷矽酸鹽玻璃、硼矽酸鹽玻璃、摻雜硼的磷矽酸鹽玻璃或類似物等）、類似材料、或其組合，且可例如通過旋轉塗佈、積層、化學氣相沉積或類似方法等來形成介電質材料128。
粘合劑116位於積體電路晶粒114的背側上並將積體電路晶粒114粘附至背側重佈線結構110（例如圖中的介電層108）。粘合劑116可為任何適合的粘合劑、環氧樹脂、晶粒貼合膜（die attach film，DAF）等。可將粘合劑116施加至積體電路晶粒114的背側，例如施加至相應半導體晶圓的背側或者可施加於載體基板100的表面之上。可例如通過鋸切（sawing）或切割（dicing）而將積體電路晶粒114單體化，並使用例如拾取及放置工具（pick-and-place tool）通過粘合劑116而將積體電路晶粒114粘附至介電層108。
在圖5中，在各種組件上形成封裝體（encapsulant）130。封裝體130可為模製化合物、環氧樹脂或類似物等，且可通過壓縮模製（compression molding）、傳遞模製（transfer molding）或類似方法等來施加封裝體130。可將封裝體130形成於積體電路晶粒114之上，進而使得晶粒連接件126及/或穿孔112被隱埋或覆蓋。在固化之後，封裝體130可經歷研磨製程（grinding process）以暴露出穿孔112及晶粒連接件126。所述研磨製程也可對介電質材料128進行研磨。在研磨製程之後，穿孔112的頂表面、晶粒連接件126的頂表面、介電質材料128的頂表面、及封裝體130的頂表面是共面的（coplanar）。研磨製程可為例如化學機械拋光（chemical-mechanical polish，CMP）。在某些實施例中，例如若已暴露出穿孔112及晶粒連接件126，則可省略所述研磨。
在圖6中，在封裝體130、穿孔112、及晶粒連接件126上形成前側重佈線結構（front-side redistribution structure）132。前側重佈線結構132包括多個介電層及金屬化圖案。例如，可將前側重佈線結構132圖案化成通過相應一個或多個介電層而彼此分隔開的多個分立的部分。前側重佈線結構132可為例如重佈線層（redistribution layer，RDL），且可包括金屬跡線（或金屬線）及位於所述金屬跡線之下且連接至所述金屬跡線的孔。根據本發明實施例的某些實施例，通過電鍍製程形成重佈線層，其中所述重佈線層中的每一者包括晶種層（未示出）及位於所述晶種層之上的經電鍍金屬材料。晶種層與經電鍍金屬材料可由相同材料或不同材料形成。
示出前側重佈線結構132作為實例。可在前側重佈線結構132中形成比所示出的前側重佈線結構132更多或更少的介電層及金屬化圖案。所屬領域中的普通技術人員將易於理解，省略或重複進行哪些步驟及製程可形成更多的或更少的介電層及金屬化圖案。
在圖6中，進一步將前側重佈線結構132的頂部介電層圖案化。所述圖案化會形成暴露出金屬化圖案的某些部分的開口以用於隨後形成導電墊。通過可接受的製程來進行所述圖案化，例如當介電層為感光性材料時通過將所述介電層暴露於光來進行所述圖案化，或者通過使用例如非等向性蝕刻進行蝕刻來進行所述圖案化。若介電層為感光性材料，則可在曝光之後對所述介電層進行顯影。
在圖7中，在前側重佈線結構132的外側（exterior side）上形成襯墊134及136。使用襯墊134及136對各導電連接件進行耦合。在所示實施例中，經由穿過介電層到達前側重佈線結構132的金屬層的開口來形成襯墊134及136。作為形成襯墊134及136的實例，在介電層之上形成晶種層（未示出）。在某些實施例中，晶種層為金屬層，其可為單一層或包括由不同材料形成的多個子層的複合層。在某些實施例中，晶種層包括鈦層及位於所述鈦層之上的銅層。可使用例如物理氣相沉積或類似製程等來形成晶種層。接著形成光阻並將所述光阻圖案化於晶種層上。可通過旋轉塗佈或類似製程等來形成光阻並可將所述光阻暴露於光以進行圖案化。光阻的圖案對應於前側重佈線結構132中的導電墊。所述圖案化會形成穿過光阻以暴露出晶種層的開口。在光阻的開口中且在晶種層的暴露的部分上形成導電材料。可通過電鍍（例如，電鍍、無電電鍍或類似製程等）來形成導電材料。導電材料可包括金屬，如銅、鈦、鎢、鋁或類似物等。接著，移除光阻以及部分上方未形成有導電材料的晶種層。通過可接受的灰化製程或剝除製程來移除光阻，例如使用氧等離子體或類似製程等。一旦光阻被移除，則例如使用可接受的蝕刻製程（如通過濕式蝕刻或乾式蝕刻）來移除被暴露的部分晶種層。晶種層的其餘部分及導電材料會形成襯墊134及136。在其中以不同的方式形成襯墊134及136的實施例中，可使用更多的光阻及圖案化步驟。
儘管被示出的襯墊134及136為具有不同尺寸，然而應知，襯墊134及136可為各種連接類型及尺寸。此外，襯墊134與襯墊136可為不同尺寸或相同尺寸。例如，在某些實施例中，襯墊134可為凸塊下金屬（under bump metallurgy，UMB）且襯墊136可為微凸塊（micro bump）。如此一來，在本文中，可將襯墊134稱作凸塊下金屬134且可將襯墊136稱作凸塊136。可在同一電鍍製程（如上論述）中形成襯墊134與襯墊136或可在不同電鍍製程中形成襯墊134與襯墊136。
在圖8A及圖8B中，在凸塊下金屬134上形成導電連接件138且在凸塊136上安裝積體被動元件組件140及142。在某些實施例中，可在將積體被動元件組件140及142安裝於凸塊136上之前，在凸塊下金屬134上形成導電連接件138。在某些實施例中，可在將積體被動元件組件140及142安裝於凸塊136上之後，在凸塊下金屬134上形成導電連接件138。
導電連接件138可為球柵陣列封裝（ball grid array，BGA）連接件、焊料球、金屬柱、受控塌陷晶片連接（controlled collapse chip connection，C4）凸塊、微凸塊、無電鍍鎳鈀浸金技術（electroless nickel-electroless palladium-immersion gold technique，ENEPIG）形成的凸塊或類似物等。導電連接件138可包含例如焊料、銅、鋁、金、鎳、銀、鈀、錫、類似材料、或其組合等導電材料。在某些實施例中，通過使用例如蒸鍍（evaporation）、電鍍、印刷、焊料轉移（solder transfer）、植球（ball placement）或類似製程等常用方法初始地形成焊料層來形成導電連接件138 。一旦已在所述結構上形成焊料層，則可執行回焊（reflow）以將所述材料造型成所需凸塊形狀。在另一實施例中，導電連接件138為通過濺鍍（sputtering）、印刷、電鍍、無電電鍍、化學氣相沉積或類似製程等而形成的金屬柱（例如銅柱）。所述金屬柱可不含有焊料且具有實質上垂直的側壁。在某些實施例中，在金屬柱連接件138的頂部上形成金屬蓋層（metal cap layer）（未示出）。金屬蓋層可包含鎳、錫、錫-鉛、金、銀、鈀、銦、鎳-鈀-金、鎳-金、類似材料、或其組合，且可通過電鍍製程來形成所述金屬蓋層。
在結合至前側重佈線結構132之前，可根據適用於在積體被動元件組件140及142中形成被動元件的製造製程來加工積體被動元件組件140及142。例如，積體被動元件組件140及142各自分別包括位於所述積體被動元件組件的主體結構中的一個或多個被動元件。所述主體結構可包括基板及/或封裝體。在所述主體結構包括基板的實施例中，所述基板可為半導體基板，例如經摻雜的或未經摻雜的矽、或絕緣體上半導體基板的作用層。半導體基板可包含：其他半導體材料，例如鍺；化合物半導體，包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、及/或銻化銦；合金半導體，包括SiGe、GaAsP、 AlInAs、AlGaAs、GaInAs、GaInP、及/或GaInAsP；或者其組合。也可使用例如多層式基板或梯度基板等其他基板。被動元件可包括電容器、電阻器、電感器、類似元件、或其組合。可在半導體基板中及/或半導體基板上及/或在封裝體內形成所述被動元件，且可通過由例如位於主體結構上的一個或多個介電層中的金屬化圖案形成的內連線結構將各所述元件進行互連以形成積體被動元件組件140及142。積體被動元件組件140與積體被動元件組件142可為相同類型的積體被動元件組件或可為不同類型的積體被動元件組件。積體被動元件組件140及142可為表面安裝元件（surface mount device，SMD）、2端子積體被動元件（2-terminal IPD）、多端子積體被動元件（multi-terminal IPD）、或其他類型的被動元件。在積體被動元件組件140及142上形成耦合至積體被動元件組件140及142的微凸塊144，微凸塊144進行外部連接。
在微凸塊144的端部上形成焊料凸塊146，進而在微凸塊144與凸塊136之間形成焊料接頭（solder joint），由此將前側重佈線結構132耦合至積體被動元件組件140及142。與在球柵陣列封裝（BGA）連接件（例如，導電連接件138）中使用的所具有的直徑可介於例如約150 μm至約300 μm範圍內的傳統焊料球相比，微凸塊具有小得多的直徑，例如介於約10 μm至約40 μm範圍內。微凸塊可在某些實施例中具有為約40 μm或大於40 μm的節距（pitch）。
將積體被動元件組件140及142貼附至第一元件封裝件200上的特定位置。如圖8B所示，積體被動元件組件142位於靠近積體電路晶粒114的周界。相比之下，積體被動元件組件140位於遠離積體電路晶粒114的周界。
在圖8A及圖8B中，進一步在靠近積體電路晶粒114的周界的積體被動元件組件（例如，積體被動元件組件142）下方形成底部填充體148。圖8A及圖8B說明完全填充式底部填充方案（full-fill underfill scheme），其中底部填充體148完全填充位於積體被動元件組件142與前側重佈線結構132之間的區域，並且環繞微凸塊144、焊料凸塊146、及凸塊136。在某些實施例（未示出）中，可使用局部填充式底部填充方案（partial-fill underfill scheme），其中底部填充體148局部填充位於積體被動元件組件142與前側重佈線結構132之間的區域。可在貼附積體被動元件組件142之後通過毛細流動製程（capillary flow process）來形成底部填充體148，或者可在貼附積體被動元件組件142之前通過適合的沉積方法或印刷方法來形成底部填充體148。
第一元件封裝件200的位於積體電路晶粒114的周界處的區域可可能受到較高的機械力或機械應力。所述較高的機械力可使得位於所述周界處的積體被動元件組件因例如其觸點（例如，微凸塊144）開裂而出現故障。所述開裂可為局部開裂或橫跨所述觸點的完全開裂。若積體被動元件組件受到較高的機械力，則可將所述積體被動元件組件視為靠近積體電路晶粒114的周界。靠近周界（proximity to the perimeter）可由平面圖中評估。如此一來，儘管在剖視圖中某些組件（例如，前側重佈線結構132）位於積體被動元件組件與積體電路晶粒114之間，然而若所述積體被動元件組件在平面圖中靠近週界，則仍可將所述積體被動元件組件視為靠近積體電路晶粒114的周界。換句話說，積體被動元件組件是否直接位於積體電路晶粒114的上方被用於評估靠近周界。在某些實施例中，當積體被動元件組件與積體電路晶粒114的周界交叉時，將所述積體被動元件組件視為靠近積體電路晶粒114的周界。在某些實施例中，當積體被動元件組件處於積體電路晶粒114的周界的特定距離以內時，將所述積體被動元件組件視為靠近積體電路晶粒114的周界。例如，如圖8B所示，積體電路晶粒114的周界可存在外餘裕（exterior margin）M1或內餘裕（interior margin）M2，進而使得當積體被動元件組件處於外餘裕M1或內餘裕M2以內時將所述積體被動元件組件視為靠近積體電路晶粒114的周界。外餘裕M1與內餘裕M2可為相同的或可為不同的。在一個實施例中，外餘裕M1為約30 μm，且內餘裕M2為約30 μm。
在圖8A及圖8B所示實例中，由於積體被動元件組件142與積體電路晶粒114的周界交叉，因此將積體被動元件組件142視為靠近積體電路晶粒114的周界。相似地，由於積體被動元件組件140不與積體電路晶粒114的周界交叉且不落於外餘裕M1或內餘裕M2中，因此將積體被動元件組件140視為遠離積體電路晶粒114的周界。如此一來，底部填充體148形成於積體被動元件組件142，但不形成於積體被動元件組件140下方。在積體被動元件組件142下方形成底部填充體148，可保護積體被動元件組件142免於承受積體電路晶粒114所施加的機械力，而提高積體被動元件組件142的可靠性。由於不在未經受積體電路晶粒114所施加的機械力的積體被動元件組件140下方形成底部填充體148，因此選擇性地形成底部填充體148還可降低封裝件形成成本。
在進行貼附之後，積體被動元件組件140及142從前側重佈線結構132延伸出第一高度H1，第一高度H1小於導電連接件138從前側重佈線結構132延伸出的第二高度H2。如此一來，當在基板上安裝第一元件封裝件200時，存在足以容納積體被動元件組件140及142的間隔高度（standoff height）。
在圖9中，執行載體基板剝離（carrier substrate de-bonding）以將載體基板100從背側重佈線結構110（例如，介電層104）脫離（剝離）。根據某些實施例，所述剝離包括將例如激光或紫外光等光投射在離型層102上以使得離型層102在光的熱量下分解，且可移除載體基板100。接著將所述結構翻轉並放置於膠帶150上。
在圖9中，進一步形成穿過介電層104的開口152以暴露出金屬化圖案106的部分。可例如使用激光鑽孔（laser drilling）、蝕刻或類似製程等來形成所述開口。
在圖9中，進一步通過沿例如位於相鄰封裝區之間的切割道區（scribe line region）進行單體化154來執行單體化製程（singulation process）。在某些實施例中，單體化154包括鋸切製程、激光製程或其組合。單體化154將第一封裝區600從相鄰封裝區（未示出）單體化。
在圖10中，示出在單體化之後的所得第一元件封裝件200，所得第一元件封裝件200可來自於第一封裝區600。也可將第一元件封裝件200稱作積體扇出（integrated fan-out，InFO）封裝件200。在某些實施例中，在將第二元件封裝件300（如下論述）結合至積體扇出封裝件200之後，執行單體化製程。
圖11是根據一些實施例中形成封裝結構500的製程期間各中間步驟的剖視圖。封裝結構500可為疊層封裝（PoP）結構。
在圖11中，將第二元件封裝件300貼附至第一元件封裝件200。第二元件封裝件300包括基板302及耦合至基板302的一個或多個堆疊晶粒308（308A及308B）。基板302可由例如矽、鍺、金剛石或類似物等半導體材料製成。在某些實施例中，也可使用例如矽鍺、碳化矽、砷化鎵、砷化銦、磷化銦、碳化矽鍺、磷化鎵砷、磷化鎵銦、其組合或類似物等化合物材料。另外，基板302可為絕緣體上半導體（SOI）基板。一般來說，絕緣體上半導體基板包括例如磊晶矽、鍺、矽鍺、絕緣體上半導體、絕緣體上矽鍺（silicon germanium on insulator，SGOI）或其組合等半導體材料的層。在一個替代性實施例中，基板302是基於絕緣芯體，例如玻璃纖維加強型樹脂芯體（fiberglass reinforced resin core）。一種示例性芯體材料為玻璃纖維樹脂（例如，FR4）。芯體材料的另一些選擇包括雙馬來酰亞胺三嗪（bismaleimide-tirazine，BT）樹脂，或作為另外一種選擇，包括其他印刷電路板（PCB）材料或膜。可對基板302使用例如味之素增層膜（Ajinomoto build-up film，ABF）等增層膜或其他積層體。
基板302可包括主動元件或被動元件（未示出）。所屬領域中的普通技術人員應知到，可使用例如電晶體、電容器、電阻器、其組合或類似物等各種各樣的元件來產生第二元件封裝件300設計中的結構性要求及功能性要求。可使用任何適合的方法來形成所述元件。
基板302也可包括金屬化層（未示出）及穿孔306。可在主動元件及被動元件之上形成金屬化層並將所述金屬化層設計成連接各種元件，以形成功能性電路系統。金屬化層可由交替的介電（例如，低k介電質材料）層與導電材料（例如，銅）層以及具有對各導電材料層進行內連的孔所形成，並且可通過任何適合的製程（例如，沉積、鑲嵌、雙鑲嵌（dual damascene）或類似製程等）來形成所述金屬化層。在某些實施例中，基板302實質上不含有主動元件及被動元件。
基板302可具有接合墊304A及接合墊304B，接合墊304A位於基板302的第一側上以耦合至堆疊晶粒308，接合墊304B位於基板302的第二側上以耦合至導電連接件314，基板302的第二側與第一側相對。在某些實施例中，通過在基板302的第一側及第二側上在介電層（未示出）中形成凹陷部（未示出）來形成接合墊304A及304B。凹陷部的形成使得接合墊304A及304B能夠嵌置於介電層中。在其他實施例中，由於可在介電層上形成接合墊304A及304B，因此會省略所述凹陷部。在某些實施例中，接合墊304A及304B包括由銅、鈦、鎳、金、鈀、類似材料、或其組合製成的薄晶種層（未示出）。可在所述薄晶種層之上沉積接合墊304A及304B的導電材料。可通過電化學電鍍製程（electro-chemical plating process）、無電電鍍製程、化學氣相沉積、原子層沉積（atomic layer deposition，ALD）、物理氣相沉積、類似製程、或其組合來形成導電材料。在一個實施例中，接合墊304A及304B的導電材料為銅、鎢、鋁、銀、金、類似材料、或其組合。
在一個實施例中，接合墊304A及304B為包括三層導電材料層的凸塊下金屬，所述三層導電材料層例如為鈦層、銅層、及鎳層。然而，所屬領域中的普通技術人員應知到尚有其它適用於形成凸塊下金屬304A及304B的材料與膜層的排列方式，例如鉻/鉻-銅合金/銅/金的排列方式、鈦/鈦鎢/銅的排列方式、或銅/鎳/金的排列方式。可用於凸塊下金屬304A及304B的任何適合的材料或材料層完全旨在包含於當前申請的範圍內。在某些實施例中，穿孔306穿過基板302而延伸且將至少一個接合墊304A耦合至至少一個接合墊304B。
在所示實施例中，儘管可使用例如導電凸塊等其他連接方式，然堆疊晶粒308是通過鍵合線（wire bonds）310耦合至基板302。在一個實施例中，堆疊晶粒308為堆疊的記憶體晶粒。例如，堆疊的記憶體晶粒308可包括低功率（low-power，LP）雙倍數據速率（double data rate，DDR）記憶體模組，例如LPDDR1、LPDDR2、LPDDR3、LPDDR4、或類似的記憶體模組。
在某些實施例中，可通過模製材料312來包覆堆疊晶粒308及鍵合線310。可例如使用壓縮模製將模製材料312模製於堆疊晶粒308及鍵合線310上。在某些實施例中，模製材料312為模製化合物、聚合物、環氧樹脂、氧化矽填料材料、類似材料、或其組合。可執行固化步驟以固化模製材料312，其中所述固化可為熱固化、紫外光固化、類似固化方式、或其組合。
在某些實施例中，將堆疊晶粒308及鍵合線310埋置於模製材料312中，且在固化模製材料312之後，執行例如研磨等平坦化步驟以移除模製材料312的過量部分，用以提供第二元件封裝件300實質上平坦的表面。
在形成第二元件封裝件300之後，通過導電連接件314、接合墊304B、背側重佈線結構110、及/或穿孔112，將第二元件封裝件300結合至第一元件封裝件200。在某些實施例中，通過鍵合線310、接合墊304A及304B、穿孔306、導電連接件314、及穿孔112可將堆疊的記憶體晶粒308耦合至積體電路晶粒114。
儘管導電連接件138與導電連接件314無需相同，然而導電連接件314可相似於上述導電連接件138且本文中不再對其予以贅述。在某些實施例中，在結合導電連接件314之前，以例如免清洗焊劑（no-clean flux）等焊劑（未示出）塗佈導電連接件314。可將導電連接件314浸入焊劑中或可將所述焊劑噴射至導電連接件314上。在另一實施例中，可將焊劑施加至背側重佈線結構110的表面。
在某些實施例中，在導電連接件314被回焊之前，導電連接件314上可形成有環氧樹脂焊劑（未示出），所述環氧樹脂焊劑的至少某些環氧樹脂部分會在將第二元件封裝件300貼合至第一元件封裝件200之後餘留。此餘留的環氧樹脂部分可充當底部填充體以減小應力並保護對導電連接件314進行回焊而得到的連接點（joints）。在某些實施例中，可在第二元件封裝件300與第一元件封裝件200之間形成環繞導電連接件314的底部填充體（未示出）。底部填充體可在貼附第二元件封裝件300之後通過毛細流動製程來形成，或者可在貼附第二元件封裝件300之前通過適合的沉積方法來形成所述底部填充體。
第二元件封裝件300與第一元件封裝件200之間的結合可為焊料結合或直接金屬對金屬（metal-to-metal）（例如，銅對銅（copper-to-copper）或錫對錫（tin-to-tin））結合。在一個實施例中，通過回焊製程將第二元件封裝件300結合至第一元件封裝件200。在此回焊製程期間，導電連接件314接觸接合墊304B及金屬化圖案106以將第二元件封裝件300物理地且電耦合至第一元件封裝件200。在結合製程之後，在金屬化圖案106與導電連接件314的介面處且還在導電連接件314與接合墊304B之間的介面（未示出）處形成IMC（未示出）。
在圖11中，進一步通過將第一元件封裝件200安裝至基板400而將第一元件封裝件200及第二元件封裝件300貼附至基​​板400。可將基板400稱為封裝件基板400。使用導電連接件138將第一元件封裝件200安裝至封裝件基板400。
封裝件基板400可由例如矽、鍺、金剛石或類似物等半導體材料製成。作為另外一種選擇，也可使用例如矽鍺、碳化矽、砷化鎵、砷化銦、磷化銦、碳化矽鍺、磷化鎵砷、磷化鎵銦、其組合或類似物等化合物材料。另外，封裝件基板400可為絕緣體上半導體基板。一般來說，絕緣體上半導體基板包括例如磊晶矽、鍺、矽鍺、絕緣體上半導體、絕緣體上矽鍺、或其組合等半導體材料的層。在一個替代性實施例中，封裝件基板400是基於絕緣芯體，例如玻璃纖維加強型樹脂芯體等。一個示例性芯體材料為玻璃纖維樹脂（例如，FR4）。芯體材料的另一些選擇包括雙馬來酰亞胺三嗪BT樹脂，或作為另外一種選擇，包括其他印刷電路板材料或膜。可對封裝件基板400使用例如味之素增層膜等增層膜或其他積層體。
封裝件基板400可包括主動元件或被動元件（未示出）。如所屬領域中的普通技術人員應知到，可使用例如電晶體、電容器、電阻器、其組合等各種各樣的元件來產生封裝結構500設計中的結構性要求及功能性要求。可使用任何適合的方法來形成所述元件。
封裝件基板400也可包括金屬化層及孔（未示出）以及位於所述金屬化層及孔之上的接合墊402。金屬化層可形成於主動元件及被動元件之上並將所述金屬化層設計成連接各種元件，以形成功能性電路系統。金屬化層可由交替的介電（例如，低k介電質材料）層與導電材料（例如，銅）層以及具有對各導電材料層進行內連的孔所形成，並且可通過任何適合的製程（例如，沉積、鑲嵌、雙鑲嵌或類似製程等）來形成所述金屬化層。在某些實施例中，封裝件基板400實質上不含有主動元件及被動元件。
在某些實施例中，導電連接件138可進行回焊以將第一元件封裝件200貼附至接合墊402。導電連接件138將基板400（包括位於基板400中的金屬化層）電耦合至及/或物理地耦合至第一元件封裝件200。
在導電連接件138被回焊之前，導電連接件138上可形成有環氧樹脂焊劑（未示出），所述環氧樹脂焊劑的至少某些環氧樹脂部分會在將第一元件封裝件200貼附至基​​板400之後餘留。此餘留的環氧樹脂部分可充當底部填充體以減小應力並保護對導電連接件138進行回焊而得到的連接點。在某些實施例中，可在第一元件封裝件200與基板400之間形成環繞導電連接件138的底部填充體（未示出）。底部填充體可在貼附第一元件封裝件200之後通過毛細流動製程來形成，或者可在貼附第一元件封裝件200之前通過適合的沉積方法來形成所述底部填充體。
圖12A及圖12B是根據一些其他實施例中形成第一元件封裝件200的另一製程期間各中間步驟的各種圖​​。圖12A是剖視圖。圖12B是沿來自圖12A的參考橫截面A-A進行說明的平面圖。
在圖12A及圖12B中，於形成第一元件封裝件200時，在第一封裝區600中粘附多個積體電路晶粒114。如此一來，所述多個積體電路晶粒114分別具有機械力（mechanical force）較高的周界區。在第一封裝區600中，每一周界區具有其自己的內餘裕及外餘裕。
在圖12A及圖12B所示的實例中，積體被動元件組件142A及142B被視為靠近積體電路晶粒114的周界的兩個積體被動元件組件，原因是其分別與積體電路晶粒114的周界交叉或落於積體電路晶粒114的周界的餘裕中。如此一來，在積體被動元件組件142A及積體被動元件組件142B下方形成底部填充體148。
儘管圖8A、圖8B、圖12A、及圖12B示出的實例存在一個或兩個積體電路晶粒114及具有底部填充體148的一個或兩個積體被動元件組件142，然而應知，實施例的元件封裝件可含有任何數量的積體電路晶粒114，且可將任何數量的積體被動元件組件視為靠近積體電路晶粒114的周界。
圖13及圖14是根據一些其他實施例中形成第一元件封裝件200及封裝結構500的另一製程期間各中間步驟的各種圖​​。圖13是第一元件封裝件200的剖視圖。圖14是在使用圖13所示第一元件封裝件200形成封裝結構500的製程期間各中間步驟的剖視圖。在圖13中，不在載體基板100上形成背側重佈線結構110。相反地​​，形成介電層150。執行形成第一元件封裝件200的其餘步驟。形成暴露出穿孔112的開口152。在圖14中，經由介電層150中的開口152將導電連接件314物理地且電耦合至穿孔112。當各種元件的圖案密度低於閾值時，可省略背側重佈線結構110且可如圖13所示般形成第一元件封裝件200。
各實施例可實現多個優點。在封裝件上的一個或多個晶粒的周界附近的積體被動元件組件下方形成底部填充體，可保護所述積體被動元件組件免於承受所述晶粒所施加的機械力，而提高所述積體被動元件組件的可靠性。由於不在未暴露至晶粒所施加的機械力的積體被動元件組件下方形成底部填充體，因此選擇性地形成底部填充體還可降低封裝件形成成本。
在一些實施方式中，一種封裝結構的形成方法的步驟如下。形成第一封裝件，包括在第一載體基板之上形成孔；將第一晶粒貼附至所述第一載體基板，所述孔與所述第一晶粒相鄰，所述第一晶粒具有第一側及與所述第一側相對的第二側，所述第一側面對所述第一載體基板；以模製化合物包覆所述第一晶粒及所述孔；以及形成上覆在所述第一晶粒的所述第二側及所述模製化合物上的重佈線結構。將積體被動元件貼附至所述重佈線結構，所述積體被動元件的第一子集靠近所述第一晶粒的周界，所述積體被動元件的第二子集遠離所述第一晶粒的所述周界。在所述重佈線結構與所述積體被動元件的所述第一子集中的每一積體被動元件之間形成底部填充體，所述底部填充體不形成於所述重佈線結構與所述積體被動元件的所述第二子集中的每一積體被動元件之間。
在一些實施方式中，所述形成方法進一步包括將所述第一載體基板從所述第一封裝件剝離；以及將第二封裝件結合至所述第一封裝件，所述第一晶粒的所述第一側面對所述第二封裝件。在一些實施方式中，所述重佈線結構具有第一側及與所述第一側相對的第二側，所述第一側面對所述第一晶粒，所述第二側面對所述積體被動元件。在一些實施方式中，所述形成方法進一步包括將所述第一封裝件結合至第二載體基板，所述重佈線結構的所述第二側面對所述第二載體基板。在一些實施方式中，所述積體被動元件包括第一微凸塊連接。在一些實施方式中，將所述積體被動元件貼附至所述重佈線結構包括將所述積體被動元件的所述第一微凸塊連接焊接至所述重佈線結構的第二微凸塊連接。在一些實施方式中，所述底部填充體接觸所述積體被動元件的所述第一子集的所述第一微凸塊連接。在一些實施方式中，所述底部填充體不接觸所述積體被動元件的所述第二子集的所述第一微凸塊連接。在一些實施方式中，將所述積體被動元件貼附至所述重佈線結構包括將所述積體被動元件的所述第一子集在距離所述第一晶粒的所述周界小於30 μm處貼附至所述重佈線結構；以及將所述積體被動元件的所述第二子集在距離所述第一晶粒的所述周界大於30 μm處貼附至所述重佈線結構。
在一些實施方式中，一種封裝結構的形成方法的步驟如下。形成與第一晶粒相鄰的第一穿孔，所述第一晶粒具有第一側及與所述第一側相對的第二側。以模製材料包覆所述第一穿孔及所述第一晶粒。在所述第一晶粒的所述第一側、所述第一穿孔、及所述模製材料之上形成第一重佈線結構，所述第一重佈線結構具有面對所述第一晶粒的第一側及與所述第一側相對的第二側，所述第一晶粒具有周界。在所述第一重佈線結構的所述第二側上形成第一凸塊下金屬。將積體被動元件貼附至所述第一重佈線結構的所述第二側。在所述第一重佈線結構的所述第二側與所述積體被動元件的子集中的每一積體被動元件之間形成底部填充體，所述積體被動元件的所述子集靠近所述第一晶粒的所述周界。
在一些實施方式中，所述積體被動元件的所述子集處於所述第一晶粒的所述周界的30 μm以內。在一些實施方式中，所述積體被動元件的所述子集安置於所述第一晶粒的所述周界內側。在一些實施方式中，所述積體被動元件的所述子集安置於所述第一晶粒的所述周界外側。在一些實施方式中，其餘的積體被動元件遠離所述第一晶粒的所述周界。在一些實施方式中，所述其餘的積體被動元件距離所述第一晶粒的所述周界大於30 μm。在一些實施方式中，所述積體被動元件包括第一微凸塊連接，且其中形成所述底部填充體包括形成與所述積體被動元件的所述子集的所述第一微凸塊連接接觸的所述底部填充體。
在一些實施方式中，一種封裝結構包括第一封裝件、第一積體被動元件、第二積體被動元件以及底部填充體。第一封裝件包括第一晶粒、與第一晶粒相鄰的孔、包覆孔並圍繞第一晶粒的周界以至少橫向地包覆第一晶粒的模製化合物以及在第一晶粒及模製化合物之上延伸的第一重佈線結構。第一積體被動元件貼附至第一重佈線結構，第一積體被動元件靠近第一晶粒的周界安置。第二積體被動元件貼附至第一重佈線結構，第二積體被動元件遠離第一晶粒的周界安置。底部填充體安置於第一積體被動元件與第一重佈線結構之間，第二積體被動元件不含有底部填充體。
在一些實施方式中，所述的封裝結構更包括第一導電連接件，耦合至所述第一重佈線結構及所述第一積體被動元件，所述底部填充體接觸所述第一導電連接件；以及第二導電連接件，耦合至所述第一重佈線結構及所述第二積體被動元件，所述底部填充體不接觸所述第二導電連接件。在一些實施方式中，所述第一積體被動元件位於距離所述第一晶粒的所述周界小於30 μm處。在一些實施方式中，其特徵在於，所述第二積體被動元件位於距離所述第一晶粒的所述周界大於30 μm處。
以上概述了若干實施例的特徵，以使所屬領域中的技術人員可更好地理解本發明實施例的各個方面。所屬領域中的技術人員應知，其可容易地使用本發明實施例作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或實現與本文中所介紹的實施例相同的優點。所屬領域中的技術人員還應認識到，這些等效構造並不背離本發明實施例的精神及範圍，而且他們可在不背離本發明實施例的精神及範圍的條件下對其作出各種改變、代替、及變更。
100‧‧‧載體基板
102‧‧‧離型層
104、108‧‧‧介電層
106‧‧‧金屬化圖案
110‧‧‧背側重佈線結構
112、306‧‧‧穿孔
114‧‧‧積體電路晶粒
116‧‧‧粘合劑
118‧‧‧半導體基板
120‧‧‧內連線結構
122‧‧‧襯墊
124‧‧‧鈍化膜
126‧‧‧晶粒連接件
128‧‧‧介電質材料
130‧‧‧封裝體
132‧‧‧前側重佈線結構
134‧‧‧襯墊/凸塊下金屬
136‧‧‧襯墊/凸塊
138‧‧‧導電連接件/金屬柱連接件
140、142、142A、142B‧‧‧積體被動元件組件
144‧‧‧微凸塊
146‧‧‧焊料凸塊
148‧‧‧底部填充體
150‧‧‧膠帶/介電層
152‧‧‧開口
154‧‧‧單體化
200‧‧‧第一元件封裝件/積體扇出封裝件
300‧‧‧第二元件封裝件
302‧‧‧基板
304A、304B‧‧‧接合墊/凸塊下金屬
308A、308B‧‧‧晶粒
310‧‧‧鍵合線
312‧‧‧模製材料
314‧‧‧導電連接件
400‧‧‧基板/封裝件基板
402‧‧‧接合墊
500‧‧‧封裝結構
600‧‧‧第一封裝區
A-A‧‧‧參考橫截面
H1‧‧‧第一高度
H2‧‧‧第二高度
M1‧‧‧外餘裕
M2‧‧‧內餘裕
根據以下的詳細說明並配合所附圖式以了解本發明實施例。應注意的是，根據本產業的一般作業，各種特徵並未按照比例繪製。事實上，為了清楚說明，可能任意的放大或縮小元件的尺寸。 圖1至圖8A以及圖9至圖10是根據一些實施例中形成元件封裝件的製程期間各中間步驟的剖視圖。 圖8B是根據一些實施例中形成元件封裝件的製程期間各中間步驟的平面圖。 圖11是根據一些實施例中形成封裝結構的製程期間各中間步驟的剖視圖。 圖12A是根據一些實施例中形成元件封裝件的製程期間各中間步驟的剖視圖。 圖12B是根據一些實施例中形成元件封裝件的製程期間各中間步驟的平面圖。 圖13至圖14是根據一些實施例中形成元件封裝件的製程期間各中間步驟的剖視圖。

Claims (1)

  1. 一種封裝結構，包括： 第一封裝件，包括： 第一晶粒； 孔，與所述第一晶粒相鄰； 模製化合物，包覆所述孔並圍繞所述第一晶粒的周界以至少橫向地包覆所述第一晶粒；以及 第一重佈線結構，在所述第一晶粒及所述模製化合物之上延伸； 第一積體被動元件，貼附至所述第一重佈線結構，所述第一積體被動元件靠近所述第一晶粒的所述周界安置； 第二積體被動元件，貼附至所述第一重佈線結構，所述第二積體被動元件遠離所述第一晶粒的所述周界安置；以及 底部填充體，安置於所述第一積體被動元件與所述第一重佈線結構之間，所述第二積體被動元件不含有所述底部填充體。
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