CN108122857A - 封装结构 - Google Patents

封装结构 Download PDF

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Publication number
CN108122857A
CN108122857A CN201710284502.5A CN201710284502A CN108122857A CN 108122857 A CN108122857 A CN 108122857A CN 201710284502 A CN201710284502 A CN 201710284502A CN 108122857 A CN108122857 A CN 108122857A
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CN
China
Prior art keywords
passive components
integrated passive
die
layer
integrated
Prior art date
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Pending
Application number
CN201710284502.5A
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English (en)
Inventor
陈洁
余振华
叶德强
陈宪伟
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN108122857A publication Critical patent/CN108122857A/zh
Pending legal-status Critical Current

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Abstract

一种封装结构及其形成方法。封装结构包括第一封装件、第一集成无源元件、第二集成无源元件以及底部填充体。第一封装件包括第一管芯、与第一管芯相邻的孔、包封孔并围绕第一管芯的周界以至少横向地包封第一管芯的模制化合物以及在第一管芯及模制化合物之上延伸的第一重布线结构。第一集成无源元件贴附至第一重布线结构，第一集成无源元件靠近第一管芯的周界安置。第二集成无源元件贴附至第一重布线结构，第二集成无源元件远离第一管芯的周界安置。底部填充体安置于第一集成无源元件与第一重布线结构之间，第二集成无源元件不含有底部填充体。

Description

封装结构
技术领域
本发明实施例是有关于一种封装结构及其形成方法。
背景技术
由于不同电子组件(例如，晶体管、二极管、电阻器、电容器等)的集成密度的持续增进，半导体行业已经历快速增长。在很大程度上，集成密度的增进来自于最小特征尺寸(feature size)上不断地缩减，这允许更多的组件能够集成到给定区域内。随着对缩小电子元件的需求的增长，需要更小且更具创造性的半导体管芯封装技术。这种封装系统的一个实例是叠层封装(Package-on-Package，PoP)技术。在叠层封装元件中，顶部半导体封装件被堆叠于底部半导体封装件的顶面上，以提供高集成水平及组件密度。叠层封装技术一般能够生产功能性得到增强且在印刷电路板(printed circuit board，PCB)上占用空间小的半导体元件。
发明内容
一种封装结构包括第一封装件、第一集成无源元件、第二集成无源元件以及底部填充体。第一封装件包括第一管芯、与第一管芯相邻的孔、包封孔并围绕第一管芯的周界以至少横向地包封第一管芯的模制化合物以及在第一管芯及模制化合物之上延伸的第一重布线结构。第一集成无源元件贴附至第一重布线结构，第一集成无源元件靠近第一管芯的周界安置。第二集成无源元件贴附至第一重布线结构，第二集成无源元件远离第一管芯的周界安置。底部填充体安置于第一集成无源元件与第一重布线结构之间，第二集成无源元件不含有底部填充体。
附图说明
结合附图阅读以下详细说明，理解本发明实施例的各个方面。应注意，根据本产业中的标准惯例，各种特征并非按比例绘制。事实上，为论述清晰说明，可能任意增大或减小各种特征的尺寸。
图1至图8A以及图9至图10是根据一些实施例中形成元件封装件的工艺期间各中间步骤的剖视图。
图8B是根据一些实施例中形成元件封装件的工艺期间各中间步骤的平面图。
图11是根据一些实施例中形成封装结构的工艺期间各中间步骤的剖视图。
图12A是根据一些实施例中形成元件封装件的工艺期间各中间步骤的剖视图。
图12B是根据一些实施例中形成元件封装件的工艺期间各中间步骤的平面图。
图13至图14是根据一些实施例中形成元件封装件的工艺期间各中间步骤的剖视图。
[符号的说明]
100：载体衬底；
102：离型层；
104、108：介电层；
106：金属化图案；
110：背侧重布线结构；
112、306：穿孔；
114：集成电路管芯；
116：粘合剂；
118：半导体衬底；
120：内连线结构；
122：衬垫；
124：钝化膜；
126：管芯连接件；
128：介电质材料；
130：封装体；
132：前侧重布线结构；
134：衬垫/凸块下金属；
136：衬垫/凸块；
138：导电连接件/金属柱连接件；
140、142、142A、142B：集成无源元件组件；
144：微凸块；
146：焊料凸块；
148：底部填充体；
150：胶带/介电层；
152：开口；
154：单体化；
200：第一元件封装件/集成扇出封装件；
300：第二元件封装件；
302：衬底；
304A、304B：接合垫/凸块下金属；
308A、308B：管芯；
310：键合线；
312：模制材料；
314：导电连接件；
400：衬底/封装件衬底；
402：接合垫；
500：封装结构；
600：第一封装区；
A-A：参考横截面；
H1：第一高度；
H2：第二高度；
M1：外余裕；
M2：内余裕。
具体实施方式
以下公开内容提供用于实作本发明实施例的不同特征的许多不同的实施例或实例。以下阐述组件及排列的具体实例以简化本发明实施例。当然，这些仅为实例且不旨在进行限制。例如，以下说明中将第一特征形成在第二特征之上或第二特征上可包括其中第一特征及第二特征被形成为直接接触的实施例，且也可包括其中第一特征与第二特征之间可形成有附加特征、进而使得所述第一特征与所述第二特征可能不直接接触的实施例。另外，本公开内容可能在各种实例中重复使用参考编号及/或字母。这种重复使用是出于简洁及清晰的目的，而不是自身表示所论述的各种实施例及/或配置之间的关系。
此外，为易于说明，本文中可能使用例如“之下(beneath)”、“下面(below)”、“下部的(lower)”、“上方(above)”、“上部的(upper)”等空间相对性用语来阐述图中所示的一个部件或特征与另一(其他)部件或特征的关系。所述空间相对性用语旨在除图中所绘示的取向外还囊括元件在使用或操作中的不同取向。所述设备/元件可具有其他取向(旋转90度或处于其他取向)且本文中所用的空间相对性描述语可同样相应地进行解释。
根据各种实施例提供一种封装结构及其形成方法。具体来说，形成包括管芯的封装结构，且在所述封装结构上形成集成无源元件(integrated passive device，IPD)。在集成无源元件的子集(subset)与封装结构的重布线结构(redistribution structure)之间形成底部填充体(underfill)。仅对定位于封装结构上的特定位置中的集成无源元件形成底部填充体。例如，可对位于靠近封装结构中的管芯的周界的集成无源元件形成底部填充体。其他集成无源元件不具有底部填充体。选择性地形成底部填充体可在降低制造成本的同时提高最终结构的可靠性。对各实施例的一些变型进行论述。所属领域中的普通技术人员将易于理解可预期落于其他实施例范围内的其他变动。
图1至图10是根据一些实施例中形成第一元件封装件200的工艺期间各中间步骤的各种图。图1至图8A以及图9至图10是剖视图。图8B是沿来自图8A的参考横截面A-A进行说明的平面图。
在图1中，示出处于处理的中间阶段的第一元件封装件200，第一元件封装件200包括形成于载体衬底100上的离型层(release layer)102。用于形成第一元件封装件200的第一封装区600也被示出。尽管仅示出一个封装区600，然而也可形成有多个封装区。
载体衬底100可为玻璃载体衬底、陶瓷载体衬底或类似物等。载体衬底100可为晶片，进而使得可在载体衬底100上同时形成多个封装件。离型层102可由聚合物系材料形成，所述聚合物系材料可与载体衬底100一起从将在后续步骤中形成的上覆结构上被移除。在某些实施例中，离型层102是会在受热时失去其粘着特性的环氧树脂系热释放材料，例如光热转换(light-to-heat-conversion，LTHC)释放涂层。在其他实施例中，离型层102可为会在被暴露至紫外光时失去其粘着特性的紫外光(ultra-violet，UV)胶。离型层102可作为液体进行分配并进行固化，离型层102可为被积层至载体衬底100上的积层体膜(laminatefilm)，或可为其他形式。离型层102的顶表面可以是等高(leveled)且离型层102的顶表面可具有高共面程度(degree of coplanarity)。
在图2中，形成介电层104及金属化图案106(metallization pattern)。如图2所示，在离型层102上形成介电层104。介电层104的底表面可接触离型层102的顶表面。在某些实施例中，介电层104是由例如聚苯并恶唑(polybenzoxazole，PBO)、聚酰亚胺(polyimide)、苯并环丁烯(benzocyclobutene，BCB)或类似物等聚合物形成。在其他实施例中，介电层104是由以下材料形成：氮化物，例如氮化硅；氧化物，例如氧化硅、磷硅酸盐玻璃(phosphosilicate glass，PSG)、硼硅酸盐玻璃(borosilicate glass，BSG)、掺杂硼的磷硅酸盐玻璃(boron-doped phosphosilicate glass，BPSG)或类似物等；或者类似材料。通过例如旋转涂布(spin coating)、化学气相沉积(chemical vapor deposition，CVD)、积层(laminating)、类似工艺、或其组合等任何可接受的沉积工艺来形成介电层104。
在介电层104上形成金属化图案106。作为形成金属化图案106的实例，在介电层104之上形成晶种层(未示出)。在某些实施例中，晶种层为金属层，其可为单一层或包括由不同材料形成的多个子层的复合层。在某些实施例中，晶种层包括钛层及位于所述钛层之上的铜层。可使用例如物理气相沉积(physical vapor deposition，PVD)或类似工艺等来形成晶种层。接着形成光刻胶(photo resist)并将所述光刻胶图案化于晶种层上。可通过旋转涂布或类似工艺等来形成光刻胶并可将所述光刻胶暴露于光以进行图案化。光刻胶的图案对应于金属化图案106。所述图案化会形成穿过光刻胶以暴露出晶种层的开口。在光刻胶的开口中且在晶种层的暴露的部分上形成导电材料。可通过电镀(例如，电镀(electroplating)、无电电镀(electroless plating)或类似工艺等)来形成导电材料。导电材料可包括金属，如铜、钛、钨、铝或类似物等。接着，移除光刻胶以及部分上方未形成有导电材料的晶种层。通过可接受的灰化工艺(ashing process)或剥除工艺(strippingprocess)来移除光刻胶，例如使用氧等离子体或类似工艺等。一旦光刻胶被移除，则例如使用可接受的蚀刻工艺(如通过湿蚀刻(wet etching)或干蚀刻(dry etching))来移除被暴露的部分晶种层。晶种层的其余部分及导电材料会形成金属化图案106。
在图3中，在金属化图案106及介电层104上形成介电层108。在某些实施例中，介电层108是由可使用光刻掩模(lithography mask)进行图案化的聚合物形成，所述聚合物可为例如聚苯并恶唑、聚酰亚胺、苯并环丁烯或类似物等感光性材料。在其他实施例中，介电层108是由以下材料形成：氮化物，例如氮化硅；氧化物，例如氧化硅、磷硅酸盐玻璃、硼硅酸盐玻璃、掺杂硼的磷硅酸盐玻璃或类似物；或者类似材料。可通过旋转涂布、积层、化学气相沉积、类似工艺、或其组合来形成介电层108。接着将介电层108图案化以形成暴露出金属化图案106的某些部分的开口。通过可接受的工艺来进行所述图案化，例如当介电层为感光性材料时通过将介电层108暴露于光来进行所述图案化，或者通过使用例如各向异性蚀刻(anisotropic etch)进行蚀刻来进行所述图案化。
可将介电层104及108以及金属化图案106称作背侧重布线结构(back-sideredistribution structure)110。如图式所示，背侧重布线结构110包括所述两个介电层104及108及一个金属化图案106。在其他实施例中，背侧重布线结构110可包括任何数目的介电层、金属化图案、及孔。可通过重复进行所述形成金属化图案106及介电层108的工艺而在背侧重布线结构110中形成一个或多个额外的金属化图案及介电层。可在所述形成金属化图案期间通过在位于下方的介电层的开口中形成所述金属化图案的晶种层及导电材料来形成孔。所述孔可因此对不同金属化图案进行内连及电耦合。在某些实施例(在图13及图14示出)，背侧重布线结构110为可选的。如此一来，可不形成金属化图案106及位于介电层108中的开口。在某些实施例中，可仅当金属化图案106具有高于预定阈值(predefinedthreshold)的图案密度时，形成背侧重布线结构110。在此类实施例中，可从介电层进行增层而形成第一元件封装件200。
在图3中，形成穿孔112。作为形成穿孔112的实例，在背侧重布线结构110(例如，所示介电层108及金属化图案106被暴露出来的部分)之上形成晶种层。在某些实施例中，晶种层为金属层，其可为单一层或包括由不同材料形成的多个子层的复合层。在某些实施例中，晶种层包括钛层及位于所述钛层之上的铜层。可使用例如物理气相沉积或类似工艺等来形成晶种层。形成光刻胶并将所述光刻胶图案化于晶种层上。可通过旋转涂布或类似工艺等来形成光刻胶并可将所述光刻胶暴露于光以进行图案化。光刻胶的图案对应于穿孔。所述图案化会形成穿过光刻胶以暴露出晶种层的开口。在光刻胶的开口中且在晶种层的暴露的部分上形成导电材料。可通过电镀(例如，电镀、无电电镀或类似工艺等)来形成导电材料。导电材料可包括金属，如铜、钛、钨、铝或类似物等。移除光刻胶以及晶种层的部分上方未形成有导电材料的晶种层。通过可接受的灰化工艺或剥除工艺来移除光刻胶，例如使用氧等离子体或类似工艺等。一旦光刻胶被移除，则例如使用可接受的蚀刻工艺(例如通过湿蚀刻或干蚀刻)来移除被暴露的部分晶种层。晶种层的其余部分及导电材料会形成穿孔112。
在图4中，通过粘合剂116将集成电路管芯114粘合至介电层108。如图4所示，将一个集成电路管芯114粘合于第一封装区600中，且在其他实施例(将在以下图12A至图12B中论述)中，可在每一区中粘附更多或更少的集成电路管芯114。集成电路管芯114可为逻辑管芯(例如，中央处理单元(central processing unit)、微控制器等)、存储器管芯(例如，动态随机存取存储器(dynamic random access memory，DRAM)管芯、静态随机存取存储器(static random access memory，SRAM)管芯等)、电力管理管芯(例如，电力管理集成电路(power management integrated circuit，PMIC)管芯)、射频(radio frequency，RF)管芯、传感器管芯、微机电系统(micro-electro-mechanical-system，MEMS)管芯、信号处理管芯(例如，数字信号处理(digital signal processing，DSP)管芯)、前端管芯(例如，模拟前端(analog front-end，AFE)管芯)、类似的管芯、或其组合。此外，在某些实施例中，集成电路管芯114可为不同大小(例如，不同高度及/或表面积)，且在其他实施例中，集成电路管芯114可为相同大小(例如，相同高度及/或表面积)。
在粘附至介电层108之前，可根据适用于在集成电路管芯114中形成集成电路的制造工艺来加工集成电路管芯114。例如，集成电路管芯114各自分别包括半导体衬底118，例如经掺杂的或未经掺杂的硅、或绝缘体上半导体(semiconductor-on-insulator，SOI)衬底的作用层。半导体衬底可包含：其他半导体材料，例如锗；化合物半导体，包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、及/或锑化铟；合金半导体，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、及/或GaInAsP；或者其组合。也可使用例如多层式衬底(multi-layeredsubstrate)或梯度衬底(gradient substrate)等其他衬底。可在半导体衬底118中及/或半导体衬底118上形成例如晶体管、二极管、电容器、电阻器等元件且可通过由例如位于半导体衬底118上的一个或多个介电层中的金属化图案所形成的内连线结构120将各所述元件进行互连以形成集成电路。
集成电路管芯114进一步包括进行外部连接的衬垫122(例如铝衬垫)。垫122位于可被称为集成电路管芯114的相应作用侧的部位上。钝化膜(passivation film)124位于集成电路管芯114上且位于衬垫122的部分上。开口穿过钝化膜124到达衬垫122。例如导电柱(例如，包含例如铜等金属)等管芯连接件126位于穿过钝化膜124的开口中，并且机械至且电耦合至相对应的衬垫122。可通过例如电镀或类似方法等来形成管芯连接件126。管芯连接件126电耦合集成电路管芯114的相应集成电路。
介电质材料128位于集成电路管芯114的作用侧(active side)上，例如位于钝化膜124及管芯连接件126上。介电质材料128横向地(laterally)包封管芯连接件126，且介电质材料128横向地与相应集成电路管芯114相接。可将介电质材料128初始地形成为掩埋或覆盖管芯连接件126；当管芯连接件126被掩埋时，介电质材料128的顶表面可具有不均匀拓扑(topology)。介电质材料128可为聚合物(例如聚苯并恶唑、聚酰亚胺、苯并环丁烯或类似物等)、氮化物(例如氮化硅或类似物等)，氧化物(例如氧化硅、磷硅酸盐玻璃、硼硅酸盐玻璃、掺杂硼的磷硅酸盐玻璃或类似物等)、类似材料、或其组合，且可例如通过旋转涂布、积层、化学气相沉积或类似方法等来形成介电质材料128。
粘合剂116位于集成电路管芯114的背侧上并将集成电路管芯114粘附至背侧重布线结构110(例如图中的介电层108)。粘合剂116可为任何适合的粘合剂、环氧树脂、管芯贴合膜(die attach film，DAF)等。可将粘合剂116施加至集成电路管芯114的背侧，例如施加至相应半导体晶片的背侧或者可施加于载体衬底100的表面之上。可例如通过锯切(sawing)或切割(dicing)而将集成电路管芯114单体化，并使用例如拾取及放置工具(pick-and-place tool)通过粘合剂116而将集成电路管芯114粘附至介电层108。
在图5中，在各种组件上形成封装体(encapsulant)130。封装体130可为模制化合物、环氧树脂或类似物等，且可通过压缩模制(compression molding)、传递模制(transfermolding)或类似方法等来施加封装体130。可将封装体130形成于集成电路管芯114之上，进而使得管芯连接件126及/或穿孔112被隐埋或覆盖。在固化之后，封装体130可经历研磨工艺(grinding process)以暴露出穿孔112及管芯连接件126。所述研磨工艺也可对介电质材料128进行研磨。在研磨工艺之后，穿孔112的顶表面、管芯连接件126的顶表面、介电质材料128的顶表面、及封装体130的顶表面是共面的(coplanar)。研磨工艺可为例如化学机械抛光(chemical-mechanical polish，CMP)。在某些实施例中，例如若已暴露出穿孔112及管芯连接件126，则可省略所述研磨。
在图6中，在封装体130、穿孔112、及管芯连接件126上形成前侧重布线结构(front-side redistribution structure)132。前侧重布线结构132包括多个介电层及金属化图案。例如，可将前侧重布线结构132图案化成通过相应一个或多个介电层而彼此分隔开的多个分立的部分。前侧重布线结构132可为例如重布线层(redistribution layer，RDL)，且可包括金属迹线(或金属线)及位于所述金属迹线之下且连接至所述金属迹线的孔。根据本发明实施例的某些实施例，通过电镀工艺形成重布线层，其中所述重布线层中的每一者包括晶种层(未示出)及位于所述晶种层之上的经电镀金属材料。晶种层与经电镀金属材料可由相同材料或不同材料形成。
示出前侧重布线结构132作为实例。可在前侧重布线结构132中形成比所示出的前侧重布线结构132更多或更少的介电层及金属化图案。所属领域中的普通技术人员将易于理解，省略或重复进行哪些步骤及工艺可形成更多的或更少的介电层及金属化图案。
在图6中，进一步将前侧重布线结构132的顶部介电层图案化。所述图案化会形成暴露出金属化图案的某些部分的开口以用于随后形成导电垫。通过可接受的工艺来进行所述图案化，例如当介电层为感光性材料时通过将所述介电层暴露于光来进行所述图案化，或者通过使用例如各向异性蚀刻进行蚀刻来进行所述图案化。若介电层为感光性材料，则可在曝光之后对所述介电层进行显影。
在图7中，在前侧重布线结构132的外侧(exterior side)上形成衬垫134及136。使用衬垫134及136对各导电连接件进行耦合。在所示实施例中，经由穿过介电层到达前侧重布线结构132的金属层的开口来形成衬垫134及136。作为形成衬垫134及136的实例，在介电层之上形成晶种层(未示出)。在某些实施例中，晶种层为金属层，其可为单一层或包括由不同材料形成的多个子层的复合层。在某些实施例中，晶种层包括钛层及位于所述钛层之上的铜层。可使用例如物理气相沉积或类似工艺等来形成晶种层。接着形成光刻胶并将所述光刻胶图案化于晶种层上。可通过旋转涂布或类似工艺等来形成光刻胶并可将所述光刻胶暴露于光以进行图案化。光刻胶的图案对应于前侧重布线结构132中的导电垫。所述图案化会形成穿过光刻胶以暴露出晶种层的开口。在光刻胶的开口中且在晶种层的暴露的部分上形成导电材料。可通过电镀(例如，电镀、无电电镀或类似工艺等)来形成导电材料。导电材料可包括金属，如铜、钛、钨、铝或类似物等。接着，移除光刻胶以及部分上方未形成有导电材料的晶种层。通过可接受的灰化工艺或剥除工艺来移除光刻胶，例如使用氧等离子体或类似工艺等。一旦光刻胶被移除，则例如使用可接受的蚀刻工艺(如通过湿蚀刻或干蚀刻)来移除被暴露的部分晶种层。晶种层的其余部分及导电材料会形成衬垫134及136。在其中以不同的方式形成衬垫134及136的实施例中，可使用更多的光刻胶及图案化步骤。
尽管被示出的衬垫134及136为具有不同尺寸，然而应知，衬垫134及136可为各种连接类型及尺寸。此外，衬垫134与衬垫136可为不同尺寸或相同尺寸。例如，在某些实施例中，衬垫134可为凸块下金属(under bump metallurgy，UMB)且衬垫136可为微凸块(microbump)。如此一来，在本文中，可将衬垫134称作凸块下金属134且可将衬垫136称作凸块136。可在同一电镀工艺(如上论述)中形成衬垫134与衬垫136或可在不同电镀工艺中形成衬垫134与衬垫136。
在图8A及图8B中，在凸块下金属134上形成导电连接件138且在凸块136上安装集成无源元件组件140及142。在某些实施例中，可在将集成无源元件组件140及142安装于凸块136上之前，在凸块下金属134上形成导电连接件138。在某些实施例中，可在将集成无源元件组件140及142安装于凸块136上之后，在凸块下金属134上形成导电连接件138。
导电连接件138可为球栅阵列封装(ball grid array，BGA)连接件、焊料球、金属柱、受控塌陷芯片连接(controlled collapse chip connection，C4)凸块、微凸块、无电镀镍钯浸金技术(electroless nickel-electroless palladium-immersion goldtechnique，ENEPIG)形成的凸块或类似物等。导电连接件138可包含例如焊料、铜、铝、金、镍、银、钯、锡、类似材料、或其组合等导电材料。在某些实施例中，通过使用例如蒸镀(evaporation)、电镀、印刷、焊料转移(solder transfer)、植球(ball placement)或类似工艺等常用方法初始地形成焊料层来形成导电连接件138。一旦已在所述结构上形成焊料层，则可执行回焊(reflow)以将所述材料造型成所需凸块形状。在另一实施例中，导电连接件138为通过溅镀(sputtering)、印刷、电镀、无电电镀、化学气相沉积或类似工艺等而形成的金属柱(例如铜柱)。所述金属柱可不含有焊料且具有实质上垂直的侧壁。在某些实施例中，在金属柱连接件138的顶部上形成金属盖层(metal cap layer)(未示出)。金属盖层可包含镍、锡、锡-铅、金、银、钯、铟、镍-钯-金、镍-金、类似材料、或其组合，且可通过电镀工艺来形成所述金属盖层。
在结合至前侧重布线结构132之前，可根据适用于在集成无源元件组件140及142中形成无源元件的制造工艺来加工集成无源元件组件140及142。例如，集成无源元件组件140及142各自分别包括位于所述集成无源元件组件的主体结构中的一个或多个无源元件。所述主体结构可包括衬底及/或封装体。在所述主体结构包括衬底的实施例中，所述衬底可为半导体衬底，例如经掺杂的或未经掺杂的硅、或绝缘体上半导体衬底的作用层。半导体衬底可包含：其他半导体材料，例如锗；化合物半导体，包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、及/或锑化铟；合金半导体，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、及/或GaInAsP；或者其组合。也可使用例如多层式衬底或梯度衬底等其他衬底。无源元件可包括电容器、电阻器、电感器、类似元件、或其组合。可在半导体衬底中及/或半导体衬底上及/或在封装体内形成所述无源元件，且可通过由例如位于主体结构上的一个或多个介电层中的金属化图案形成的内连线结构将各所述元件进行互连以形成集成无源元件组件140及142。集成无源元件组件140与集成无源元件组件142可为相同类型的集成无源元件组件或可为不同类型的集成无源元件组件。集成无源元件组件140及142可为表面安装元件(surfacemount device，SMD)、2端子集成无源元件(2-terminal IPD)、多端子集成无源元件(multi-terminal IPD)、或其他类型的无源元件。在集成无源元件组件140及142上形成耦合至集成无源元件组件140及142的微凸块144，微凸块144进行外部连接。
在微凸块144的端部上形成焊料凸块146，进而在微凸块144与凸块136之间形成焊料接头(solder joint)，由此将前侧重布线结构132耦合至集成无源元件组件140及142。与在球栅阵列封装(BGA)连接件(例如，导电连接件138)中使用的所具有的直径可介于例如约150μm至约300μm范围内的传统焊料球相比，微凸块具有小得多的直径，例如介于约10μm至约40μm范围内。微凸块可在某些实施例中具有为约40μm或大于40μm的节距(pitch)。
将集成无源元件组件140及142贴附至第一元件封装件200上的特定位置。如图8B所示，集成无源元件组件142位於靠近集成电路管芯114的周界。相比之下，集成无源元件组件140位於远离集成电路管芯114的周界。
在图8A及图8B中，进一步在靠近集成电路管芯114的周界的集成无源元件组件(例如，集成无源元件组件142)下方形成底部填充体148。图8A及图8B说明完全填充式底部填充方案(full-fill underfill scheme)，其中底部填充体148完全填充位于集成无源元件组件142与前侧重布线结构132之间的区域，并且环绕微凸块144、焊料凸块146、及凸块136。在某些实施例(未示出)中，可使用局部填充式底部填充方案(partial-fill underfillscheme)，其中底部填充体148局部填充位于集成无源元件组件142与前侧重布线结构132之间的区域。可在贴附集成无源元件组件142之后通过毛细流动工艺(capillary flowprocess)来形成底部填充体148，或者可在贴附集成无源元件组件142之前通过适合的沉积方法或印刷方法来形成底部填充体148。
第一元件封装件200的位于集成电路管芯114的周界处的区域可可能受到较高的机械力或机械应力。所述较高的机械力可使得位于所述周界处的集成无源元件组件因例如其触点(例如，微凸块144)开裂而出现故障。所述开裂可为局部开裂或横跨所述触点的完全开裂。若集成无源元件组件受到较高的机械力，则可将所述集成无源元件组件视为靠近集成电路管芯114的周界。靠近周界(proximity to the perimeter)可由平面图中评估。如此一来，尽管在剖视图中某些组件(例如，前侧重布线结构132)位于集成无源元件组件与集成电路管芯114之间，然而若所述集成无源元件组件在平面图中靠近周界，则仍可将所述集成无源元件组件视为靠近集成电路管芯114的周界。换句话说，集成无源元件组件是否直接位于集成电路管芯114的上方被用于评估靠近周界。在某些实施例中，当集成无源元件组件与集成电路管芯114的周界交叉时，将所述集成无源元件组件视为靠近集成电路管芯114的周界。在某些实施例中，当集成无源元件组件处于集成电路管芯114的周界的特定距离以内时，将所述集成无源元件组件视为靠近集成电路管芯114的周界。例如，如图8B所示，集成电路管芯114的周界可存在外余裕(exterior margin)M1或内余裕(interior margin)M2，进而使得当集成无源元件组件处于外余裕M1或内余裕M2以内时将所述集成无源元件组件视为靠近集成电路管芯114的周界。外余裕M1与内余裕M2可为相同的或可为不同的。在一个实施例中，外余裕M1为约30μm，且内余裕M2为约30μm。
在图8A及图8B所示实例中，由于集成无源元件组件142与集成电路管芯114的周界交叉，因此将集成无源元件组件142视为靠近集成电路管芯114的周界。相似地，由于集成无源元件组件140不与集成电路管芯114的周界交叉且不落于外余裕M1或内余裕M2中，因此将集成无源元件组件140视为远离集成电路管芯114的周界。如此一来，底部填充体148形成于集成无源元件组件142，但不形成于集成无源元件组件140下方。在集成无源元件组件142下方形成底部填充体148，可保护集成无源元件组件142免于承受集成电路管芯114所施加的机械力，而提高集成无源元件组件142的可靠性。由于不在未经受集成电路管芯114所施加的机械力的集成无源元件组件140下方形成底部填充体148，因此选择性地形成底部填充体148还可降低封装件形成成本。
在进行贴附之后，集成无源元件组件140及142从前侧重布线结构132延伸出第一高度H1，第一高度H1小于导电连接件138从前侧重布线结构132延伸出的第二高度H2。如此一来，当在衬底上安装第一元件封装件200时，存在足以容纳集成无源元件组件140及142的间隔高度(standoff height)。
在图9中，执行载体衬底剥离(carrier substrate de-bonding)以将载体衬底100从背侧重布线结构110(例如，介电层104)脱离(剥离)。根据某些实施例，所述剥离包括将例如激光或紫外光等光投射在离型层102上以使得离型层102在光的热量下分解，且可移除载体衬底100。接着将所述结构翻转并放置于胶带150上。
在图9中，进一步形成穿过介电层104的开口152以暴露出金属化图案106的部分。可例如使用激光钻孔(laser drilling)、蚀刻或类似工艺等来形成所述开口。
在图9中，进一步通过沿例如位于相邻封装区之间的切割道区(scribe lineregion)进行单体化154来执行单体化工艺(singulation process)。在某些实施例中，单体化154包括锯切工艺、激光工艺或其组合。单体化154将第一封装区600从相邻封装区(未示出)单体化。
在图10中，示出在单体化之后的所得第一元件封装件200，所得第一元件封装件200可来自于第一封装区600。也可将第一元件封装件200称作集成扇出(integrated fan-out，InFO)封装件200。在某些实施例中，在将第二元件封装件300(如下论述)结合至集成扇出封装件200之后，执行单体化工艺。
图11是根据一些实施例中形成封装结构500的工艺期间各中间步骤的剖视图。封装结构500可为叠层封装(PoP)结构。
在图11中，将第二元件封装件300贴附至第一元件封装件200。第二元件封装件300包括衬底302及耦合至衬底302的一个或多个堆叠管芯308(308A及308B)。衬底302可由例如硅、锗、金刚石或类似物等半导体材料制成。在某些实施例中，也可使用例如硅锗、碳化硅、砷化镓、砷化铟、磷化铟、碳化硅锗、磷化镓砷、磷化镓铟、其组合或类似物等化合物材料。另外，衬底302可为绝缘体上半导体(SOI)衬底。一般来说，绝缘体上半导体衬底包括例如磊晶硅、锗、硅锗、绝缘体上半导体、绝缘体上硅锗(silicon germanium on insulator，SGOI)或其组合等半导体材料的层。在一个替代性实施例中，衬底302是基于绝缘芯体，例如玻璃纤维加强型树脂芯体(fiberglass reinforced resin core)。一种示例性芯体材料为玻璃纤维树脂(例如，FR4)。芯体材料的另一些选择包括双马来酰亚胺三嗪(bismaleimide-tirazine，BT)树脂，或作为另外一种选择，包括其他印刷电路板(PCB)材料或膜。可对衬底302使用例如味之素增层膜(Ajinomoto build-up film，ABF)等增层膜或其他积层体。
衬底302可包括有源元件或无源元件(未示出)。所属领域中的普通技术人员应知到，可使用例如晶体管、电容器、电阻器、其组合或类似物等各种各样的元件来产生第二元件封装件300设计中的结构性要求及功能性要求。可使用任何适合的方法来形成所述元件。
衬底302也可包括金属化层(未示出)及穿孔306。可在有源元件及无源元件之上形成金属化层并将所述金属化层设计成连接各种元件，以形成功能性电路系统。金属化层可由交替的介电(例如，低k介电质材料)层与导电材料(例如，铜)层以及具有对各导电材料层进行内连的孔所形成，并且可通过任何适合的工艺(例如，沉积、镶嵌、双镶嵌(dualdamascene)或类似工艺等)来形成所述金属化层。在某些实施例中，衬底302实质上不含有有源元件及无源元件。
衬底302可具有接合垫304A及接合垫304B，接合垫304A位于衬底302的第一侧上以耦合至堆叠管芯308，接合垫304B位于衬底302的第二侧上以耦合至导电连接件314，衬底302的第二侧与第一侧相对。在某些实施例中，通过在衬底302的第一侧及第二侧上在介电层(未示出)中形成凹陷部(未示出)来形成接合垫304A及304B。凹陷部的形成使得接合垫304A及304B能够嵌置于介电层中。在其他实施例中，由于可在介电层上形成接合垫304A及304B，因此会省略所述凹陷部。在某些实施例中，接合垫304A及304B包括由铜、钛、镍、金、钯、类似材料、或其组合制成的薄晶种层(未示出)。可在所述薄晶种层之上沉积接合垫304A及304B的导电材料。可通过电化学电镀工艺(electro-chemical plating process)、无电电镀工艺、化学气相沉积、原子层沉积(atomic layer deposition，ALD)、物理气相沉积、类似工艺、或其组合来形成导电材料。在一个实施例中，接合垫304A及304B的导电材料为铜、钨、铝、银、金、类似材料、或其组合。
在一个实施例中，接合垫304A及304B为包括三层导电材料层的凸块下金属，所述三层导电材料层例如为钛层、铜层、及镍层。然而，所属领域中的普通技术人员应知到尚有其它适用于形成凸块下金属304A及304B的材料与膜层的排列方式，例如铬/铬-铜合金/铜/金的排列方式、钛/钛钨/铜的排列方式、或铜/镍/金的排列方式。可用于凸块下金属304A及304B的任何适合的材料或材料层完全旨在包含于当前申请的范围内。在某些实施例中，穿孔306穿过衬底302而延伸且将至少一个接合垫304A耦合至至少一个接合垫304B。
在所示实施例中，尽管可使用例如导电凸块等其他连接方式，然堆叠管芯308是通过键合线(wire bonds)310耦合至衬底302。在一个实施例中，堆叠管芯308为堆叠的存储器管芯。例如，堆叠的存储器管芯308可包括低功率(low-power，LP)双倍数据速率(doubledata rate，DDR)存储器模组，例如LPDDR1、LPDDR2、LPDDR3、LPDDR4、或类似的存储器模组。
在某些实施例中，可通过模制材料312来包封堆叠管芯308及键合线310。可例如使用压缩模制将模制材料312模制于堆叠管芯308及键合线310上。在某些实施例中，模制材料312为模制化合物、聚合物、环氧树脂、氧化硅填料材料、类似材料、或其组合。可执行固化步骤以固化模制材料312，其中所述固化可为热固化、紫外光固化、类似固化方式、或其组合。
在某些实施例中，将堆叠管芯308及键合线310埋置于模制材料312中，且在固化模制材料312之后，执行例如研磨等平坦化步骤以移除模制材料312的过量部分，用以提供第二元件封装件300实质上平坦的表面。
在形成第二元件封装件300之后，通过导电连接件314、接合垫304B、背侧重布线结构110、及/或穿孔112，将第二元件封装件300结合至第一元件封装件200。在某些实施例中，通过键合线310、接合垫304A及304B、穿孔306、导电连接件314、及穿孔112可将堆叠的存储器管芯308耦合至集成电路管芯114。
尽管导电连接件138与导电连接件314无需相同，然而导电连接件314可相似于上述导电连接件138且本文中不再对其予以赘述。在某些实施例中，在结合导电连接件314之前，以例如免清洗焊剂(no-clean flux)等焊剂(未示出)涂布导电连接件314。可将导电连接件314浸入焊剂中或可将所述焊剂喷射至导电连接件314上。在另一实施例中，可将焊剂施加至背侧重布线结构110的表面。
在某些实施例中，在导电连接件314被回焊之前，导电连接件314上可形成有环氧树脂焊剂(未示出)，所述环氧树脂焊剂的至少某些环氧树脂部分会在将第二元件封装件300贴合至第一元件封装件200之后余留。此余留的环氧树脂部分可充当底部填充体以减小应力并保护对导电连接件314进行回焊而得到的连接点(joints)。在某些实施例中，可在第二元件封装件300与第一元件封装件200之间形成环绕导电连接件314的底部填充体(未示出)。底部填充体可在贴附第二元件封装件300之后通过毛细流动工艺来形成，或者可在贴附第二元件封装件300之前通过适合的沉积方法来形成所述底部填充体。
第二元件封装件300与第一元件封装件200之间的结合可为焊料结合或直接金属对金属(metal-to-metal)(例如，铜对铜(copper-to-copper)或锡对锡(tin-to-tin))结合。在一个实施例中，通过回焊工艺将第二元件封装件300结合至第一元件封装件200。在此回焊工艺期间，导电连接件314接触接合垫304B及金属化图案106以将第二元件封装件300物理地且电耦合至第一元件封装件200。在结合工艺之后，在金属化图案106与导电连接件314的介面处且还在导电连接件314与接合垫304B之间的介面(未示出)处形成IMC(未示出)。
在图11中，进一步通过将第一元件封装件200安装至衬底400而将第一元件封装件200及第二元件封装件300贴附至衬底400。可将衬底400称为封装件衬底400。使用导电连接件138将第一元件封装件200安装至封装件衬底400。
封装件衬底400可由例如硅、锗、金刚石或类似物等半导体材料制成。作为另外一种选择，也可使用例如硅锗、碳化硅、砷化镓、砷化铟、磷化铟、碳化硅锗、磷化镓砷、磷化镓铟、其组合或类似物等化合物材料。另外，封装件衬底400可为绝缘体上半导体衬底。一般来说，绝缘体上半导体衬底包括例如磊晶硅、锗、硅锗、绝缘体上半导体、绝缘体上硅锗、或其组合等半导体材料的层。在一个替代性实施例中，封装件衬底400是基于绝缘芯体，例如玻璃纤维加强型树脂芯体等。一个示例性芯体材料为玻璃纤维树脂(例如，FR4)。芯体材料的另一些选择包括双马来酰亚胺三嗪BT树脂，或作为另外一种选择，包括其他印刷电路板材料或膜。可对封装件衬底400使用例如味之素增层膜等增层膜或其他积层体。
封装件衬底400可包括有源元件或无源元件(未示出)。如所属领域中的普通技术人员应知到，可使用例如晶体管、电容器、电阻器、其组合等各种各样的元件来产生封装结构500设计中的结构性要求及功能性要求。可使用任何适合的方法来形成所述元件。
封装件衬底400也可包括金属化层及孔(未示出)以及位于所述金属化层及孔之上的接合垫402。金属化层可形成于有源元件及无源元件之上并将所述金属化层设计成连接各种元件，以形成功能性电路系统。金属化层可由交替的介电(例如，低k介电质材料)层与导电材料(例如，铜)层以及具有对各导电材料层进行内连的孔所形成，并且可通过任何适合的工艺(例如，沉积、镶嵌、双镶嵌或类似工艺等)来形成所述金属化层。在某些实施例中，封装件衬底400实质上不含有有源元件及无源元件。
在某些实施例中，导电连接件138可进行回焊以将第一元件封装件200贴附至接合垫402。导电连接件138将衬底400(包括位于衬底400中的金属化层)电耦合至及/或物理地耦合至第一元件封装件200。
在导电连接件138被回焊之前，导电连接件138上可形成有环氧树脂焊剂(未示出)，所述环氧树脂焊剂的至少某些环氧树脂部分会在将第一元件封装件200贴附至衬底400之后余留。此余留的环氧树脂部分可充当底部填充体以减小应力并保护对导电连接件138进行回焊而得到的连接点。在某些实施例中，可在第一元件封装件200与衬底400之间形成环绕导电连接件138的底部填充体(未示出)。底部填充体可在贴附第一元件封装件200之后通过毛细流动工艺来形成，或者可在贴附第一元件封装件200之前通过适合的沉积方法来形成所述底部填充体。
图12A及图12B是根据一些其他实施例中形成第一元件封装件200的另一工艺期间各中间步骤的各种图。图12A是剖视图。图12B是沿来自图12A的参考横截面A-A进行说明的平面图。
在图12A及图12B中，于形成第一元件封装件200时，在第一封装区600中粘附多个集成电路管芯114。如此一来，所述多个集成电路管芯114分别具有机械力(mechanicalforce)较高的周界区。在第一封装区600中，每一周界区具有其自己的内余裕及外余裕。
在图12A及图12B所示的实例中，集成无源元件组件142A及142B被视为靠近集成电路管芯114的周界的两个集成无源元件组件，原因是其分别与集成电路管芯114的周界交叉或落于集成电路管芯114的周界的余裕中。如此一来，在集成无源元件组件142A及集成无源元件组件142B下方形成底部填充体148。
尽管图8A、图8B、图12A、及图12B示出的实例存在一个或两个集成电路管芯114及具有底部填充体148的一个或两个集成无源元件组件142，然而应知，实施例的元件封装件可含有任何数量的集成电路管芯114，且可将任何数量的集成无源元件组件视为靠近集成电路管芯114的周界。
图13及图14是根据一些其他实施例中形成第一元件封装件200及封装结构500的另一工艺期间各中间步骤的各种图。图13是第一元件封装件200的剖视图。图14是在使用图13所示第一元件封装件200形成封装结构500的工艺期间各中间步骤的剖视图。在图13中，不在载体衬底100上形成背侧重布线结构110。相反地，形成介电层150。执行形成第一元件封装件200的其余步骤。形成暴露出穿孔112的开口152。在图14中，经由介电层150中的开口152将导电连接件314物理地且电耦合至穿孔112。当各种元件的图案密度低于阈值时，可省略背侧重布线结构110且可如图13所示般形成第一元件封装件200。
各实施例可实现多个优点。在封装件上的一个或多个管芯的周界附近的集成无源元件组件下方形成底部填充体，可保护所述集成无源元件组件免于承受所述管芯所施加的机械力，而提高所述集成无源元件组件的可靠性。由于不在未暴露至管芯所施加的机械力的集成无源元件组件下方形成底部填充体，因此选择性地形成底部填充体还可降低封装件形成成本。
在一些实施方式中，一种封装结构的形成方法的步骤如下。形成第一封装件，包括在第一载体衬底之上形成孔；将第一管芯贴附至所述第一载体衬底，所述孔与所述第一管芯相邻，所述第一管芯具有第一侧及与所述第一侧相对的第二侧，所述第一侧面对所述第一载体衬底；以模制化合物包封所述第一管芯及所述孔；以及形成上覆在所述第一管芯的所述第二侧及所述模制化合物上的重布线结构。将集成无源元件贴附至所述重布线结构，所述集成无源元件的第一子集靠近所述第一管芯的周界，所述集成无源元件的第二子集远离所述第一管芯的所述周界。在所述重布线结构与所述集成无源元件的所述第一子集中的每一集成无源元件之间形成底部填充体，所述底部填充体不形成于所述重布线结构与所述集成无源元件的所述第二子集中的每一集成无源元件之间。
在一些实施方式中，所述形成方法进一步包括将所述第一载体衬底从所述第一封装件剥离；以及将第二封装件结合至所述第一封装件，所述第一管芯的所述第一侧面对所述第二封装件。在一些实施方式中，所述重布线结构具有第一侧及与所述第一侧相对的第二侧，所述第一侧面对所述第一管芯，所述第二侧面对所述集成无源元件。在一些实施方式中，所述形成方法进一步包括将所述第一封装件结合至第二载体衬底，所述重布线结构的所述第二侧面对所述第二载体衬底。在一些实施方式中，所述集成无源元件包括第一微凸块连接。在一些实施方式中，将所述集成无源元件贴附至所述重布线结构包括将所述集成无源元件的所述第一微凸块连接焊接至所述重布线结构的第二微凸块连接。在一些实施方式中，所述底部填充体接触所述集成无源元件的所述第一子集的所述第一微凸块连接。在一些实施方式中，所述底部填充体不接触所述集成无源元件的所述第二子集的所述第一微凸块连接。在一些实施方式中，将所述集成无源元件贴附至所述重布线结构包括将所述集成无源元件的所述第一子集在距离所述第一管芯的所述周界小于30μm处贴附至所述重布线结构；以及将所述集成无源元件的所述第二子集在距离所述第一管芯的所述周界大于30μm处贴附至所述重布线结构。
在一些实施方式中，一种封装结构的形成方法的步骤如下。形成与第一管芯相邻的第一穿孔，所述第一管芯具有第一侧及与所述第一侧相对的第二侧。以模制材料包封所述第一穿孔及所述第一管芯。在所述第一管芯的所述第一侧、所述第一穿孔、及所述模制材料之上形成第一重布线结构，所述第一重布线结构具有面对所述第一管芯的第一侧及与所述第一侧相对的第二侧，所述第一管芯具有周界。在所述第一重布线结构的所述第二侧上形成第一凸块下金属。将集成无源元件贴附至所述第一重布线结构的所述第二侧。在所述第一重布线结构的所述第二侧与所述集成无源元件的子集中的每一集成无源元件之间形成底部填充体，所述集成无源元件的所述子集靠近所述第一管芯的所述周界。
在一些实施方式中，所述集成无源元件的所述子集处于所述第一管芯的所述周界的30μm以内。在一些实施方式中，所述集成无源元件的所述子集安置于所述第一管芯的所述周界内侧。在一些实施方式中，所述集成无源元件的所述子集安置于所述第一管芯的所述周界外侧。在一些实施方式中，其余的集成无源元件远离所述第一管芯的所述周界。在一些实施方式中，所述其余的集成无源元件距离所述第一管芯的所述周界大于30μm。在一些实施方式中，所述集成无源元件包括第一微凸块连接，且其中形成所述底部填充体包括形成与所述集成无源元件的所述子集的所述第一微凸块连接接触的所述底部填充体。
在一些实施方式中，一种封装结构包括第一封装件、第一集成无源元件、第二集成无源元件以及底部填充体。第一封装件包括第一管芯、与第一管芯相邻的孔、包封孔并围绕第一管芯的周界以至少横向地包封第一管芯的模制化合物以及在第一管芯及模制化合物之上延伸的第一重布线结构。第一集成无源元件贴附至第一重布线结构，第一集成无源元件靠近第一管芯的周界安置。第二集成无源元件贴附至第一重布线结构，第二集成无源元件远离第一管芯的周界安置。底部填充体安置于第一集成无源元件与第一重布线结构之间，第二集成无源元件不含有底部填充体。
在一些实施方式中，所述的封装结构更包括第一导电连接件，耦合至所述第一重布线结构及所述第一集成无源元件，所述底部填充体接触所述第一导电连接件；以及第二导电连接件，耦合至所述第一重布线结构及所述第二集成无源元件，所述底部填充体不接触所述第二导电连接件。在一些实施方式中，所述第一集成无源元件位于距离所述第一管芯的所述周界小于30μm处。在一些实施方式中，其特征在于，所述第二集成无源元件位于距离所述第一管芯的所述周界大于30μm处。
以上概述了若干实施例的特征，以使所属领域中的技术人员可更好地理解本发明实施例的各个方面。所属领域中的技术人员应知，其可容易地使用本发明实施例作为设计或修改其他工艺及结构的基础来实施与本文中所介绍的实施例相同的目的及/或实现与本文中所介绍的实施例相同的优点。所属领域中的技术人员还应认识到，这些等效构造并不背离本发明实施例的精神及范围，而且他们可在不背离本发明实施例的精神及范围的条件下对其作出各种改变、代替、及变更。

Claims (1)

1.一种封装结构，其特征在于，包括：
第一封装件，包括：
第一管芯；
孔，与所述第一管芯相邻；
模制化合物，包封所述孔并围绕所述第一管芯的周界以至少横向地包封所述第一管芯；以及
第一重布线结构，在所述第一管芯及所述模制化合物之上延伸；
第一集成无源元件，贴附至所述第一重布线结构，所述第一集成无源元件靠近所述第一管芯的所述周界安置；
第二集成无源元件，贴附至所述第一重布线结构，所述第二集成无源元件远离所述第一管芯的所述周界安置；以及
底部填充体，安置于所述第一集成无源元件与所述第一重布线结构之间，所述第二集成无源元件不含有所述底部填充体。
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