CN111261531A - 半导体器件和形成集成电路封装件的方法 - Google Patents

半导体器件和形成集成电路封装件的方法 Download PDF

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CN111261531A
CN111261531A CN201911205785.5A CN201911205785A CN111261531A CN 111261531 A CN111261531 A CN 111261531A CN 201911205785 A CN201911205785 A CN 201911205785A CN 111261531 A CN111261531 A CN 111261531A
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pad
integrated circuit
dielectric layer
conductive
flux
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CN111261531B (zh
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余人睿
裴浩然
陈威宇
张家纶
林修任
谢静华
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

在实施例中，半导体器件包括：集成电路管芯；密封剂，至少部分地密封集成电路管芯；位于密封剂上的再分布结构，再分布结构电连接至集成电路管芯，再分布结构包括焊盘；无源器件，包括物理和电连接至焊盘的导电连接件；以及保护结构，设置在无源器件和再分布结构之间，保护结构围绕导电连接件，保护结构包括环氧树脂助焊剂，保护结构中设置有空隙。本发明的实施例还涉及形成集成电路封装件的方法。

Description

半导体器件和形成集成电路封装件的方法
技术领域
本发明的实施例涉及半导体器件和形成集成电路封装件的方法。
背景技术
由于各个电子组件(例如，晶体管、二极管、电阻器、电容器等)的集成密度的不断提高，半导体工业经历了快速的增长。在大多数情况下，集成密度的改进来自最小部件尺寸的重复减小，这允许更多的组件集成到给定区域中。随着对缩小电子器件的需求的增长，已经出现了对更小且更具创造性的半导体管芯封装技术的需求。这种封装系统的实例是叠层封装(PoP)技术。在PoP器件中，顶部半导体封装件堆叠在底部半导体封装件的顶部上，以提供高水平的集成度和组件密度。PoP技术通常能够在印刷电路板(PCB)上生产功能增强且占位面积小的半导体器件。
发明内容
本发明的实施例提供了一种形成集成电路封装件的方法，包括：用密封剂密封集成电路管芯；在所述密封剂上形成再分布结构，所述再分布结构电连接至所述集成电路管芯，所述再分布结构包括第一焊盘和第二焊盘；在所述第一焊盘上分配环氧树脂助焊剂以形成保护结构；在固化所述环氧树脂助焊剂之前，将无源器件压入所述保护结构中以将所述无源器件物理耦合至所述第一焊盘；在所述第二焊盘上形成第一导电连接件；以及实施单个热处理工艺以同时固化所述保护结构并且回流所述第一导电连接件，在所述单个热处理工艺之后，所述第一导电连接件将所述无源器件物理和电耦合至所述第一焊盘。
本发明的另一实施例提供了一种形成集成电路封装件的方法，包括：用密封剂密封集成电路管芯；在所述密封剂和所述集成电路管芯上方沉积第一介电层；形成沿着所述第一介电层延伸并且穿过所述第一介电层的第一金属化图案，所述第一金属化图案电耦合所述集成电路管芯；在所述第一金属化图案上方沉积第二介电层；穿过所述第二介电层形成第一焊盘和第二焊盘，所述第一焊盘和所述第二焊盘电耦合所述第一金属化图案；利用环氧树脂助焊剂将无源器件粘附至所述第一焊盘和所述第二介电层，所述无源器件包括第一可回流连接件，在粘附所述无源器件之后，所述第一可回流连接件物理和电耦合至所述第一焊盘；在所述第二焊盘上形成所述第一助焊剂，所述第一助焊剂不同于所述环氧树脂助焊剂；在所述第一助焊剂上形成第二可回流连接件；以及实施单个热工艺以同时固化所述环氧树脂助焊剂，去除所述第一助焊剂，回流所述第一可回流连接件，并且回流所述第二可回流连接件。
本发明的又一实施例提供了一种半导体器件，包括：集成电路管芯；密封剂，至少部分地密封所述集成电路管芯；再分布结构，位于所述密封剂上，所述再分布结构电连接至所述集成电路管芯，所述再分布结构包括焊盘；无源器件，包括物理和电连接至所述焊盘的导电连接件；以及保护结构，设置在所述无源器件和所述再分布结构之间，所述保护结构围绕所述导电连接件，所述保护结构包括环氧树脂助焊剂，所述保护结构中设置有空隙。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该指出，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1示出了根据一些实施例的集成电路管芯的截面图。
图2、图3、图4、图5、图6、图7、图8、图9、图10、图11、图12、图13、图14、图16、图17、图18、图20和图21示出了根据一些实施例的在用于形成封装组件的工艺期间的中间步骤的截面图。
图19是示出根据一些实施例的热工艺步骤的各个方面的图。
图15A、图15B、图15C和图15D示出了根据一些实施例的无源器件的截面图。
图22和图23示出了根据一些实施例的器件堆叠件的形成和实施。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等间隔相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外，间隔相对术语旨在包括器件在使用或操作中的不同方位。器件可以以其它方式定向(旋转90度或在其它方位上)，而本文使用的间隔相对描述符可以同样地作出相应的解释。
根据一些实施例，形成再分布结构，并且在该再分布结构的表面上预填充保护结构。该保护结构由环氧树脂助焊剂形成，直接印刷在再分布结构的接触焊盘上，并且在印刷后不会立即固化。将诸如无源器件的表面安装器件(SMD)压入未固化的保护结构中，以物理和电耦合再分布结构的接触焊盘。诸如焊料连接件的外部连接件也形成在再分布结构的焊盘上。实施单个热工艺步骤以同时固化保护结构并且回流外部连接件和无源器件接触件。通过延迟固化并且与回流同时实施固化，可以省略一个或多个热工艺步骤，从而减少了晶圆处理时间和制造成本。
图1示出了根据一些实施例的集成电路管芯50的截面图。集成电路管芯50将在随后的工艺中被封装以形成集成电路封装件。集成电路管芯50可以是逻辑管芯(例如，中央处理器(CPU)、图形处理器(GPU)、片上系统(SoC)、应用处理器(AP)、微控制器等)、存储管芯(例如，动态随机存取存储器(DRAM)管芯、静态随机存取存储器(SRAM)管芯等)、电源管理管芯(例如，电源管理集成电路(PMIC)管芯)、射频(RF)管芯、传感器管芯、微机电系统(MEMS)管芯、信号处理管芯(例如，数字信号处理(DSP)管芯)、前端管芯(例如，模拟前端(AFE)管芯)等或它们的组合。
集成电路管芯50可以形成在晶圆中，该晶圆可以包括在后续步骤中分割以形成多个集成电路管芯的不同的器件区域。可以根据适用的制造工艺来处理集成电路管芯50以形成集成电路。例如，集成电路管芯50包括半导体衬底52，诸如掺杂或未掺杂的硅，或者绝缘体上半导体(SOI)衬底的有源层。半导体衬底52可以包括其它半导体材料，诸如锗；包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟的化合物半导体；包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP的合金半导体；或它们的组合。也可以使用其它衬底，诸如多层或梯度衬底。半导体衬底52具有有源表面(例如，图1中朝上的表面)，有时称为正面，以及非活性表面(例如，图1中朝下的表面)，有时称为背面。
器件54可以形成在半导体衬底52的正面处。器件54可以是有源器件(例如，晶体管、二极管等)、电容器、电阻器等。层间电介质(ILD)56位于半导体衬底52的正面上方。ILD56围绕并且可以覆盖器件54。ILD 56可以包括由诸如磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂磷硅酸盐玻璃(BPSG)、未掺杂硅酸盐玻璃(USG)等的材料形成的一个或多个介电层。
导电插塞58延伸穿过ILD 56，以电和物理方式耦合器件54。例如，当器件54是晶体管时，导电插塞58可以耦合晶体管的栅极和源极/漏极区域。导电插塞58可以由钨、钴、镍、铜、银、金、铝等或它们的组合形成。互连结构60位于ILD 56和导电插塞58上方。互连结构60互连器件54以形成集成电路。互连结构60可以由例如ILD 56上的介电层中的金属化图案形成。金属化图案包括形成在一个或多个低k介电层中的金属线和通孔。互连结构60的金属化图案通过导电插塞58电耦合至器件54。
集成电路管芯50还包括焊盘62，诸如铝焊盘，制成至集成电路管芯50的外部连接。焊盘62位于集成电路管芯50的有源侧上，诸如位于互连结构60中和/或上。一个或多个钝化膜64位于集成电路管芯50上，诸如位于互连结构60和焊盘62的部分上。开口穿过钝化膜64延伸至焊盘62。诸如导电柱(例如，由诸如铜的金属形成)的管芯连接件66延伸穿过钝化膜64中的开口，并且物理和电耦合至相应的焊盘62。管芯连接件66可以通过例如镀等形成。管芯连接件66电耦合集成电路管芯50的相应集成电路。
可选地，可以在焊盘62上设置焊料区域(例如，焊球或焊料凸块)。焊球可以用于在集成电路管芯50上实施芯片探针(CP)测试。可以在集成电路管芯50上实施CP测试，以确定集成电路管芯50是否是已知良好管芯(KGD)。因此，仅封装经过后续工艺的为KGD的集成电路管芯50，并且不封装未通过CP测试的管芯。在测试之后，可以在随后的工艺步骤中去除焊料区域。
介电层68可以(也可以不)位于集成电路管芯50的有源侧，诸如位于钝化膜64和管芯连接件66上。介电层68横向密封管芯连接件66，并且介电层68与集成电路芯片50横向共末端。最初，介电层68可以掩埋管芯连接件66，从而使得介电层68的最上表面位于管芯连接件66的最上表面之上。在焊料区域设置在管芯连接件66上的一些实施例中，介电层68也可以掩埋焊料区域。可选地，可以在形成介电层68之前去除焊料区域。
介电层68可以是诸如PBO、聚酰亚胺、BCB等的聚合物；诸如氮化硅等的氮化物；诸如氧化硅、PSG、BSG、BPSG等的氧化物；等或它们的组合。介电层68可以例如通过旋涂、层压、化学汽相沉积(CVD)等形成。在一些实施例中，在集成电路管芯50的形成期间，管芯连接件66通过介电层68暴露。在一些实施例中，管芯连接件66保持掩埋并且在随后的用于封装集成电路管芯50的工艺期间暴露。暴露管芯连接件66可以去除管芯连接件66上可能存在的任何焊料区域。
在一些实施例中，集成电路管芯50是包括多个半导体衬底52的堆叠器件。例如，集成电路管芯50可以是包括多个存储管芯的诸如混合存储器立方体(HMC)模块、高带宽存储器(HBM)模块等的存储器件。在这样的实施例中，集成电路管芯50包括通过衬底通孔(TSV)互连的多个半导体衬底52。每个半导体衬底52可以具有(或可以不具有)互连结构60。
图2至图21示出了根据一些实施例的用于形成第一封装组件100的工艺期间的中间步骤的截面图。示出了第一封装区域100A和第二封装区域100B，并且封装一个或多个集成电路管芯50以在每个封装区域100A和100B中形成集成电路封装件。集成电路封装件也可以称为集成扇出(InFO)封装件。
在图2中，提供了载体衬底102，并且释放层104形成在载体衬底102上。载体衬底102可以是玻璃载体衬底、陶瓷载体衬底等。载体衬底102可以是晶圆，从而使得可以在载体衬底102上同时形成多个封装件。释放层104可以由基于聚合物的材料形成，其可以与载体衬底102一起从将在后续步骤中形成的上面的结构中去除。在一些实施例中，释放层104是基于环氧树脂的热释放材料，其在加热时失去其粘合性，诸如光热转换(LTHC)释放涂层。在其它实施例中，释放层104可以是紫外(UV)胶，当暴露于UV光时会失去其粘合性。释放层104可以以液体的形式分配并且固化，可以是层压在载体衬底102上的层压膜，或者可以是类似的。释放层104的顶面可以是水平的并且可以具有较高的平面度。
在图3中，可以在释放层104上形成背侧再分布结构106。在所示的实施例中，背侧再分布结构106包括介电层108、金属化图案110(有时称为再分布层或再分布线)和介电层112。背侧再分布结构106是可选的。在一些实施例中，代替背侧再分布结构106，在释放层104上形成没有金属化图案的介电层。
介电层108可以形成在释放层104上。介电层108的底面可以与释放层104的顶面接触。在一些实施例中，介电层108由诸如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等的聚合物形成。在其它实施例中，介电层108由诸如氮化硅的氮化物；诸如氧化硅的氧化物、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)等；等形成。介电层108可以通过任何可接受的沉积工艺形成，诸如旋涂、CVD、层压等或它们的组合。
金属化图案110可以形成在介电层108上。作为形成金属化图案110的实例，在介电层108上方形成晶种层。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和位于钛层上方的铜层。可以使用例如物理汽相沉积(PVD)等形成晶种层。然后，在晶种层上形成并且图案化光刻胶。光刻胶可以通过旋涂等形成，并且可以暴露于光以用于图案化。光刻胶的图案对应于金属化图案110。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中和晶种层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀来形成导电材料。导电材料可以包括金属，如铜、钛、钨、铝等。然后，去除光刻胶和晶种层的其上未形成导电材料的部分。可以通过可接受的灰化或剥离工艺去除光刻胶，诸如使用氧等离子体等。一旦去除光刻胶，则去除晶种层的暴露部分，诸如通过使用可接受的蚀刻工艺，诸如通过湿蚀刻或干蚀刻。晶种层的剩余部分和导电材料形成金属化图案110。
介电层112可以形成在金属化图案110和介电层108上。在一些实施例中，介电层112由聚合物形成，该聚合物可以是光敏材料，诸如PBO、聚酰亚胺、BCB等，其可以使用光刻掩模来图案化。在其它实施例中，介电层112由诸如氮化硅的氮化物；诸如氧化硅、PSG、BSG、BPSG的氧化物；等形成。介电层112可以通过旋涂、层压、CVD等或它们的组合来形成。然后，图案化介电层112以形成暴露金属化图案110的部分开口114。可以通过可接受的工艺来形成图案，诸如当介电层112是光敏材料时通过将介电层112暴露于光或通过使用例如各向异性蚀刻的蚀刻。如果介电层112是光敏材料，则可以在曝光之后显影介电层112。
应该理解，背侧再分布结构106可以包括任何数量的介电层和金属化图案。如果要形成更多的介电层和金属化图案，则可以重复上述步骤和工艺。金属化图案可以包括导线和导电通孔。可以在金属化图案的形成期间通过在下面的介电层的开口中形成晶种层和金属化图案的导电材料来形成导电通孔。因此，导电通孔可以互连并且电耦合各个导线。
在图4中，通孔116形成在开口114中，并且远离背侧再分布结构106的最顶部介电层(例如，介电层112)延伸。作为形成通孔116的实例，在背侧再分布结构106上方形成晶种层，例如，在介电层112和金属化图案110的由开口114暴露的部分上。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和位于钛层上方的铜层。可以使用例如PVD等形成晶种层。然后，在晶种层上形成并且图案化光刻胶。光刻胶可以通过旋涂等形成，并且可以暴露于光以用于图案化。光刻胶的图案对应于导电通孔。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中和晶种层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀来形成导电材料。导电材料可以包括金属，如铜、钛、钨、铝等。然后，去除光刻胶和晶种层的其上未形成导电材料的部分。可以通过可接受的灰化或剥离工艺去除光刻胶，诸如使用氧等离子体等。一旦去除光刻胶，则去除晶种层的暴露部分，诸如通过使用可接受的蚀刻工艺，诸如通过湿蚀刻或干蚀刻。晶种层的剩余部分和导电材料形成通孔116。
在图5中，集成电路管芯50通过粘合剂118粘附至介电层112。期望类型和数量的集成电路管芯50粘附在每个封装区域100A和100B中。在所示的实施例中，包括第一集成电路管芯50A和第二集成电路管芯50B的多个集成电路管芯50彼此相邻地粘附。第一集成电路管芯50A可以是逻辑器件，诸如中央处理单元(CPU)、图形处理单元(GPU)、片上系统(SoC)、微控制器等。第二集成电路管芯50B可以是存储器件，诸如动态随机存取存储器(DRAM)管芯、静态随机存取存储器(SRAM)管芯、混合存储器立方体(HMC)模块、高带宽存储器(HBM)模块等。在一些实施例中，集成电路管芯50A和50B可以是相同类型的管芯，诸如SoC管芯。第一集成电路芯片50A和第二集成电路芯片50B可以在相同技术节点的工艺中形成，或者可以在不同技术节点的工艺中形成。例如，第一集成电路管芯50A可以具有比第二集成电路管芯50B更先进的工艺节点。集成电路管芯50A和50B可以具有不同的尺寸(例如，不同的高度和/或表面积)，或者可以具有相同的尺寸(例如，相同的高度和/或表面积)。可以限制封装区域100A和100B中的通孔116可用的空间，特别是当集成电路管芯50A和50B包括具有大占位面积的器件(诸如SoC)时。当封装区域100A和100B具有可用于通孔116的有限空间时，使用背侧再分布结构106允许改进的互连布置。
粘合剂118位于集成电路管芯50A和50B的背侧上，并且将集成电路管芯50A和50B粘附至背侧再分布结构106，诸如粘附至介电层112。粘合剂118可以是任何合适的粘合剂、环氧树脂、管芯附接膜(DAF)等。粘合剂118可以施加到集成电路管芯50A和50B的背侧，或者可以施加在载体衬底102的表面上方。例如，可以在分割以分离集成电路管芯50A和50B之前将粘合剂118施加到集成电路管芯50A和50B的背侧。
在图6中，在各个部件上和周围形成密封剂120。在形成之后，密封剂120密封通孔116和集成电路管芯50。密封剂120可以是模塑料、环氧树脂等。密封剂120可以通过压缩模塑、传递模塑等施加，并且可以形成在载体衬底102上方，从而掩埋或覆盖通孔116和/或集成电路管芯50。密封剂120还形成在集成电路管芯50之间的间隙区域(如果存在的话)中。密封剂120可以以液体或半液体形式施加，并且然后被固化。
在图7中，对密封剂120实施平坦化工艺以暴露通孔116和管芯连接件66。平坦化工艺还可去除通孔116、介电层68和/或管芯连接件66的材料，直至管芯连接件66和通孔116暴露。在平坦化工艺之后，通孔116、管芯连接件66、介电层68和密封剂120的顶面共面。平坦化工艺可以是例如化学机械抛光(CMP)、研磨工艺等。在一些实施例中，例如，如果通孔116和/或管芯连接件66已经暴露，则可以省略平坦化。
在图8至图12中，在密封剂120、通孔116和集成电路管芯50上方形成前侧再分布结构122(见图11)。前侧再分布结构122包括介电层124、128、132和136；金属化图案126、130和134；以及焊盘138A和138B。金属化图案也可以称为再分布层或再分布线。前侧再分布结构122示出为具有三层金属化图案的实例。可以在前侧再分布结构122中形成更多或更少的介电层和金属化图案。如果要形成较少的介电层和金属化图案，则可以省略下面讨论的步骤和工艺。如果要形成更多的介电层和金属化图案，则可以重复下面讨论的步骤和工艺。
在图8中，介电层124沉积在密封剂120、通孔116和管芯连接件66上。在一些实施例中，介电层124由诸如PBO、聚酰亚胺、BCB等的光敏材料形成，其可以使用光刻掩模来图案化。介电层124可以通过旋涂、层压、CVD等或它们的组合来形成。然后图案化介电层124。图案化形成暴露通孔116和管芯连接件66的部分的开口。可以通过可接受的工艺来图案化，诸如当介电层124是光敏材料时通过使介电层124暴露于光或通过使用例如各向异性蚀刻的蚀刻。如果介电层124是光敏材料，则可以在曝光之后显影介电层124。
然后形成金属化图案126。金属化图案126包括位于介电层124的主表面上并且沿着主表面延伸的线部分(也称为导线)。金属化图案126还包括延伸穿过介电层124以物理和电耦合通孔116和集成电路管芯50的通孔部分(也称为导电通孔)。作为形成金属化图案126的实例，在介电层124上方并且在延伸穿过介电层124的开口中形成晶种层。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和位于钛层上方的铜层。可以使用例如PVD等形成晶种层。然后，在晶种层上形成并且图案化光刻胶。光刻胶可以通过旋涂等形成，并且可以暴露于光以用于图案化。光刻胶的图案对应于金属化图案126。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中和晶种层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀来形成导电材料。导电材料可以包括金属，如铜、钛、钨、铝等。然后，去除光刻胶和晶种层的其上未形成导电材料的部分。可以通过可接受的灰化或剥离工艺去除光刻胶，诸如使用氧等离子体等。一旦去除光刻胶，则去除晶种层的暴露部分，诸如通过使用可接受的蚀刻工艺，诸如通过湿蚀刻或干蚀刻。
在图9中，介电层128沉积在金属化图案126和介电层124上。介电层128可以以类似于介电层124的方式形成，并且可以由与介电层124类似的材料形成。
然后形成金属化图案130。金属化图案130包括位于介电层128的主表面上并且沿着主表面延伸的线部分。金属化图案130还包括延伸穿过介电层128以物理和电耦合金属化图案126的通孔部分。金属化图案130可以以与金属化图案126类似的方式和类似的材料形成。在一些实施例中，金属化图案130具有与金属化图案126不同的尺寸。例如，金属化图案130的导线和/或通孔可以宽于或厚于金属化图案126的导线和/或通孔。此外，金属化图案130可以形成为比金属化图案126更大的间距。
在图10中，介电层132沉积在金属化图案130和介电层128上。介电层132可以以类似于介电层124的方式形成，并且可以由与介电层124类似的材料形成。
然后形成金属化图案134。金属化图案134包括位于介电层132的主表面上并且沿着主表面延伸的线部分。金属化图案134还包括延伸穿过介电层132以物理和电耦合金属化图案130的通孔部分。金属化图案134可以以与金属化图案126类似的方式和类似的材料形成。金属化图案134是前侧再分布结构122的最顶部金属化图案。因此，前侧再分布结构122的所有中间金属化图案(例如，金属化图案126和130)设置在金属化图案134和集成电路管芯50之间。在一些实施例中，金属化图案134具有与金属化图案126和130不同的尺寸。例如，金属化图案134的导线和/或通孔可以宽于或厚于金属化图案126和130的导线和/或通孔。此外，金属化图案134可以形成为比金属化图案130更大的间距。
在图11中，介电层136沉积在金属化图案134和介电层132上。介电层136可以以类似于介电层124的方式形成，并且可以由与介电层124相同的材料形成。介电层136是前侧再分布结构122的最顶部介电层。因此，前侧再分布结构122的所有金属化图案(例如，金属化图案126、130和134)设置在介电层136和集成电路管芯50之间。此外，前侧再分布结构122的所有中间介电层(例如，介电层124、128、132)设置在介电层136和集成电路管芯50之间。
在图12中，焊盘138A和138B形成在介电层136上并且延伸穿过介电层136。作为形成焊盘138A和138B的实例，可以图案化介电层136以形成暴露金属化图案134的部分的开口。图案化可以通过可接受的工艺进行，诸如当介电层136是光敏材料时通过将介电层136暴露于光或通过使用例如各向异性蚀刻的蚀刻。如果介电层136是光敏材料，则可以在曝光之后显影介电层136。用于焊盘138A和138B的开口可以比用于金属化图案126、130和134的导电通孔的开口宽。在介电层136上方和开口中形成晶种层。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和位于钛层上方的铜层。可以使用例如PVD等形成晶种层。然后，在晶种层上形成并且图案化光刻胶。光刻胶可以通过旋涂等形成，并且可以暴露于光以用于图案化。光刻胶的图案对应于焊盘138A和138B。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中和晶种层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀来形成导电材料。导电材料可以包括金属，如铜、钛、钨、铝等。然后，去除光刻胶和晶种层的其上未形成导电材料的部分。可以通过可接受的灰化或剥离工艺去除光刻胶，诸如使用氧等离子体等。一旦去除光刻胶，则去除晶种层的暴露部分，诸如通过使用可接受的蚀刻工艺，诸如通过湿蚀刻或干蚀刻。晶种层的剩余部分和导电材料形成焊盘138A和138B。在焊盘138A和138B以不同方式形成的实施例中，可以利用更多的光刻胶和图案化步骤。
在所示的实施例中，焊盘138A大于焊盘138B。例如，焊盘138A可具有在约30μm至约1000μm的范围内的宽度，并且焊盘138B可具有在约100μm至约760μm的范围内的宽度。在另一实施例中，焊盘138A可以小于焊盘138B。焊盘138A可以用于耦合至表面安装无源器件146(见图14)，并且焊盘138B可以用于耦合至导电连接件164(见图17)。应该理解，焊盘138A和138B可以是多种连接类型和尺寸。此外，焊盘138A和138B可以具有相同的尺寸。在一些实施例中，焊盘138A是微凸块，并且焊盘138B是凸块下金属(UBM)。焊盘138A和138B可以以不同的工艺形成。例如，可以形成具有用于焊盘138A的图案的第一光刻胶，可以在第一光刻胶的图案中实施第一镀工艺，并且可以去除第一光刻胶。然后可以形成具有用于焊盘138B的图案的第二光刻胶，可以在第二光刻胶的图案中实施第二镀工艺，并且可以去除第二光刻胶。
在图13中，在焊盘138A上和周围形成保护结构140。在所示的实施例中，保护结构140的每个均是单个连续材料，并且由环氧树脂助焊剂形成。在另一实施例中，保护结构140可以包括多层材料。环氧树脂助焊剂是聚合材料，其包括用于形成导电连接件的助焊剂，并且还包括用于在形成之后密封和保护导电连接件的树脂。树脂可以是环氧基树脂、酚基树脂等。助焊剂可以是盐酸、磷酸、柠檬酸、氢溴酸、羧酸、氨基酸、无机酸与胺的盐等。当器件随后附接至焊盘138A时，由环氧树脂助焊剂形成保护结构140避免了助焊剂的使用。保护结构140可以通过使用(或不使用)模板142在焊盘138A上印刷、喷射或分配环氧树脂助焊剂来形成。模板142具有与将要分配环氧树脂助焊剂的目标区域相对应的开口144。实施保护结构140的使用还消除了在随后附接的器件下面模塑底部填充物的需要。保护结构140可以比用于形成底部填充的毛细流动工艺更快地用模板142印刷。因此，可以减少用于形成第一封装组件100的处理时间。此外，环氧树脂助焊剂在分配后不会立即固化。而且，固化工艺被延迟并且与随后形成的可回流材料的回流工艺同时实施。因此可以省略一个或多个热工艺步骤，并且未固化的保护结构140是粘性的，从而使得它们可以容易地模塑并且在工艺期间用作粘合剂。
在图14中，将无源器件146附接至焊盘138A。图15A至图15D是根据各个实施例的第一封装组件100的区域10的详细视图。图15A至图15D示出了无源器件146的附加细节，并且结合图14进行了描述。无源器件146在无源器件146的主结构中包括一个或多个无源器件。主结构可以包括衬底和/或密封剂。在包括衬底的实施例中，衬底可以是半导体衬底，诸如掺杂或未掺杂的硅，或SOI衬底的有源层。半导体衬底可以包括其它半导体材料，例如锗；包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟的化合物半导体；包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP的合金半导体；或它们的组合。也可以使用其它衬底，诸如多层或梯度衬底。无源器件可以包括电容器、电阻器、电感器等或它们的组合。无源器件可以形成在半导体衬底内和/或上和/或密封剂内，并且可以通过由金属结构形成的互连结构互连以形成无源器件146，该互连结构由例如主结构上的一个或多个介电层中的金属化图案形成。无源器件146可以是表面安装器件(SMD)、2终端集成无源器件(IPD)、多终端IPD或其它类型的无源器件。焊盘148形成在无源器件146上并且耦合至无源器件146，形成至无源器件146的外部连接。焊盘148可以是例如微凸块。导电连接件150形成在焊盘148的端部上，并且包括例如可回流的材料。导电连接件150也可以称为可回流连接件。
可以使用例如拾取和放置工具将无源器件146附接至前侧再分布结构122。焊盘138A和148在放置期间对准。将无源器件146压入未固化的保护结构140中，从而使得焊盘148和导电连接件150延伸至未固化的保护结构140中并且由未固化的保护结构140围绕。未固化的保护结构140将无源器件146粘附至前侧再分布结构122。未固化的保护结构140可以不沿着无源器件146的侧壁146S延伸，例如，无源器件146的侧壁146S可以没有未固化的保护结构140的材料。保护结构140具有主体140B和填角140F。如上所述，用于保护结构140的固化工艺延迟并且与随后的回流步骤结合。通过在该工艺阶段省略热工艺步骤，可以缩短保护结构140的填角140F。在一些实施例中，填角140F的长度L1在从约1μm至约200μm的范围内。通过减小填角140F的长度L1，可以将相邻的无源器件146(或相邻的焊盘138B)之间的最小间隔减小多达200μm。在一些实施例中，相邻的无源器件146(或相邻的焊盘138B)之间的间隔在从约100μm至约600μm的范围内，诸如约150μm。因此，无源器件146的总占位面积可以减少，从而改善了前侧再分布结构122的电路布线。
未固化的保护结构140的粘性材料具有高的表面张力，因此，在放置期间可在相邻的导电连接件150之间形成空隙152。在一些实施例(例如，图15A)中，保护结构140将空隙152与无源器件146、介电层136、导电连接件150以及焊盘138A和148分隔开。在一些实施例(例如，图15B)中，保护结构140将空隙152与无源器件146和介电层136分隔开，并且空隙152暴露导电连接件150以及焊盘138A和148的表面。在一些实施例(例如，图15C)中，保护结构140将空隙152与导电连接件150以及焊盘138A和148分隔开，并且空隙152暴露无源器件146和介电层136的表面。在一些实施例(例如，图15D)中，空隙152暴露无源器件146、介电层136、导电连接件150以及焊盘138A和148的表面。
尽管图15A至图15D将保护结构140示出为每个都具有单个空隙152，但是应该理解，保护结构140的每个均可以具有多个空隙152。此外，尽管图15A至图15D将单个空隙152示出为位于每个保护结构140的中心，但是应该理解，空隙152可以设置在其它位置。例如，空隙152可以设置在保护结构140的中心或沿着保护结构140的边缘。
在图16中，在焊盘138B上形成助焊剂154。在用于使焊盘138B的表面脱氧的清洁工艺期间形成助焊剂154。助焊剂154不同于保护结构140的环氧树脂助焊剂。例如，助焊剂154可以是非环氧树脂助焊剂。在一些实施例中，助焊剂154是水、盐酸、磷酸、柠檬酸、氢溴酸、羧酸、氨基酸、无机酸与胺的盐等。可以利用模版156将助焊剂154分配在焊盘138B上。模板156具有对应于将分配助焊剂154(例如，对应于焊盘138B的图案)的目标区域的开口158。模版156还具有对应于无源器件146的凹槽160。模板156的凹槽160在清洁工艺期间覆盖无源器件146，从而使得在助焊剂分配工艺中，无源器件146设置在凹槽160中并且受到保护(例如，未与助焊剂154接触)。
在图17中，在助焊剂154上形成可回流材料162。可回流材料162可包括焊料、铜、铝、金、镍、银、钯、锡等或它们的组合。在一些实施例中，可回流材料162是焊料，其可以通过诸如蒸发、电镀、印刷、焊料转移、球放置等方法形成。在一些实施例中，在形成可回流材料162之后实施修复工艺。在修复工艺期间，识别并且更换有缺陷或缺失的可回流材料162。可回流材料162也可被称为可回流连接件。
在图18中，通过使可回流材料162回流而在焊盘138B上形成导电连接件164。所得的导电连接件164可以是球栅阵列(BGA)连接件、焊球等。在一些实施例中，实施单个热工艺步骤以同时固化保护结构140，使导电连接件150回流，并且使可回流材料162回流。关于热工艺步骤的细节在下面关于图19进一步讨论。在热工艺步骤之后，导电连接件150将无源器件146物理和电耦合至前侧再分布结构122。此外，可回流材料162通过热工艺步骤成形为期望的凸块形状，从而形成导电连接件164。助焊剂154可在热工艺步骤期间燃烧和/或蒸发，从而去除助焊剂154。最后，通过热工艺步骤来固化保护结构140，从而允许省略单独的固化工艺(例如，在回流之后)。固化的保护结构140保护导电连接件150以及焊盘138A和148，从而消除了在无源器件146下面形成底部填充物的需要。因此，可以省略用于底部填充物的模塑步骤和用于底部填充物的固化步骤，从而减少用于形成第一封装组件100的工艺时间。因此可以降低制造成本。
图19是示出根据一些实施例的热工艺步骤的温度和持续时间的图。热工艺步骤在几个不同的温度下实施。首先，温度从初始温度T0(例如，室温)升高至约150℃的第一温度T1。然后在约30s至约180s的时间段t1内将温度升高至约200℃的第二温度T2。从T1至T2的增加可以是非线性的。然后将温度进一步升高至约217℃的温度T3，并且甚至进一步升高至约260℃的温度T4。可回流材料162的回流发生在217℃和260℃之间，并且保护结构140的固化发生在回流工艺期间。对于从约30s至约150s的总时间段t2，温度保持在最小回流温度T3之上，其中，对于在从约20s至约100s的最大时间段t3，温度保持在最大回流温度T4处。然后，随着可回流材料162的冷却，温度降低回至初始温度T0。从最小回流温度T3至最大回流温度T4的增加速率可以高达约3℃/s，并且从最大回流温度T4至最小回流温度T3的降低速率可以高达约6℃/s。初始温度和最大回流温度T4之间的运行时间的总量可以高达约8分钟。
在图20中，实施载体衬底剥离以将载体衬底102与背侧再分布结构106(例如介电层108)分离(或“剥离”)。根据一些实施例，剥离包括在释放层104上投射诸如激光或UV光的光，使得释放层104在光的热量下分解并且可以去除载体衬底102。然后将结构翻转并且放置在带上。
在图21中，形成延伸穿过介电层108以接触金属化图案110的导电连接件166。穿过介电层108形成开口以暴露金属化图案110的部分。可以例如使用激光钻孔、蚀刻等形成开口。导电连接件166形成在开口中。在一些实施例中，导电连接件166包括助焊剂并且在助焊剂浸渍工艺中形成。在一些实施例中，导电连接件166包括诸如焊膏、银浆等的导电膏，并且在印刷工艺中分配。在一些实施例中，导电连接件166以类似于导电连接件164的方式形成，并且可以由与导电连接件164相同的材料形成。
图22和图23示出了根据一些实施例的器件堆叠件的形成和实施。器件堆叠件由形成在第一封装组件100中的集成电路封装件形成。器件堆叠件也可以称为叠层封装(PoP)结构。
在图22中，第二封装组件200耦合至第一封装组件100。第二封装组件200中的一个耦合在封装区域100A和100B的每个中以在第一封装组件100的每个区域中形成集成电路器件堆叠件。
第二封装组件200包括衬底202和耦合至衬底202的一个或多个管芯。在所示的实施例中，管芯包括堆叠的管芯210A和210B。在一些实施例中，管芯(或管芯堆叠件)可以并排设置为耦合至衬底202的相同表面。衬底202可以由诸如硅、锗、金刚石等的半导体材料制成。在一些实施例中，也可以使用诸如硅锗、碳化硅、砷化镓、砷化铟、磷化铟、碳化硅锗、磷砷化镓、磷化镓铟、这些的组合等的复合材料。另外，衬底202可以是绝缘体上硅(SOI)衬底。通常，SOI衬底包括半导体材料层，诸如外延硅、锗、硅锗、SOI、绝缘体上硅锗(SGOI)或它们的组合。在一个可选实施例中，衬底202是基于诸如玻璃纤维增强树脂芯的绝缘芯。一种示例性芯材料是玻璃纤维树脂，诸如FR4。用于芯材料的替代材料包括双马来酰亚胺三嗪(BT)树脂，或者其它印刷电路板(PCB)材料或薄膜。诸如味之素积聚膜(ABF)或其它层压材料的积聚膜可用于衬底202。
衬底202可以包括有源和无源器件(未示出)。可以使用诸如晶体管、电容器、电阻器、它们的组合的多种器件来生成第二封装组件200的设计的结构和功能要求。可以使用任何合适的方法来形成器件。
衬底202还可包括金属化层(未示出)和导电通孔208。金属化层可以形成在有源和无源器件上方，并且被设计为连接各种器件以形成功能电路。金属化层可以由电介质(例如，低k介电材料)和导电材料(例如，铜)(其具有互连导电材料层的通孔)的交替层形成，并且可以通过任何合适的工艺(诸如沉积、镶嵌、双镶嵌等)形成。在一些实施例中，衬底202基本上没有有源和无源器件。
衬底202可以在衬底202的第一侧上具有焊盘204，以耦合至堆叠管芯210A和210B、衬底202的第二侧上的接合焊盘206(第二侧与衬底202的第一侧相对)，以与导电连接件166耦合。在一些实施例中，通过在衬底202的第一侧和第二侧上的介电层(未示出)中形成凹槽来形成接合焊盘204和206。可以形成凹槽以允许接合焊盘204和206嵌入到介电层中。在其它实施例中，由于可以在介电层上形成接合焊盘204和206，因此省略凹槽。在一些实施例中，接合焊盘204和206包括由铜、钛、镍、金、钯等或它们的组合制成的薄晶种层。接合焊盘204和206的导电材料可以沉积在薄晶种层上方。可以通过电化学镀工艺、化学镀工艺、CVD、原子层沉积(ALD)、PVD等或它们的组合来形成导电材料。在实施例中，接合焊盘204和206的导电材料是铜、钨、铝、银、金等或它们的组合。
在实施例中，接合焊盘204和接合焊盘206是UBM，其包括三个导电材料层，诸如钛层、铜层和镍层。可以使用用于形成焊盘204和206的材料和层的其它布置，诸如铬/铬-铜合金/铜/金的布置、钛/钛钨/铜的布置或铜/镍/金的布置。可以用于接合焊盘204和206的任何合适的材料或材料层完全旨在包括在本申请的范围内。在一些实施例中，导电通孔208延伸穿过衬底202，并且将至少一个接合焊盘204耦合至至少一个接合焊盘206。
在示出的实施例中，堆叠的管芯210A和210B通过引线接合212耦合至衬底202，但是可以使用其它连接，诸如导电凸块。在实施例中，堆叠的管芯210A和210B是堆叠的存储器管芯。例如，堆叠的管芯210A和210B可以是存储管芯，诸如低功率(LP)双倍数据速率(DDR)存储模块，诸如LPDDR1、LPDDR2、LPDDR3、LPDDR4，或类似的存储模块。
堆叠的管芯210A和210B以及引线接合212可以由模塑材料214密封。模塑材料214可以模塑在引线接合212以及堆叠的管芯210A和210B上，例如，使用压缩模塑。在一些实施例中，模塑材料214是模塑料、聚合物、环氧树脂、氧化硅填充材料等或它们的组合。可以实施固化工艺以固化模塑材料214；固化工艺可以是热固化、UV固化等或它们的组合。
在一些实施例中，引线接合212以及堆叠的管芯210A和210B掩埋在模塑材料214中，并且在模塑材料214固化之后，实施诸如研磨的平坦化步骤以去除模塑材料214的过量部分，并且为第二封装组件200提供基本平坦的表面。
在形成第二封装组件200之后，第二封装组件200通过导电连接件166、接合焊盘206和背侧再分布结构106机械和电耦合至第一封装组件100。在一些实施例中，堆叠的管芯210A和210B可以通过引线接合212、接合焊盘204和206、导电通孔208、导电连接件166、背侧再分布结构106、通孔116和前侧再分布结构122耦合至集成电路管芯50。
在一些实施例中，在衬底202的与堆叠的管芯210A和210B相对的一侧上形成阻焊剂。导电连接件166可以设置在阻焊剂中的开口中，以电和机械耦合至衬底202中的导电部件(例如，接合焊盘206)。阻焊剂可用于保护衬底202的区域免受外部损坏。
在一些实施例中，导电连接件166可以具有在其上形成的可选环氧树脂助焊剂(未示出)，然后回流在将第二封装组件200附接至第一封装组件100之后剩余的环氧树脂助焊剂的至少一些环氧树脂部分。
在一些实施例中，在第一封装组件100和第二封装组件200之间形成围绕导电连接件166的底部填充物。底部填充可减少应力并且保护由于导电连接件166的回流引起的接头。底部填充物可以在第二封装组件200附接之后通过毛细管流动工艺形成，或者可以在第二封装组件200附接之前通过合适的沉积方法形成。在形成环氧树脂助焊剂的实施例中，它可以用作底部填充物。
在图23中，通过沿着例如第一封装区域100A和第二封装区域100B之间的划线区域锯切来实施分割工艺。锯切将第一封装区域100A与第二封装区域100B分开。所得的单个器件堆叠件来自第一封装区域100A或第二封装区域100B中的一个。在一些实施例中，在第二封装组件200耦合至第一封装组件100之后实施分割工艺。在其它实施例中，在第二封装组件200耦合至第一封装组件100之前实施分割工艺，诸如在将载体衬底102剥离并且形成导电连接件166之后。
然后使用导电连接件164将每个单独的第一封装组件100安装到封装衬底300。封装衬底300包括衬底芯302和位于衬底芯302上方的接合焊盘304。衬底芯302可以由半导体材料制成，诸如硅、锗、金刚石等。可选地，也可以使用诸如硅锗、碳化硅、砷化镓、砷化铟、磷化铟、碳化硅锗、磷砷化镓、磷化镓铟、这些的组合等的复合材料。另外，衬底芯302可以是SOI衬底。通常，SOI衬底包括半导体材料层，诸如外延硅、锗、硅锗、SOI、SGOI或它们的组合。在可选实施例中，衬底芯302是基于诸如玻璃纤维增强树脂芯的绝缘芯。一种示例性芯材料是玻璃纤维树脂，诸如FR4。芯材的替代材料包括双马来酰亚胺-三嗪BT树脂，或者可选地包括其它PCB材料或膜。诸如ABF或其它层压材料的积聚膜可用于衬底芯302。
衬底芯302可以包括有源和无源器件(未示出)。如本领域的普通技术人员将意识到，诸如晶体管、电容器、电阻器、它们的组合等的多种器件可以用于生成用于器件堆叠件的设计的结构和功能要求。可以使用任何合适的方法来形成器件。
衬底芯302还可包括金属化层和通孔(未示出)，其中接合焊盘304物理和/或电耦合至金属化层和通孔。金属化层可以形成在有源和无源器件上方，并且被设计为连接各个器件以形成功能电路。金属化层可以由电介质(例如，低k介电材料)和导电材料(例如，铜)(其具有互连导电材料层的通孔)的交替层形成，并且可以通过任何合适的工艺形成(诸如沉积、镶嵌、双重镶嵌等)。在一些实施例中，衬底芯302基本上没有有源和无源器件。
在一些实施例中，回流导电连接件164以将第一封装组件100附接至接合焊盘304。导电连接件164将包括位于衬底芯302中的金属化层的封装衬底300电和/或物理耦合至第一封装组件100。在一些实施例中，阻焊剂形成在衬底芯302上。导电连接件164可以设置在阻焊剂中的开口中，以电和机械耦合至接合焊盘304。阻焊剂可用于保护衬底202的区域免受外部损坏。
导电连接件164可以具有在其上形成的可选环氧树脂助焊剂(未示出)，然后回流在将第一封装组件100附接至封装衬底300之后剩余的环氧树脂助焊剂的至少一些环氧树脂部分。该剩余的环氧树脂部分可以用作底部填充物以减小应力并且保护由导电连接件164的回流产生的接头。在一些实施例中，底部填充物306可以形成在第一封装组件100和封装衬底300之间并且围绕导电连接件164。底部填充物306可以在附接第一封装组件100之后通过毛细管流动工艺形成，或者可以在附接第一封装组件100之前通过合适的沉积方法形成。底部填充物306接触表面安装无源器件146和保护结构140的表面。
在一些实施例中，无源器件(例如，表面安装器件(SMD)，未示出)也可以附接至封装衬底300(例如，附接至接合焊盘304)。例如，无源器件可以与导电连接件164耦合至第一封装组件100或封装衬底300的相同表面。无源器件可以在将第一封装组件100安装在封装衬底300上之前附接至封装组件100，或者可以在将第一封装组件100安装在封装衬底300上之前或之后附接至封装衬底300。
应该理解，第一封装组件100可以在其它器件堆叠件中实现。例如，示出了PoP结构，但是第一封装组件100也可以在倒装芯片球栅阵列(FCBGA)封装件中实现。在这样的实施例中，将第一封装组件100安装至诸如封装衬底300的衬底，但是省略第二封装组件200。而且，可以将盖或散热器附接至第一封装组件100。当省略第二封装组件200时，也可以省略背侧再分布结构106和通孔116。
也可以包括其它部件和工艺。例如，可以包括测试结构以辅助3D封装件或3DIC器件的验证测试。测试结构可以包括例如形成在再分布层中或衬底上的测试焊盘，其允许使用探针和/或探针卡等对3D封装件或3DIC测试。验证测试可以对中间结构以及最终结构实施。另外，本文公开的结构和方法可以与结合已知良好管芯的中间验证的测试方法结合使用，以增加良率并且降低成本。
实施例可以实现许多优势。在附接无源器件146之前分配保护结构140可以消除对底部填充物的需要，从而减少了无源器件146的总占位面积。通过在相同的热工艺步骤中固化保护结构140并且使可回流材料162回流，可以省略一个或多个热工艺步骤，从而减少了晶圆处理时间和制造成本。
在实施例中，方法包括：用密封剂密封集成电路管芯；在所述密封剂上形成再分布结构，该再分布结构电连接至集成电路管芯，再分布结构包括第一焊盘和第二焊盘。在第一焊盘上分配环氧树脂助焊剂以形成保护结构；在固化环氧树脂助焊剂之前，将无源器件压入保护结构以将无源器件物理耦合至第一焊盘；在第二焊盘上形成第一导电连接件；并且实施单个热工艺以同时固化所述保护结构并且回流第一导电连接件，第一导电连接件在单个热工艺之后将无源器件物理和电耦合至第一焊盘。
在一些实施例中，该方法还包括：将集成电路管芯放置为邻近导电通孔，再分布结构电连接至导电通孔；并且用密封剂密封导电通孔。在该方法的一些实施例中，无源器件包括第二导电连接件，将该无源器件压入保护结构中，直至第二导电连接件接触第一焊盘，第二导电连接件包括可回流材料。在该方法的一些实施例中，实施单个热工艺回流第二导电连接件。在该方法的一些实施例中，保护结构具有设置在无源器件和再分布结构之间的空隙。在该方法的一些实施例中，保护结构将空隙与无源器件、再分布结构、第二导电连接件和第一焊盘分隔开。在该方法的一些实施例中，保护结构将空隙与无源器件和再分布结构分隔开，并且空隙暴露第二导电连接件和第一焊盘的表面。在该方法的一些实施例中，保护结构将空隙与第二导电连接件和第一焊盘分隔开，并且空隙暴露无源器件和再分布结构的表面。在该方法的一些实施例中，空隙暴露第二导电连接件、第一焊盘、无源器件和再分布结构的表面。
在实施例中，方法包括：用密封剂密封集成电路管芯；在密封剂和集成电路管芯上方沉积第一介电层；形成沿着第一介电层延伸并且穿过第一介电层的第一金属化图案，第一金属化图案电耦合集成电路管芯；在第一金属化图案上方沉积第二介电层；穿过第二介电层形成第一焊盘和第二焊盘，第一焊盘和第二焊盘电耦合第一金属化图案；用环氧树脂助焊剂将无源器件粘附至第一焊盘和第二介电层，该无源器件包括第一可回流连接件，在粘附无源器件之后，第一可回流连接件物理和电耦合至第一焊盘；在第二焊盘上形成第一助焊剂，该第一助焊剂不同于环氧树脂助焊剂；在第一助焊剂上形成第二可回流连接件；并且实施单个热工艺以同时固化环氧树脂助焊剂，去除第一助焊剂，回流第一可回流连接件以及回流第二回流连接件。
在一些实施例中，该方法还包括：用第一模版在第一焊盘上印刷环氧树脂助焊剂，第一模版具有暴露第一焊盘的第一开口。在该方法的一些实施例中，在第二焊盘上形成第一助焊剂包括：用第二模板在第二焊盘上印刷第一助焊剂，第二模板具有暴露第二焊盘的第二开口，第二模板具有覆盖无源器件的凹槽。在该方法的一些实施例中，在粘附无源器件之后，环氧树脂助焊剂具有设置在无源器件和第二介电层之间的主体以及沿着第二介电层远离主体延伸的填角，主体中设置有空隙。在该方法的一些实施例中，环氧树脂助焊剂的填角远离主体延伸第一距离，该第一距离在从1μm至200μm。在一些实施例中，该方法还包括：使用第二可回流连接件将封装衬底附接至第二焊盘；并且在封装衬底和第二介电层之间形成底部填充物，底部填充物接触环氧树脂助焊剂和无源器件的侧。
在实施例中，器件包括：集成电路管芯；密封剂，至少部分地密封集成电路管芯；位于密封剂上的再分布结构，该再分布结构电连接至集成电路管芯，该再分布结构包括焊盘；无源器件，包括物理和电连接至焊盘的导电连接件；以及设置在无源器件和再分布结构之间的保护结构，该保护结构围绕导电连接件，该保护结构包括环氧树脂助焊剂，该保护结构中设置有空隙。
在器件的一些实施例中，保护结构将空隙与无源器件、再分布结构、导电连接件和焊盘分隔开。在器件的一些实施例中，保护结构将空隙与无源器件和再分布结构分隔开，并且空隙暴露导电连接件和焊盘的表面。在器件的一些实施例中，保护结构将空隙与导电连接件和焊盘分隔开，并且空隙暴露无源器件和再分布结构的表面。在器件的一些实施例中，空隙暴露导电连接件、焊盘、无源器件和再分布结构的表面。
上面概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解，它们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。

Claims (10)

1.一种形成集成电路封装件的方法，包括：
用密封剂密封集成电路管芯；
在所述密封剂上形成再分布结构，所述再分布结构电连接至所述集成电路管芯，所述再分布结构包括第一焊盘和第二焊盘；
在所述第一焊盘上分配环氧树脂助焊剂以形成保护结构；
在固化所述环氧树脂助焊剂之前，将无源器件压入所述保护结构中以将所述无源器件物理耦合至所述第一焊盘；
在所述第二焊盘上形成第一导电连接件；以及
实施单个热处理工艺以同时固化所述保护结构并且回流所述第一导电连接件，在所述单个热处理工艺之后，所述第一导电连接件将所述无源器件物理和电耦合至所述第一焊盘。
2.根据权利要求1所述的方法，还包括：
将所述集成电路管芯放置为邻近导电通孔，所述再分布结构电连接至所述导电通孔；以及
用所述密封剂密封所述导电通孔。
3.根据权利要求1所述的方法，其中，所述无源器件包括第二导电连接件，将所述无源器件压入所述保护结构中，直至所述第二导电连接件接触所述第一焊盘，所述第二导电连接件包括可回流材料。
4.根据权利要求3所述的方法，其中，实施所述单个热工艺来回流所述第二导电连接件。
5.根据权利要求3所述的方法，其中，所述保护结构具有设置在所述无源器件和所述再分布结构之间的空隙。
6.根据权利要求5所述的方法，其中，所述保护结构将所述空隙与所述无源器件、所述再分布结构、所述第二导电连接件和所述第一焊盘分隔开。
7.根据权利要求5所述的方法，其中，所述保护结构将所述空隙与所述无源器件和所述再分布结构分隔开，并且所述空隙暴露所述第二导电连接件和所述第一焊盘的表面。
8.根据权利要求5所述的方法，其中，所述保护结构将所述空隙与所述第二导电连接件和所述第一焊盘分隔开，并且所述空隙暴露所述无源器件和所述再分布结构的表面。
9.一种形成集成电路封装件的方法，包括：
用密封剂密封集成电路管芯；
在所述密封剂和所述集成电路管芯上方沉积第一介电层；
形成沿着所述第一介电层延伸并且穿过所述第一介电层的第一金属化图案，所述第一金属化图案电耦合所述集成电路管芯；
在所述第一金属化图案上方沉积第二介电层；
穿过所述第二介电层形成第一焊盘和第二焊盘，所述第一焊盘和所述第二焊盘电耦合所述第一金属化图案；
利用环氧树脂助焊剂将无源器件粘附至所述第一焊盘和所述第二介电层，所述无源器件包括第一可回流连接件，在粘附所述无源器件之后，所述第一可回流连接件物理和电耦合至所述第一焊盘；
在所述第二焊盘上形成所述第一助焊剂，所述第一助焊剂不同于所述环氧树脂助焊剂；
在所述第一助焊剂上形成第二可回流连接件；以及
实施单个热工艺以同时固化所述环氧树脂助焊剂，去除所述第一助焊剂，回流所述第一可回流连接件，并且回流所述第二可回流连接件。
10.一种半导体器件，包括：
集成电路管芯；
密封剂，至少部分地密封所述集成电路管芯；
再分布结构，位于所述密封剂上，所述再分布结构电连接至所述集成电路管芯，所述再分布结构包括焊盘；
无源器件，包括物理和电连接至所述焊盘的导电连接件；以及
保护结构，设置在所述无源器件和所述再分布结构之间，所述保护结构围绕所述导电连接件，所述保护结构包括环氧树脂助焊剂，所述保护结构中设置有空隙。
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