CN109786268B - 半导体封装件中的金属化图案及其形成方法 - Google Patents

半导体封装件中的金属化图案及其形成方法 Download PDF

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CN109786268B
CN109786268B CN201810691508.9A CN201810691508A CN109786268B CN 109786268 B CN109786268 B CN 109786268B CN 201810691508 A CN201810691508 A CN 201810691508A CN 109786268 B CN109786268 B CN 109786268B
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die
polymer material
encapsulant
package
metallization pattern
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CN109786268A (zh
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游济阳
陈海明
梁裕民
郑荣伟
李建勋
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

实施例方法包括：将半导体管芯密封在密封剂中，平坦化密封剂并且在密封剂上沉积聚合物材料。该方法还包括平坦化聚合物材料以及在聚合物材料上形成金属化图案。金属化图案将半导体管芯的管芯连接件电连接至设置在半导体管芯的外部的导电部件。本发明的实施例还涉及半导体封装件中的金属化图案及其形成方法。

Description

半导体封装件中的金属化图案及其形成方法
技术领域
本发明的实施例涉及半导体封装件中的金属化图案及其形成方法。
背景技术
由于各个电组件(例如，晶体管、二极管、电阻器、电容器等)的集成密度的持续改进，半导体工业已经经历了快速增长。对于大部分而言，这种集成密度的改进来自于最小部件尺寸的连续减小，这允许更多的组件集成到给定的区域。随着对电子器件缩小的需求不断增长，对半导体管芯的更小且更具创造性的封装技术的需求也已经出现。这种封装系统的实例是叠层封装(PoP)技术。在PoP器件中，顶部半导体封装件堆叠在底部半导体封装件的顶部以提供高集成度和组件密度。PoP技术一般能够在印刷电路板(PCB)上产生具有增强的功能和较小的覆盖区的半导体器件。
发明内容
本发明的实施例提供了一种形成封装件的方法，包括：将半导体管芯密封在密封剂中；平坦化所述密封剂；在所述密封剂上沉积聚合物材料；平坦化所述聚合物材料；以及在所述聚合物材料上形成金属化图案，其中，所述金属化图案将所述半导体管芯的管芯连接件电连接至设置在所述半导体管芯的外部的导电部件。
本发明的另一实施例提供了一种形成封装件的方法，包括：将第一集成电路管芯设置为与第二集成电路管芯相邻；将所述第一集成电路管芯和所述第二集成电路管芯密封在模塑料中，所述模塑料包括多种填充物；平坦化所述模塑料以暴露所述第一集成电路管芯的第一管芯连接件和所述第二集成电路管芯的第二管芯连接件，平坦化所述模塑料限定了所述模塑料的顶面处的多个凹陷；在所述模塑料上方沉积聚合物材料，所述聚合物材料设置在所述模塑料的顶面处的所述多个凹陷中；平坦化所述聚合物材料；以及在所述聚合物材料上方形成金属化图案，所述金属化图案将所述第一管芯连接件电连接至所述第二管芯连接件。
本发明的又一实施例提供了一种封装件，包括：集成电路管芯，包括管芯连接件；密封剂，设置在所述集成电路管芯周围；聚合物材料，位于所述密封剂的至少部分上方；杂质，设置在所述聚合物材料的顶面处，所述杂质的材料与所述聚合物材料不同；以及导线，位于所述聚合物材料上方，所述导线将所述管芯连接件电连接至导电部件，并且所述密封剂的部分设置在所述管芯连接件和所述导电部件之间。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该指出，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1、图2、图3、图4A、图4B、图5、图6A、图6B、图7A、图7B、图8A、图8B、图9A、图9B、图10A、图10B、图11A、图11B、图12、图13、图14、图15、图16、图17、图18、图19、图20、图21、图22、图23、图24、图25A和图25B示出了根据一些实施例的用于形成封装件的工艺期间的中间步骤的截面图。
图26A、图26B和图27示出了根据一些可选实施例的用于形成封装件的工艺期间的中间步骤的截面图。
图28A、图28B、图29A、图29B、图30A、图30B、图31A、图31B、图32A、图32B、图32C、图33A、图33B、图33C、图34A和图34B示出了根据一些可选实施例的用于形成封装件的工艺期间的中间步骤的截面图。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其它方式定向(旋转90度或在其它方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。
本文讨论的实施例可以在特定的上下文中讨论，即，具有设置在密封剂上的聚合物层的封装结构(例如，叠层封装(PoP)结构)。密封剂设置在一个或多个集成电路管芯以及穿过密封剂延伸的导电通孔周围。此外，可以分配、固化并且之后平坦化密封剂以暴露集成电路管芯的接触件和通孔。然而，由于设置在密封剂内的填充物，平坦化工艺可能导致模塑料在平坦化之后具有不平坦的顶面。该不平坦的顶面可能进一步引起形成在密封剂上方的部件中的制造缺陷。例如，一些填充物可能具有中空芯，并且平坦化这些填充物可能导致平坦化之后在模塑料的顶面处产生凹部(例如，由暴露中空芯产生)。即使没有中空芯填充物，平坦化之后的模塑料的表面纹理可能也会不期望地变粗糙。由于模塑料的凹部和粗糙表面，形成在模塑料上的金属化图案(有时称为再分布线或再分布层)可能遭受制造缺陷，诸如金属化图案中的断线(例如，导致开路)和/或金属化图案中的桥接线(例如，导致短路电路)。
在各个实施例中，为了对随后形成金属化图案提供改进的表面形貌，可以将聚合物材料分配在模塑料上。之后，可以将平坦化工艺应用于聚合物材料。在一些实施例中，聚合物材料可以基本不含填充物，与模塑料相比，不含填充物允许聚合物材料的上表面在平坦化之后具有改进的光滑度。已经观察到，通过在模塑料的顶面上包含该聚合物材料，可以有利地减少在模塑料上方形成的金属化图案中的制造缺陷。
图1至图25B示出了根据一些实施例的用于形成第一封装组件的工艺期间的中间步骤的截面图。图1示出了载体衬底100和形成在载体衬底100上的释放层102。示出了分别用于形成第一封装件和第二封装件的第一封装区域600和第二封装区域602。
载体衬底100可以是玻璃载体衬底、陶瓷载体衬底等。载体衬底100可以是晶圆，从而使得可以同时在载体衬底100上形成多个封装件。释放层102可以由基于聚合物的材料形成，其可以与载体衬底100一起从在随后的步骤中形成的上面的结构去除。在一些实施例中，释放层102是诸如光热转换(LTHC)释放涂层的基于环氧树脂的热释放材料，该材料在加热时失去其粘合性。在其它实施例中，释放层102可以是紫外(UV)胶，当暴露于UV光时失去其粘合性。释放层102可以以液体形式分配并且被固化，可以是层压在载体衬底100上的层压膜，或者可以是类似的。释放层102的顶面可以是齐平的并且可以具有高度的共面性。
图2至图3示出了可选背侧再分布结构110(见图3)和可选通孔112(见图3)的形成。在其它实施例中，可以省略背侧再分布结构110和通孔112(例如，见图4B和图25B的实施例)。在图2中，形成介电层104和金属化图案106(有时称为再分布层106或再分布线106)。如图2示出的，介电层104形成在释放层102上。介电层104的底面可以与释放层102的顶面接触。在一些实施例中，介电层104由诸如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等的聚合物形成。在其它实施例中，介电层104由氮化物，诸如氮化硅；氧化物，诸如氧化硅、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)等；等形成。可以通过诸如旋涂、化学汽相沉积(CVD)、层压等或它们的组合的任何可接受的沉积工艺形成介电层104。
在介电层104上形成金属化图案106。作为形成金属化图案106的实例，在介电层104上方形成晶种层(未示出)。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和位于钛层上方的铜层。可以使用例如PVD等形成晶种层。之后，在晶种层上形成并且图案化光刻胶。光刻胶可以通过旋涂等形成，并且可以暴露于光以用于图案化。光刻胶的图案对应于金属化图案106。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中和晶种层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括如铜、钛、钨、铝等的金属。之后，去除光刻胶和晶种层的其上未形成导电材料的部分。可以通过可接受的灰化或剥离工艺(诸如使用氧等离子体等)去除光刻胶。一旦去除光刻胶，则诸如通过使用可接受的蚀刻工艺(诸如湿或干蚀刻)去除晶种层的暴露部分。晶种层的剩余部分和导电材料形成金属化图案106。
在图3中，在金属化图案106和介电层104上形成介电层108。在一些实施例中，介电层108由聚合物形成，聚合物可以是可以使用光刻掩模图案化的诸如PBO、聚酰亚胺、BCB等的光敏材料。在其它实施例中，介电层108由氮化物，诸如氮化硅；氧化物，诸如氧化硅、PSG、BSG、BPSG；等形成。可以通过旋涂、层压、CVD等或它们的组合形成介电层108。之后，图案化介电层108以形成暴露金属化图案106的部分的开口。可以通过可接受的工艺图案化，诸如当介电层是光敏材料时通过将介电层108暴露于光或通过例如使用各向异性蚀刻的蚀刻。
介电层104和108以及金属化图案106可以称为背侧再分布结构110。如图所示，背侧再分布结构110包括两个介电层104和108以及一个金属化图案106。在其它实施例中，背侧再分布结构110可以包括任何数量的介电层、金属化图案和通孔，或可以完全省略背侧再分布结构110。通过重复用于形成金属化图案106和介电层108的工艺，可以在背侧再分布结构110中形成一个或多个额外的金属化图案和介电层。可以在通过在下面的介电层的开口中形成金属化图案的晶种层和导电材料的金属化图案的形成期间形成通孔。因此，通孔可以互连并且电连接各个金属化图案。在一些实施例中，可以排除背侧再分布结构110。
进一步在图3中，形成可选通孔112。作为形成通孔112的实例，在背侧再分布结构110(当存在时)上方(例如，在如图所示的介电层108和金属化图案106的暴露部分上方)形成晶种层。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和位于钛层上方的铜层。可以使用例如PVD等形成晶种层。在晶种层上形成并且图案化光刻胶。光刻胶可以通过旋涂等形成，并且可以暴露于光以用于图案化。光刻胶的图案对应于通孔。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中和晶种层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括如铜、钛、钨、铝等的金属。去除光刻胶和晶种层的其上未形成导电材料的部分。可以通过可接受的灰化或剥离工艺(诸如使用氧等离子体等)去除光刻胶。一旦去除光刻胶，则诸如通过使用可接受的蚀刻工艺(诸如湿或干蚀刻)去除晶种层的暴露部分。晶种层的剩余部分和导电材料形成通孔112。在一些实施例中，可以省略通孔112(例如，见图4B和图25B)。
在图4A中，通过粘合剂116将集成电路管芯114A和114B粘合至介电层108。如图4A所示，两个集成电路管芯114A/114B粘合在第一封装区域600和第二封装区域602的每个中，但是在其它实施例中，可以在每个区域中粘合更多或更少的集成电路管芯114A/114B。例如，在实施例中，可以在每个区域中仅粘合一个集成电路管芯114A和/或114B。集成电路管芯114A/114B可以是逻辑管芯(例如，中央处理单元、微控制器等)、存储器管芯(例如，动态随机存取存储器(DRAM)管芯、静态随机存取存储器(SRAM)管芯、混合存储立方体(HMC)、宽输入/输出(宽IO)存储器管芯、磁阻式随机存取存储器(mRAM)管芯、电阻式随机存取存储器(rRAM)管芯等)、电源管理管芯(例如，电源管理集成电路(PMIC)管芯)、射频(RF)管芯、传感器管芯、微电子机械系统(MEMS)管芯、信号处理管芯(例如，数字信号处理(DSP)管芯)、前端管芯(例如，模拟前端(AFE)管芯)等或它们的组合。例如，集成电路管芯114A/114B可以实施相同类型的功能或不同类型的功能。在实施例中，集成电路管芯114A是处理器管芯，而集成电路管芯114B是存储器管芯。而且，在一些实施例中，集成电路管芯114A/114B可以是不同的尺寸(例如，不同的高度和/或表面积)，并且在其它实施例中，集成电路管芯114A/114B可以是相同的尺寸(例如，相同的高度和/或表面积)。
在粘合至介电层108之前，可以根据可应用的制造工艺处理集成电路管芯114A/114B以在集成电路管芯114A/114B中形成集成电路。例如，集成电路管芯114A/114B每个均包括半导体衬底118，半导体衬底118诸如掺杂或未掺杂的硅或绝缘体上半导体(SOI)衬底的有源层。半导体衬底可以包括其它半导体材料，诸如锗；化合物半导体，包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟；合金半导体，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP；或它们的组合。也可以使用诸如多层衬底或梯度衬底的其它衬底。诸如晶体管、二极管、电容器、电阻器等的器件可以形成在半导体衬底118中和/或上，并且可以通过互连结构120互连以形成集成电路，互连结构120由半导体衬底118上的一个或多个介电层中的金属化图案形成。
集成电路管芯114A/114B还包括制成外部连接的焊盘122，诸如铝焊盘。焊盘122位于可以称为集成电路管芯114A/114B的相应的有源侧的位置上。钝化膜124位于集成电路管芯114A/114B上并且可以位于焊盘122的部分上。开口穿过钝化膜124至焊盘122。诸如导电柱(例如，包括诸如铜的金属)的管芯连接件126位于穿过钝化膜124的开口中并且机械和电连接至相应的焊盘122。可以通过例如镀等形成管芯连接件126。管芯连接件126电连接集成电路管芯114A/114B的相应集成电路。
介电材料128位于集成电路管芯114A的有源侧上，诸如位于钝化膜124和管芯连接件126上。介电材料128横向密封管芯连接件126，并且介电材料128与相应的集成电路管芯114横向共末端。介电材料128可以是聚合物，诸如PBO、聚酰亚胺、BCB等；氮化物，诸如氮化硅等；氧化物，诸如氧化硅、PSG、BSG、BPSG等；等或它们的组合，并且可以例如通过旋涂、层压、CVD等形成。此外，在一些实施例中，从集成电路管芯114B省略介电材料128，从而使得管芯连接件126的顶面和侧壁暴露。在其它实施例(未示出)中，可以在集成电路管芯114B的管芯连接件周围形成介电材料128。
粘合剂116位于集成电路管芯114A/114B的背侧上并且将集成电路管芯114A/114B粘合至背侧再分布结构110，诸如附图中的介电层108。粘合剂116可以是任何合适的粘合剂、环氧树脂、管芯附着膜(DAF)等。粘合剂116可以施加至集成电路管芯114A/114B的背侧(诸如相应的半导体晶圆的背侧)或可以施加在载体衬底100的表面上方。集成电路管芯114A/114B可以诸如通过锯切或切割被分割并且使用例如拾取和放置工具通过粘合剂116粘合至介电层108。在一些实施例(例如，如图4A示出的)中，在将集成电路管芯114A/114B附接至载体衬底100之前，将粘合剂116粘附至集成电路管芯114A/114B的每个。在其它实施例(例如，如图4B示出的)中，具体地当省略背侧RDL 110和通孔112时，可以将粘合剂116毯式沉积在载体衬底100上，从而使得连续的粘合剂116覆盖整个载体衬底100。在这种实施例中，在沉积粘合剂116之后，将集成电路管芯114A/114B放置在粘合剂116上并且粘合至载体衬底100。
在图5中，在各个组件上形成密封剂130。密封剂130可以是模塑料、环氧树脂等，并且可以通过压缩模塑、转移模塑等施加。密封剂130还可以包含填充物，诸如二氧化硅等(例如，填充物130A，见图6B)。在一些实施例中，密封剂130中的一些或全部填充物可以是中空的。密封剂130可以以液体形式分配在通孔112和集成电路管芯114A/114B周围。在暴露集成电路管芯114B的管芯连接件126的侧壁的实施例中，密封剂可以进一步分配在集成电路管芯114B的管芯连接件126周围。例如，密封剂130可以物理接触集成电路管芯114B的管芯连接件126。可以分配密封剂以覆盖通孔112和集成电路管芯114A/114B的顶面。在分配密封剂130之后，可以实施固化工艺以使密封剂130硬化。
在固化之后，如图6A示出的，密封剂130可以经历平坦化工艺(例如，机械研磨、化学机械抛光(CMP)等)以暴露通孔112和管芯连接件126。图6B示出了图6A中的区域604的详细的截面图。由于平坦化工艺，密封剂130的顶面可能是不平坦的。密封剂130的顶面的不平坦可以至少部分地由密封剂130中的填充物引起。例如，参照图6B，平坦化工艺可以暴露一个或多个填充物130A的中空芯130B，中空芯130B导致在密封剂130的顶面处产生凹部。此外，即使当填充物130A具有实芯时，平坦化也可以使填充物130A破裂和/或去除填充物130A，从而使得平坦化之后密封剂130的顶面不平坦。
如图7A示出的，在平坦化之后，在密封剂130上形成聚合物材料131。图7B示出了图7A中的区域604的详细的截面图。聚合物材料131可以包括PBO、聚酰亚胺、BCB等。在一些实施例中，聚合物材料131是光敏材料。形成聚合物材料131可以包括诸如旋涂工艺的涂覆工艺。可以涂覆聚合物材料131以填充密封剂130的顶面处的凹部和其它凹陷。聚合物材料131可以进一步覆盖管芯连接件126和通孔112的顶面。例如，参照图7B，聚合物材料131可以填充填充物130A的任何暴露的中空芯130B(见图6B)。可以将聚合物材料131分配至厚度T1以提供对密封剂130的不均匀形貌的充分覆盖。在一些实施例中，聚合物层的厚度T1与填充物130A的平均直径的比率可以至少为约0.5。在一些实施例中，聚合物层的厚度T1至少为10μm。在一些实施例中，用于形成聚合物材料131的涂覆工艺与密封剂130的不均匀形貌一起可能使得聚合物材料131的顶面非平面。例如，聚合物材料131的顶面的直接位于暴露的中空芯130B(见图6B)上方的部分可能不平坦。
在涂覆之后，可以将固化工艺(例如，退火)应用于聚合物材料131。在一个或多个集成电路管芯114A/114B是温度敏感(例如，存储器管芯)的实施例中，聚合物材料131可以包括低温聚合物，其在相对较低的温度(例如，小于约300℃)下固化，从而不损坏集成电路管芯114A/114B。在其它实施例中，可以在任何合适的温度下固化聚合物材料131。
在图8A和图8B中，将平坦化工艺应用于聚合物材料131以暴露管芯连接件126和通孔112。图8B示出了图8A中的区域604的详细的截面图。平坦化工艺进一步提供具有高平坦度的顶面，以用于在密封剂130和聚合物材料131上方形成额外的部件(例如，金属化图案)。在一些实施例中，平坦化工艺包括使用化学浆料的CMP，CMP以比密封剂130更高的速率选择性地去除聚合物材料131。例如，化学浆料可以包括氧化硅、氧化铝、它们的组合等。平坦化还可以是定时工艺，其中，平坦化工艺的终点通过定时来确定。
在平坦化之后，可以保留聚合物材料131的填充密封剂130的顶面中的凹部和其它凹陷的部分。此外，平坦化工艺可以去除聚合物材料131的其它部分，从而使得密封剂130的区(例如，图8B中的区130C)暴露。例如，在平坦化之后，聚合物材料131、密封剂130、集成电路管芯114A/114B和通孔112的最上表面可以基本共面。此外，在平坦化之后，聚合物材料131的厚度可以改变并且可以横跨密封剂130的顶面在0μm至约0.1μm的范围内。此外，平坦化工艺可能使得CMP残留物(例如，残留物133，也称为杂质133)保留在聚合物材料131和/或密封剂130的顶面上。CMP残留物(也称为杂质)是与聚合物材料131不同的材料，并且CMP残留物可以包括在CMP期间使用的化学浆料的材料。例如，当化学浆料包括氧化硅、氧化铝、它们的组合等时，CMP残留物同样可以包括硅、铝、氧的分子、它们的组合等。
在图9A至图19中，形成前侧再分布结构160。如将在图20中示出的，前侧再分布结构160包括介电层132、140、148和156以及金属化图案138、146和154(有时称为再分布层138、146和154或再分布线138、146和154)。
在图9A和图9B中，在密封剂130、聚合物材料131、通孔112和管芯连接件126上沉积介电层132。图9B示出了图9A中的区域604的详细的截面图。在一些实施例中，介电层132由聚合物形成，聚合物可以是可以使用光刻掩模图案化的诸如PBO、聚酰亚胺、BCB等的光敏材料。在其它实施例中，介电层132由氮化物，诸如氮化硅；氧化物，诸如氧化硅、PSG、BSG、BPSG；等形成。介电层132和聚合物材料131的材料组成可以相同或不同。可以通过旋涂、层压、CVD等或它们的组合形成介电层132。介电层132可以与聚合物材料131和/或密封剂130形成界面。此外，在一些实施例中，CMP残留物(例如，残留物133)可以设置在介电层132和聚合物材料131之间的界面处和/或介电层132和密封剂130之间的界面(未明确示出)处。通过包括聚合物材料131来填充密封剂130的顶面中的凹陷，在改进的平坦性的表面上形成介电材料132，这使得介电材料132的顶面也具有相对平坦的形貌。
在图10A和图10B中，之后，图案化介电层132。图案化形成暴露通孔112和管芯连接件126的部分的开口。图10B示出了图10A中的区域604的详细的截面图。可以通过可接受的工艺图案化，诸如当介电层132是光敏材料时通过将介电层132暴露于光或通过例如使用各向异性蚀刻的蚀刻。如果介电层132是光敏材料，则可以在曝光之后显影(例如，通过退火固化)介电层132。
在图11A和图11B中，在介电层132上形成具有通孔的金属化图案138。图11B示出了图11A中的区域604的详细的截面图。作为形成金属化图案138的实例，在介电层132上方和穿过介电层132的开口中形成晶种层(未示出)。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和位于钛层上方的铜层。可以使用例如PVD等形成晶种层。之后，在晶种层上形成并且图案化光刻胶。光刻胶可以通过旋涂等形成，并且可以暴露于光以用于图案化。光刻胶的图案对应于金属化图案138。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中和晶种层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括如铜、钛、钨、铝等的金属。之后，去除光刻胶和晶种层的其上未形成导电材料的部分。可以通过可接受的灰化或剥离工艺(诸如使用氧等离子体等)去除光刻胶。一旦去除光刻胶，则诸如通过使用可接受的蚀刻工艺(诸如湿或干蚀刻)去除晶种层的暴露部分。晶种层的剩余部分和导电材料形成金属化图案138和通孔。在穿过介电层132至例如通孔112和/或管芯连接件126的开口中形成通孔。在一些实施例中，金属化图案138是具有例如5μm或更小线宽的精细间距再分布线。在其它实施例中，金属化图案138可以具有其它尺寸。通过包括聚合物材料131来填充密封剂130的顶面中的凹陷，可以在介电层132的相对平坦的顶面上形成金属化图案138。因此，可以有利地减少金属化图案138中的制造缺陷(例如，断开的和/或合并的导线)。
在图12中，在金属化图案138和介电层132上沉积介电层140。在一些实施例中，介电层140由聚合物形成，聚合物可以是可以使用光刻掩模图案化的诸如PBO、聚酰亚胺、BCB等的光敏材料。在其它实施例中，介电层140由氮化物，诸如氮化硅；氧化物，诸如氧化硅、PSG、BSG、BPSG；等形成。可以通过旋涂、层压、CVD等或它们的组合形成介电层140。
在图13中，之后，图案化介电层140。图案化形成暴露金属化图案138的部分的开口。可以通过可接受的工艺图案化，诸如当介电层140是光敏材料时通过将介电层140暴露于光或通过例如使用各向异性蚀刻的蚀刻。如果介电层140是光敏材料，则可以在曝光之后显影介电层140。
在图14中，在介电层140上形成具有通孔的金属化图案146。作为形成金属化图案146的实例，在介电层140上方和穿过介电层140的开口中形成晶种层(未示出)。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和位于钛层上方的铜层。可以使用例如PVD等形成晶种层。之后，在晶种层上形成并且图案化光刻胶。光刻胶可以通过旋涂等形成，并且可以暴露于光以用于图案化。光刻胶的图案对应于金属化图案146。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中和晶种层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括如铜、钛、钨、铝等的金属。之后，去除光刻胶和晶种层的其上未形成导电材料的部分。可以通过可接受的灰化或剥离工艺(诸如使用氧等离子体等)去除光刻胶。一旦去除光刻胶，则诸如通过使用可接受的蚀刻工艺(诸如湿或干蚀刻)去除晶种层的暴露部分。晶种层的剩余部分和导电材料形成金属化图案146和通孔。在穿过介电层140至例如金属化图案138的部分的开口中形成通孔。
在图15中，在金属化图案146和介电层140上沉积介电层148。在一些实施例中，介电层148由聚合物形成，聚合物可以是可以使用光刻掩模图案化的诸如PBO、聚酰亚胺、BCB等的光敏材料。在其它实施例中，介电层148由氮化物，诸如氮化硅；氧化物，诸如氧化硅、PSG、BSG、BPSG；等形成。可以通过旋涂、层压、CVD等或它们的组合形成介电层148。
在图16中，之后，图案化介电层148。图案化形成暴露金属化图案146的部分的开口。可以通过可接受的工艺图案化，诸如当介电层148是光敏材料时通过将介电层148暴露于光或通过例如使用各向异性蚀刻的蚀刻。如果介电层148是光敏材料，则可以在曝光之后显影介电层148。
在图17中，在介电层148上形成具有通孔的金属化图案154。作为形成金属化图案154的实例，在介电层148上方和穿过介电层148的开口中形成晶种层(未示出)。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和位于钛层上方的铜层。可以使用例如PVD等形成晶种层。之后，在晶种层上形成并且图案化光刻胶。光刻胶可以通过旋涂等形成，并且可以暴露于光以用于图案化。光刻胶的图案对应于金属化图案154。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中和晶种层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括如铜、钛、钨、铝等的金属。之后，去除光刻胶和晶种层的其上未形成导电材料的部分。可以通过可接受的灰化或剥离工艺(诸如使用氧等离子体等)去除光刻胶。一旦去除光刻胶，则诸如通过使用可接受的蚀刻工艺(诸如湿或干蚀刻)去除晶种层的暴露部分。晶种层的剩余部分和导电材料形成金属化图案154和通孔。在穿过介电层148至例如金属化图案146的部分的开口中形成通孔。
在图18中，在金属化图案154和介电层148上沉积介电层156。在一些实施例中，介电层156由聚合物形成，聚合物可以是可以使用光刻掩模图案化的诸如PBO、聚酰亚胺、BCB等的光敏材料。在其它实施例中，介电层156由氮化物，诸如氮化硅；氧化物，诸如氧化硅、PSG、BSG、BPSG；等形成。可以通过旋涂、层压、CVD等或它们的组合形成介电层156。
在图19中，之后，图案化介电层156。图案化形成暴露金属化图案154的部分的开口。可以通过可接受的工艺图案化，诸如当介电层156是光敏材料时通过将介电层156暴露于光或通过例如使用各向异性蚀刻的蚀刻。如果介电层156是光敏材料，则可以在曝光之后显影介电层156。
前侧再分布结构160示出为实例。可以在前侧再分布结构160中形成更多或更少的介电层和金属化图案。如果要形成更少的介电层和金属化图案，则可以省略以上讨论的步骤和工艺。如果要形成更多的介电层和金属化图案，则可以重复以上讨论的步骤和工艺。本领域普通技术人员将容易理解，可以省略或重复哪些步骤和工艺。
在图20中，在前侧再分布结构160的外侧上形成焊盘162。焊盘162用于连接至导电连接件166(见图21)并且可以称为凸块下金属(UBM)162或导电柱162(见图25B)。在示出的实施例中，通过穿过介电层156至金属化图案154的开口形成焊盘162。作为形成焊盘162的实例，在介电层156上方形成晶种层(未示出)。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和位于钛层上方的铜层。可以使用例如PVD等形成晶种层。之后，在晶种层上形成并且图案化光刻胶。光刻胶可以通过旋涂等形成，并且可以暴露于光以用于图案化。光刻胶的图案对应于焊盘162。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中和晶种层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括如铜、钛、钨、铝等的金属。之后，去除光刻胶和晶种层的其上未形成导电材料的部分。可以通过可接受的灰化或剥离工艺(诸如使用氧等离子体等)去除光刻胶。一旦去除光刻胶，则诸如通过使用可接受的蚀刻工艺(诸如湿或干蚀刻)去除晶种层的暴露部分。晶种层的剩余部分和导电材料形成焊盘162。在实施例中，在不同地形成焊盘162的情况下，可以利用更多的光刻胶和图案化步骤。
在图21中，在UBM 162上形成导电连接件166。导电连接件166可以是BGA连接件、焊料球、焊料帽、金属柱、可控塌陷芯片连接(C4)凸块、微凸块、化学镀镍-化学镀钯浸金技术(ENEPIG)形成的凸块等。导电连接件166可以包括诸如焊料、铜、铝、金、镍、银、钯、锡等或它们的组合的导电材料。在一些实施例中，可以通过首先由诸如蒸发、电镀、印刷、焊料转移、球植等常用的方法形成焊料层来形成导电连接件166。一旦已经在结构上形成焊料层，则可以实施回流以将材料成形为期望的凸块形状。在另一实施例中，导电连接件166是通过溅射、印刷、电镀、化学镀、CVD等形成的金属柱(诸如铜柱)。金属柱可以是无焊料的并且具有基本垂直的侧壁。在一些实施例中，在金属柱连接件166的顶部上形成金属覆盖层(未示出)。金属覆盖层可以包括镍、锡、锡-铅、金、银、钯、铟、镍-钯-金、镍-金等或它们的组合，并且可以通过镀工艺形成。
在图22中，实施载体衬底脱粘以将载体衬底100从背侧再分布结构(例如，介电层104)脱离(脱粘)。根据一些实施例，脱粘包括将诸如激光或UV光的光投射到释放层102上，使得释放层102在光的热量下分解，并且可以去除载体衬底100。之后，翻转该结构并且放置在带190上。
如图22中进一步示出的，穿过介电层104形成暴露金属化图案106的部分的开口。可以例如使用激光钻孔、蚀刻等形成开口。
在图23中，通过沿着划线区域(例如，在相邻区域600和602之间)锯切来实施分割工艺。锯切将第一封装区域600与第二封装区域602分割。
图23示出了可以来自第一封装区域600或第二封装区域602的一个的产生的分割的封装件200。封装件200也可以称为集成扇出(InFO)封装件200。
图24示出了包括封装件200(可以称为第一封装件200)和可选第二封装件300的封装结构500。第二封装件300包括衬底302和连接至衬底302的一个或多个堆叠管芯308(308A和308B)。衬底302可以由诸如硅、锗、金刚石等的半导体材料制成。在一些实施例中，也可以使用诸如硅锗、碳化硅、砷化镓、砷化铟、磷化铟、碳化硅锗、磷砷化镓、磷化镓铟、这些的组合等的化合物材料。此外，衬底302可以是绝缘体上硅(SOI)衬底。通常，SOI衬底包括诸如外延硅、锗、硅锗、SOI、绝缘体上硅锗(SGOI)或它们的组合的半导体材料层。在一个可选实施例中，衬底302是基于诸如玻璃纤维增强树脂芯的绝缘芯。芯材料的一个实例是诸如FR4的玻璃纤维树脂。芯材料的可选物质包括双马来酰亚胺-三嗪(BT)树脂或者其它印刷电路板(PCB)材料或薄膜。对于衬底302，可以使用诸如味之素积聚膜(ABF)或其它层压材料的积聚膜。
衬底302可以包括有源和无源器件(未在图24中示出)。如本领域普通技术人员将意识到，诸如晶体管、电容器、电阻器、这些的组合等的多种器件可以用于生成用于第二封装件300的设计的结构和功能需求。可以使用任何合适的方法形成该器件。
衬底302也可以包括金属化层(未示出)和通孔306。金属化层可以形成在有源和无源器件上方并且被设计为连接各个器件以形成功能电路。金属化层可以由电介质(例如，低k介电材料)和导电材料(例如，铜)(其具有互连导电材料层的通孔)的交替层形成，并且可以通过任何合适的工艺(诸如沉积、镶嵌、双镶嵌等)形成。在一些实施例中，衬底302基本没有有源和无源器件。
衬底302可以具有位于衬底302的第一侧上以连接至堆叠管芯308的接合焊盘303，以及位于衬底302的第二侧上以连接至功能连接件314的接合焊盘304，衬底302的第二侧与第一侧相对。在一些实施例中，通过在衬底302的第一侧和第二侧上的介电层(未示出)中形成凹槽(未示出)来形成接合焊盘303和304。凹槽可以形成为允许接合焊盘303和304嵌入在介电层内。在其它实施例中，由于接合焊盘303和304可以形成在介电层上，因此省略了凹槽。在一些实施例中，接合焊盘303和304包括由铜、钛、镍、金、钯等或它们的组合制成的薄晶种层(未示出)。可以在薄晶种层上方沉积接合焊盘303和304的导电材料。可以通过电化学镀工艺、化学镀工艺、CVD、ALD、PVD等或它们的组合来形成导电材料。在实施例中，接合焊盘303和304的导电材料是铜、钨、铝、银、金等或它们的组合。
在实施例中，接合焊盘303和304是UBM，其包括三个导电材料层，诸如钛层、铜层和镍层。然而，本领域普通技术人员将意识到，存在适合于形成UBM 303和304的许多合适的材料和层的布置，诸如铬/铬-铜合金/铜/金的布置、钛/钛钨/铜的布置或铜/镍/金的布置。可以用于UBM 303和304的任何合适的材料或材料层均完全旨在包括在本申请的范围内。在一些实施例中，通孔306穿过衬底302延伸并且将至少一个接合焊盘303连接至至少一个接合焊盘304。
在示出的实施例中，通过引线接合310将堆叠管芯308连接至衬底302，但是也可以使用其它连接，诸如导电凸块。在实施例中，堆叠管芯308是堆叠的存储器管芯。例如，堆叠的存储器管芯308可以包括诸如LPDDR1、LPDDR2、LPDDR3、LPDDR4等存储器模块的低功率(LP)双数据率(DDR)存储器模块。
在一些实施例中，堆叠管芯308和引线接合310可以由模塑材料312密封。可以例如使用压缩模塑将模塑材料312模塑在堆叠管芯308和引线接合310上。在一些实施例中，模塑材料312是模塑料、聚合物、环氧树脂、氧化硅填充材料等或它们的组合。可以实施固化步骤以固化模塑材料312，其中，固化可以是热固化、UV固化等或它们的组合。
在一些实施例中，将堆叠管芯308和引线接合310掩埋在模塑材料312中，并且在模塑材料312的固化之后，实施诸如研磨的平坦化步骤以去除模塑材料312的过量部分并且为第二封装件300提供基本平坦的表面。
在形成第二封装件300之后，通过功能连接件314、接合焊盘304和金属化图案106将第二封装件300机械和电接合至第一封装件200。在一些实施例中，可以通过引线接合310、接合焊盘303和304、通孔306、功能连接件314和通孔112将堆叠管芯308连接至集成电路管芯114A/114B。
功能连接件314可以与以上描述的导电连接件166类似，并且此处不再重复描述，但是功能连接件314和导电连接件166不需要是相同的。功能连接件314可以设置在衬底302的与堆叠管芯308相对的侧上。在一些实施例中，阻焊剂也可以形成在衬底302的与堆叠管芯308相对的侧上。功能连接件314可以设置在阻焊剂中的开口中以电和机械连接至衬底302中的导电部件(例如，接合焊盘304)。阻焊剂可以用于保护衬底302的区免受外部损坏。
在一些实施例中，在接合功能连接件314之前，功能连接件314涂覆有焊剂(未示出)，诸如免洗焊剂。功能连接件314可以浸入焊剂中，或可以将焊剂喷射到功能连接件314上。在另一实施例中，可以将焊剂施加至金属化图案106的表面。
在一些实施例中，功能连接件314可以具有在其上形成的可选环氧树脂焊剂(未示出)，然后回流在将第二封装件300附接至第一封装件200之后剩余的环氧树脂焊剂的至少一些环氧树脂部分。该剩余的环氧树脂部分可以用作底部填充物以减小应力并且保护由功能连接件314的回流产生的接头。
第二封装件300和第一封装件200之间的接合可以是焊料接合。在实施例中，通过回流工艺将第二封装件300接合至第一封装件200。在该回流工艺期间，功能连接件314与接合焊盘304和金属化图案106接触，以将第二封装件300物理和电连接至第一封装件200。在接合工艺之后，金属间化合物(IMC，未示出)可以形成在金属化图案106和功能连接件314的界面处并且也形成在功能连接件314和接合焊盘304之间的界面(未示出)处。虽然图23和图24示出了在分割第一封装件200之后将第二封装件300接合至第一封装件200，但是在其它实施例中，可以在分割之前将第二封装件300接合至第一封装件200(例如，当第一封装件200是封装晶圆的一部分时，见图21)。在第二封装件300接合至第一封装件200之后，之后可以将第一封装件200与封装晶圆中的其它封装件分割。
第二封装件300是可选的。在其它实施例(例如，见图25B)中，具体地当省略背侧RDL 110和通孔112时，也可以省略第二封装件300。在这种实施例中，封装件的存储器组件可以由集成电路管芯114B提供，集成电路管芯114B与集成电路管芯114A(例如，处理器管芯)一起模塑在第一封装件200中。通过将存储器组件和处理器组件封装在单个封装层中，可以有利地减小最终封装件(例如，图25B的封装件550)的形状因子和制造成本。
图25A示出了在封装件200和300被安装至衬底400之后的半导体封装件500。衬底400可以是指封装衬底400。使用导电连接件166将封装件200安装至封装衬底400。
封装衬底400可以由诸如硅、锗、金刚石等的半导体材料制成。可选地，也可以使用诸如硅锗、碳化硅、砷化镓、砷化铟、磷化铟、碳化硅锗、磷砷化镓、磷化镓铟、这些的组合等的化合物材料。此外，封装衬底400可以是SOI衬底。通常，SOI衬底包括诸如外延硅、锗、硅锗、SOI、SGOI或它们的组合的半导体材料层。在一个可选实施例中，封装衬底400是基于诸如玻璃纤维增强树脂芯的绝缘芯。芯材料的一个实例是诸如FR4的玻璃纤维树脂。芯材料的可选物质包括双马来酰亚胺-三嗪BT树脂或者其PCB材料或薄膜。对于封装衬底400，可以使用诸如ABF或其它层压材料的积聚膜。
封装衬底400可以包括有源和无源器件(未示出)。如本领域普通技术人员将意识到，诸如晶体管、电容器、电阻器、这些的组合等的多种器件可以用于生成用于封装结构500的设计的结构和功能需求。可以使用任何合适的方法形成该器件。
封装衬底400也可以包括金属化层和通孔(未示出)以及位于金属化层和通孔上方的接合焊盘402。金属化层可以形成在有源和无源器件上方并且被设计为连接各个器件以形成功能电路。金属化层可以由电介质(例如，低k介电材料)和导电材料(例如，铜)(其具有互连导电材料层的通孔)的交替层形成，并且可以通过任何合适的工艺(诸如沉积、镶嵌、双镶嵌等)形成。在一些实施例中，封装衬底400基本没有有源和无源器件。
在一些实施例中，可以回流导电连接件166以将封装件200附接至接合焊盘402。导电连接件166将包括封装衬底400中的金属化层的封装衬底400电和/或物理连接至第一封装件200。在一些实施例中，在安装在封装衬底400上之前，可以将无源器件(例如，未示出的表面安装器件(SMD))附接至封装件200(例如，接合至接合焊盘402)。在这种实施例中，无源器件可以与导电连接件166接合至封装件200的同一表面。
导电连接件166可以具有在其上形成的可选环氧树脂焊剂(未示出)，然后回流在将封装件200附接至封装衬底400之后剩余的环氧树脂焊剂的至少一些环氧树脂部分。该剩余的环氧树脂部分可以用作底部填充物以减小应力并且保护由导电连接件166的回流产生的接头。在一些实施例中，底部填充物(未示出)可以形成在第一封装件200和封装衬底400之间并且围绕导电连接件166。底部填充物可以在附接封装件200之后通过毛细管流动工艺形成，或可以在附接封装件200之前通过合适的沉积方法形成。
也可以包括其它部件和工艺。例如，可以包括测试结构以辅助3D封装件或3DIC器件的验证测试。测试结构可以包括例如形成在再分布层中或衬底上的测试焊盘以允许使用探针和/或探针卡等测试3D封装件或3DIC。验证测试可以对中间结构以及最终结构实施。此外，本文公开的结构和方法可以与结合已知良好管芯的中间验证的测试方法结合使用以增加良率和降低成本。
图25B示出了根据一些实施例的封装件550。封装件550包括通过连接件162A和166A接合至封装件400的第一封装件250。连接件162A和166A可以是BGA球、C4凸块等。在一些实施例中，连接件162A和166A包括设置在导电柱162A上的焊料帽166A。封装件550可以与封装件500(见图25A)基本类似，其中，相同的参考标号指示相同的元件。然而，在封装件250中，省略可选背侧RDL 110和通孔112。此外，没有存储器模块(例如，与图25B中示出的封装件300类似)接合至第一封装件250的与封装件400相对的侧。在一些实施例中，封装件550的存储器组件由如上所述的集成电路管芯114B提供。虽然称为“管芯”，但是集成电路管芯114A和/或114B可以是裸芯片或封装芯片(例如，包括一个或多个管芯和/或再分布部件)。
图26A至图27示出了根据可选实施例的制造封装件502(见图27)的各个阶段的截面图。参照图26A和图26B，示出了形成封装件502(见图27)的中间工艺步骤。图26B示出了图26A的区604的详细的截面图。封装件502可以与封装件500(见图25A)基本类似，其中，相同的参考标号指示使用相同的工艺步骤(例如，如以上参照图1至图11B描述的)形成的相同的元件。与上述实施例类似，背侧再分布结构110和/或通孔112是可选的并且可以省略。然而，在封装件502中，省略介电层132(见图11A和图11B)，并且金属化图案138直接形成在密封剂130和聚合物材料131上以电互连集成电路管芯114A的管芯连接件126、集成电路管芯114B的管芯连接件126和通孔112。例如，金属化图案138与密封剂130和聚合物材料131形成界面。此外，来自平坦化聚合物材料131的CMP残留物(示出为残留物133)可以设置在金属化图案138和聚合物材料131之间的界面处和/或金属化图案138和密封剂130之间的界面处。如上所述，CMP残留物(也称为杂质)可以包括在聚合物材料131的CMP期间使用的化学浆料的材料。例如，当化学浆料包括氧化硅、氧化铝、它们的组合等时，CMP残留物同样可以包括硅、铝、氧的分子、它们的组合等。图27示出了进一步处理(例如，通过应用与以上参照图12至图25A讨论的那些相同的工艺步骤)之后的完成的封装件502。在其它实施例(例如，与图25B类似)中，具体是当省略可选背侧再分布结构110和通孔112时，可以省略封装件300。
图28A至图34B示出根据可选实施例的制造封装件504(见图34A)和/或封装件506(见图34B)的各个阶段的截面图。参照图28A和图28B，示出了形成封装件504和506(见图34A和图34B)的中间工艺步骤。图28B示出了图28A的区604的详细的截面图。图28A和图28B的部件可以与以上参照图6A和图6B示出和描述的部件基本类似，其中，相同的参考标号指示使用相同的工艺步骤形成的相同的元件。与上述实施例类似，背侧再分布结构110和/或通孔112是可选的并且可以省略。
下一步，在图29A和图29B中，图案化导电通孔112和管芯连接件126。图29B示出了图29A的区604的详细的截面图。图案化导电通孔112和管芯连接件126可以包括回蚀刻工艺、去污工艺、它们的组合等，以使导电通孔112和管芯连接件126凹进至密封剂130和介电材料128的顶面之下。在一些实施例中，图案化导电通孔112和管芯连接件126去除了在导电通孔112和管芯连接件126的顶面处形成的原生氧化物(例如，氧化铜)。已经观察到，通过去除这种原生氧化物，可以改进导电通孔112和管芯连接件126的电导率。在一些实施例中，图案化导电通孔112和管芯连接件126，每个导电通孔112和管芯连接件126的相应高度减小厚度T2(见图29B)，厚度T2可以在约0.1μm至约20μm的范围内。
下一步，如图30A示出的，在密封剂130上形成聚合物材料131。图30B示出了图30A中的区域604的详细的截面图。聚合物材料131可以包含PBO、聚酰亚胺、BCB等。在一些实施例中，聚合物材料131是光敏材料。形成聚合物材料131可以包括诸如旋涂工艺的涂覆工艺。可以涂覆聚合物材料131以填充密封剂130的顶面处的凹部和其它凹陷。聚合物材料131可以进一步填充由导电通孔112和管芯连接件126的图案化限定的开口(见图29A/图29B)。例如，聚合物材料131可以进一步覆盖管芯连接件126和通孔112的顶面。
参照图30B，聚合物材料131可以填充填充物130A的任何暴露的中空芯130B(见图28B)。可以将聚合物材料131分配至厚度T1以提供对密封剂130的不均匀形貌的充分覆盖。在一些实施例中，聚合物层的厚度T1与填充物130A的平均直径的比率可以至少为约0.5。在一些实施例中，聚合物层的厚度T1至少为10μm。在一些实施例中，用于形成聚合物材料131的涂覆工艺与密封剂130的不均匀形貌一起可能使得聚合物材料131的顶面非平面。例如，聚合物材料131的顶面的直接位于暴露的中空芯130B(见图28B)上方的部分可能不平坦。
下一步，在图31A和图31B中，在聚合物材料131中图案化开口170以暴露通孔112和管芯连接件126。图31B示出了图31A中的区域604的详细的截面图。可以通过可接受的工艺图案化，诸如当聚合物材料131是光敏材料时通过将聚合物材料131暴露于光或通过例如使用各向异性蚀刻的蚀刻。
在图案化之后，可以将固化工艺(例如，退火)应用于聚合物材料131。在一个或多个集成电路管芯114A/114B是温度敏感(例如，存储器管芯)的实施例中，聚合物材料131可以包括低温聚合物，其在相对较低的温度(例如，小于约300℃)下固化，从而不损坏集成电路管芯114A/114B。在其它实施例中，可以在任何合适的温度下固化聚合物材料131。固化工艺可以使聚合物材料硬化以为随后的工艺步骤(例如，平坦化，见图32A、图32B和图32C)提供足够的硬度。虽然固化工艺描述为在图案化聚合物材料131之后实施，但是在其它实施例中，可以在图案化聚合物材料131之前实施固化聚合物材料131(例如，当使用蚀刻工艺来图案化聚合物材料131时)。
在图32A、图32B和图32C中，将平坦化工艺应用于聚合物材料131。图32B和32C示出了图32A中的区域604的详细的截面图。图32B对应于根据一些实施例的产生封装件504(见图34A)的平坦化工艺。图32C对应于根据一些可选实施例的产生封装件506(见图34B)的平坦化工艺。
平坦化工艺提供具有高平坦度的顶面，以用于在密封剂130和聚合物材料131上方形成额外的部件(例如，金属化图案)。在一些实施例中，平坦化工艺包括使用化学浆料的CMP，CMP以比密封剂130更高的速率选择性地去除聚合物材料131。例如，化学浆料可以包括氧化硅、氧化铝，它们的组合等。平坦化还可以是定时工艺，其中，平坦化工艺的终点通过定时来确定。
在平坦化之后，可以保留聚合物材料131的填充密封剂130的顶面中的凹部和其它凹陷的部分。在一些实施例(见图32B)中，平坦化工艺可以去除聚合物材料131的其它部分，从而使得密封剂130的区(例如，图32B中的区130C)暴露。例如，在平坦化之后，聚合物材料131、密封剂130和介电材料128的最上表面可以基本共面。在这种实施例中，在平坦化之后，聚合物材料131的厚度可以改变并且可以横跨密封剂130和介电材料128的顶面在0μm至约0.1μm的范围内。
在其它实施例(例如，见图32C)，平坦化工艺平坦化聚合物材料131而没有暴露密封剂130或介电材料128的任何部分。例如，在平坦化之后，聚合物材料131完全地覆盖密封剂130和介电材料128的顶面。在这种实施例中，在平坦化之后，聚合物材料131的厚度可以改变并且可以横跨密封剂130和介电材料128的顶面在0.1μm至约30μm的范围内。
此外，平坦化工艺可能使得CMP残留物(例如，残留物133，也称为杂质133)保留在聚合物材料131和/或密封剂130的顶面上。CMP残留物(也称为杂质)是与聚合物材料131不同的材料，并且CMP残留物可以包括在CMP期间使用的化学浆料的材料。例如，当化学浆料包括氧化硅、氧化铝、它们的组合等时，CMP残留物同样可以包括硅、铝、氧的分子、它们的组合等。此外，在聚合物材料131的材料组成中未发现CMP残留物的材料。
下一步，在图33A、图33B和图33C中，金属化图案138直接形成在聚合物材料131上以电互连集成电路管芯114A的管芯连接件126、集成电路管芯114B的管芯连接件126和通孔112。图33B和图33C示出了图33A中的区域604的详细的截面图。图33B对应于根据一些实施例形成产生封装件504(见图34A)的金属化图案。图33C对应于根据一些可选实施例形成产生封装件506(见图34B)的金属化图案。
在一些实施例(见图33B)中，金属化图案138与密封剂130、介电材料128和聚合物材料131形成界面。在这种实施例中，来自平坦化聚合物材料131的CMP残留物(示出为残留物133)可以设置在金属化图案138和聚合物材料131之间的界面处和/或金属化图案138和密封剂130之间的界面处。如上所述，CMP残留物可以包括在聚合物材料131的CMP期间使用的化学浆料的材料。例如，当化学浆料包括氧化硅、氧化铝、它们的组合等时，CMP残留物同样可以包括硅、铝、氧的分子、它们的组合等。图34A示出了进一步处理(例如，通过应用与以上参照图12至图25A讨论的那些相同的工艺步骤)之后的完成的封装件504。在其它实施例(例如，与图25B类似)中，具体是当省略可选背侧再分布结构110和通孔112时，可以省略封装件300。
在一些实施例(见图33C)中，金属化图案138与聚合物材料131形成界面，而没有与密封剂130或介电材料128形成界面。在这种实施例中，来自平坦化聚合物材料131的CMP残留物(示出为残留物133)可以设置在金属化图案138和聚合物材料131之间的界面处。如上所述，CMP残留物可以包括在聚合物材料131的CMP期间使用的化学浆料的材料。例如，当化学浆料包括氧化硅、氧化铝、它们的组合等时，CMP残留物同样可以包括硅、铝、氧的分子、它们的组合等。图34B示出了进一步处理(例如，通过应用与以上参照图12至图25A讨论的那些相同的工艺步骤)之后的完成的封装件506。在其它实施例(例如，与图25B类似)中，具体是当省略可选背侧再分布结构110和通孔112时，可以省略封装件300。
以上讨论的各个实施例提供了填充在器件封装件中的密封剂的不平坦顶面中并且平坦化器件封装件中的密封剂的不平坦顶面的额外的聚合物材料。聚合物材料基本不含填充物，从而与包含填充物的密封剂相比，可以使聚合物材料平坦化为具有改进的形貌。已经观察到，通过提供这种聚合物材料，可以减少随后形成的部件(例如，金属化图案的导线)中的制造缺陷。
根据实施例，方法包括：将半导体管芯密封在密封剂中；平坦化密封剂；在密封剂上沉积聚合物材料；平坦化聚合物材料；以及在聚合物材料上形成金属化图案。金属化图案将半导体管芯的管芯连接件电连接至设置在半导体管芯的外部的导电部件。在实施例中，密封剂包括填充物，并且平坦化密封剂暴露填充物的中空芯，并且其中，沉积聚合物材料包括用聚合物材料填充中空芯。在实施例中，该方法还包括在聚合物材料和金属化图案之间形成聚合物层。在实施例中，形成金属化图案包括形成与聚合物材料物理接触的金属化图案。在实施例中，该方法还包括穿过聚合物材料图案化第一开口以暴露半导体管芯的管芯连接件并且穿过聚合物材料图案化第二开口以暴露导电部件。形成金属化图案包括在第一开口和第二开口中形成金属化图案的部分。在实施例中，在平坦化聚合物材料之前实施图案化第一开口和图案化第二开口。在实施例中，在沉积聚合物材料之前，该方法还包括使半导体管芯的管芯连接件凹进至密封剂的顶面之下。在实施例中，平坦化聚合物材料暴露部分密封剂。
根据实施例，方法包括：将第一集成电路管芯设置为与第二集成电路管芯相邻；将第一集成电路管芯和第二集成电路管芯密封在模塑料中，模塑料包括多种填充物；以及平坦化模塑料以暴露第一集成电路管芯的第一管芯连接件和第二集成电路管芯的第二管芯连接件。平坦化模塑料限定了模塑料的顶面处的多个凹陷。该方法还包括在模塑料上方沉积聚合物材料，聚合物材料设置在模塑料的顶面处的多个凹陷中；平坦化聚合物材料；并且在聚合物材料上方形成金属化图案。金属化图案将第一管芯连接件电连接至第二管芯连接件。在实施例中，该方法还包括在聚合物材料上方沉积聚合物层并且形成金属化图案包括在聚合物层上方形成金属化图案。在实施例中，形成金属化图案包括形成与聚合物材料接触的金属化图案。在实施例中，该方法还包括将第一管芯连接件和第二管芯连接件图案化至模塑料的顶面之下。在实施例中，在平坦化聚合物材料之后，聚合物材料、模塑料、第一管芯连接件和第二管芯连接件的顶面共面。
根据实施例，封装件包括集成电路管芯，该集成电路管芯包括管芯连接件；设置在集成电路管芯周围的密封剂；位于密封剂的至少部分上方的聚合物材料；设置在聚合物材料的顶面处的杂质，杂质的材料与聚合物材料不同；以及位于聚合物材料上方的导线。导线将管芯连接件电连接至导电部件，并且密封剂的部分设置在管芯连接件和导电部件之间。在实施例中，聚合物层设置在导线和聚合物材料之间，并且杂质设置在聚合物材料和聚合物层之间的界面处。在实施例中，聚合物层还与密封剂形成界面。在实施例中，聚合物层覆盖密封剂的整个顶面。在实施例中，杂质设置在导线和聚合物材料之间的界面处。在实施例中，管芯连接件的顶面设置在密封剂的顶面之下，并且聚合物材料从密封剂的顶面延伸至管芯连接件的顶面。在实施例中，杂质包括硅、铝或它们的组合。
上面概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解，它们可以容易地使用本发明作为基础来设计或修改用于实施与本人所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。

Claims (20)

1.一种形成封装件的方法，包括：
将半导体管芯密封在密封剂中，其中，所述密封剂包括填充物；
平坦化所述密封剂，其中，平坦化所述密封剂暴露所述填充物的中空芯；
在所述密封剂上沉积聚合物材料，其中，沉积所述聚合物材料包括用所述聚合物材料填充所述中空芯；
平坦化所述聚合物材料；以及
在所述聚合物材料上形成金属化图案，其中，所述金属化图案将所述半导体管芯的管芯连接件电连接至设置在所述半导体管芯的外部的导电部件。
2.根据权利要求1所述的方法，其中，在平坦化所述聚合物材料之后，所述聚合物材料、所述密封剂和所述半导体管芯的管芯连接件的顶面共面。
3.根据权利要求1所述的方法，还包括在所述聚合物材料和所述金属化图案之间形成聚合物层。
4.根据权利要求1所述的方法，其中，形成所述金属化图案包括形成与所述聚合物材料物理接触的金属化图案。
5.根据权利要求4所述的方法，还包括：
穿过所述聚合物材料图案化第一开口以暴露所述半导体管芯的管芯连接件；以及
穿过所述聚合物材料图案化第二开口以暴露所述导电部件，其中，形成所述金属化图案包括在所述第一开口和所述第二开口中形成所述金属化图案的部分。
6.根据权利要求5所述的方法，其中，在平坦化所述聚合物材料之前实施图案化所述第一开口和图案化所述第二开口。
7.根据权利要求1所述的方法，还包括：在沉积所述聚合物材料之前，使所述半导体管芯的管芯连接件凹进至所述密封剂的顶面之下。
8.根据权利要求1所述的方法，其中，平坦化所述聚合物材料暴露所述密封剂的部分。
9.一种形成封装件的方法，包括：
将第一集成电路管芯设置为与第二集成电路管芯相邻；
将所述第一集成电路管芯和所述第二集成电路管芯密封在模塑料中，所述模塑料包括多种填充物；
平坦化所述模塑料以暴露所述第一集成电路管芯的第一管芯连接件和所述第二集成电路管芯的第二管芯连接件，平坦化所述模塑料限定了所述模塑料的顶面处的多个凹陷；
在所述模塑料上方沉积聚合物材料，所述聚合物材料设置在所述模塑料的顶面处的所述多个凹陷中；
平坦化所述聚合物材料；以及
在所述聚合物材料上方形成金属化图案，所述金属化图案将所述第一管芯连接件电连接至所述第二管芯连接件。
10.根据权利要求9所述的方法，还包括在所述聚合物材料上方沉积聚合物层，其中，形成所述金属化图案包括在所述聚合物层上方形成所述金属化图案。
11.根据权利要求9所述的方法，其中，形成所述金属化图案包括形成与所述聚合物材料接触的金属化图案。
12.根据权利要求9所述的方法，还包括将所述第一管芯连接件和所述第二管芯连接件图案化至所述模塑料的顶面之下。
13.根据权利要求9所述的方法，其中，在平坦化所述聚合物材料之后，所述聚合物材料、所述模塑料、所述第一管芯连接件和所述第二管芯连接件的顶面共面。
14.一种封装件，包括：
集成电路管芯，包括管芯连接件；
密封剂，设置在所述集成电路管芯周围；
聚合物材料，位于所述密封剂的至少部分上方；
杂质，设置在所述聚合物材料的顶面处，所述杂质的材料与所述聚合物材料不同；以及
导线，位于所述聚合物材料上方，所述导线将所述管芯连接件电连接至导电部件，并且所述密封剂的部分设置在所述管芯连接件和所述导电部件之间；
聚合物层，设置在所述导线和所述聚合物材料之间，并且所述杂质设置在所述聚合物材料和所述聚合物层之间的界面处。
15.根据权利要求14所述的封装件，其中，所述聚合物材料、所述密封剂和所述管芯连接件的顶面共面。
16.根据权利要求15所述的封装件，其中，所述聚合物层还与所述密封剂形成界面。
17.根据权利要求15所述的封装件，其中，所述聚合物层覆盖所述密封剂的整个顶面。
18.根据权利要求14所述的封装件，其中，所述杂质设置在所述导线和所述聚合物材料之间的界面处。
19.根据权利要求14所述的封装件，其中，所述管芯连接件的顶面设置在所述密封剂的顶面之下，并且所述聚合物材料从所述密封剂的顶面延伸至所述管芯连接件的顶面。
20.根据权利要求14所述的封装件，其中，所述杂质包括硅、铝或它们的组合。
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