CN109216296B - 半导体封装件和方法 - Google Patents

半导体封装件和方法 Download PDF

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Publication number
CN109216296B
CN109216296B CN201810722317.4A CN201810722317A CN109216296B CN 109216296 B CN109216296 B CN 109216296B CN 201810722317 A CN201810722317 A CN 201810722317A CN 109216296 B CN109216296 B CN 109216296B
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dielectric layer
conductive via
opening
conductive
plane
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CN109216296A (zh
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王博汉
郭宏瑞
胡毓祥
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

在实施例中，器件包括：模塑料；密封在模塑料中的集成电路管芯；邻近集成电路管芯的通孔；以及位于集成电路管芯、模塑料和通孔上方的再分布结构，再分布结构电连接至集成电路管芯和通孔，再分布结构包括：设置在模塑料上方的第一介电层；穿过第一介电层延伸的第一导电通孔；设置在第一介电层和第一导电通孔上方的第二介电层；以及穿过第二介电层延伸并且延伸至第一导电通孔的部分内的第二导电通孔，第一导电通孔和第二导电通孔之间的界面是非平面的。本发明的实施例还涉及半导体封装件和方法。

Description

半导体封装件和方法
技术领域
本发明的实施例涉及半导体封装件和方法。
背景技术
由于各个电组件(例如，晶体管、二极管、电阻器、电容器等)的集成密度的持续改进，半导体工业已经经历快速了增长。对于大部分而言，这种集成密度的改进来自于最小部件尺寸的连续减小，这使得更多的组件集成到给定的区域。随着近来对更小的电子器件的需求的增长，对半导体管芯的更小且更具创造性的封装技术的需求也已经出现。这种封装系统的一个实例是叠层封装(POP)技术。在PoP器件中，顶部半导体封装件堆叠在底部半导体封装件的顶部上以提供高集成度和组件密度。PoP技术通常能够在印刷电路板(PCB)上生产具有增强的功能和较小的覆盖区的半导体器件。
发明内容
本发明的实施例提供了一种半导体器件，包括：模塑料；集成电路管芯，密封在所述模塑料中；通孔，邻近所述集成电路管芯；以及再分布结构，位于所述集成电路管芯、所述模塑料和所述通孔上方，所述再分布结构电连接至所述集成电路管芯和所述通孔，所述再分布结构包括：第一介电层，设置在所述模塑料上方；第一导电通孔，穿过所述第一介电层延伸；第二介电层，设置在所述第一介电层和所述第一导电通孔上方；和第二导电通孔，穿过所述第二介电层延伸并且延伸至所述第一导电通孔的部分内，所述第一导电通孔和所述第二导电通孔之间的界面是非平面的。
本发明的另一实施例提供了一种形成半导体封装件的方法，包括：将集成电路管芯密封在模塑料中，所述集成电路管芯具有管芯连接件；在所述模塑料上方沉积第一介电层；穿过所述第一介电层图案化第一开口，所述第一开口暴露所述集成电路管芯的所述管芯连接件；在所述第一介电层上方和所述第一开口中沉积第一晶种层；在所述第一晶种层上镀第一导电通孔，所述第一导电通孔穿过所述第一介电层延伸，所述第一导电通孔在穿过所述第一介电层延伸的所述第一导电通孔的部分中具有第一凹槽；在所述第一介电层和所述第一导电通孔上方沉积第二介电层；在所述第二介电层中图案化第二开口，所述第二开口暴露所述第一导电通孔的所述第一凹槽；在所述第二介电层上方、所述第二开口中和所述第一凹槽中沉积第二晶种层；以及在所述第二晶种层上镀第二导电通孔，所述第二导电通孔延伸至所述第一导电通孔的所述第一凹槽内并且穿过所述第二介电层延伸，所述第二导电通孔在穿过所述第二介电层延伸的所述第二导电通孔的部分中具有第二凹槽。
本发明的又一实施例提供了一种形成半导体封装件的方法，包括：将集成电路管芯密封在模塑料中，所述集成电路管芯具有管芯连接件；在所述模塑料上方沉积第一介电层；穿过所述第一介电层图案化第一开口；在所述集成电路管芯的所述管芯连接件上的所述第一开口中形成第一导电柱；在所述第一介电层上方沉积第二介电层；在所述第二介电层中图案化第二开口，所述第二开口暴露所述第一开口；以及在所述第一开口和所述第二开口中的所述第一导电柱周围形成第一导电通孔。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该指出，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1至图23示出了根据一些实施例的用于形成封装件的工艺期间的中间步骤的截面图。
图24至图26示出了根据一些实施例的用于形成封装结构的工艺期间的中间步骤的截面图。
图27至图42示出了根据一些其它实施例的堆叠通孔结构的形成。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其它方式定向(旋转90度或在其它方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。
本文讨论的实施例可以在特定上下文中讨论，即在再分布结构中具有堆叠通孔结构的封装结构(例如，叠层封装(PoP)结构)及其形成方法。本文使用堆叠通孔结构来描述互连不同金属化图案的多个(“堆叠”)导电通孔，其中，多个导电通孔的每个都垂直对准(例如，垂直于再分布结构的主表面的线穿过多个导电通孔的每个延伸)。各个实施例可以提供形成堆叠导电通孔的方法，该方法具有减少的缺陷，诸如减小热循环测试期间通孔至通孔界面处的应力、减少通孔内部和/或邻近的堆叠通孔之间的层间金属氧化物(例如，氧化铜)处的空隙形成等。例如，各个实施例可以提供晶种层作为邻近的堆叠通孔之间的扩散阻挡层(例如，铜扩散)。在一些实施例中，晶种层可以是包括例如钛层和铜层的多层结构。此外，堆叠通孔之间的界面可以是非平面的(例如，交错的)以增强堆叠通孔结构的整体强度。各个实施例可以提供这些实施例而不显着增加制造成本。
本发明的教导适用于包括堆叠导电通孔的任何封装结构。其它实施例考虑其它应用，诸如本领域普通技术人员在阅读本发明之后将显而易见的不同封装件类型或不同配置。应该注意，本文讨论的实施例可以不必示出可以存在于结构中的每个组件或部件。例如，诸如当一个组件的讨论可能足以表达实施例的各个方面时，可以从图中省略多个组件。此外，本文讨论的方法实施例可以讨论为以特定顺序实施；然而，可以以任何逻辑顺序来实施其它方法实施例。
图1至图23示出了根据一些实施例的用于形成第一封装件200的工艺期间的中间步骤的截面图。第一封装件200也可以称为集成扇出(InFO)封装件。图1至图23是示出用于形成第一封装件200的第一封装区域600的截面图。应该理解，可以同时在多个封装区域中形成多个封装件。
在图1中，提供载体衬底100，并且在载体衬底100上形成释放层102。载体衬底100可以是玻璃载体衬底、陶瓷载体衬底等。载体衬底100可以是晶圆，从而使得可以同时在载体衬底100上形成多个封装件。释放层102可以由基于聚合物的材料形成，其可以与载体衬底100一起从在随后的步骤中形成的上面的结构去除。在一些实施例中，释放层102是诸如光热转换(LTHC)释放涂层的基于环氧树脂的热释放材料，该材料在加热时失去其粘合性。在其它实施例中，释放层102可以是紫外(UV)胶，当暴露于UV光时失去其粘合性。释放层102可以以液体形式分配并且被固化，可以是层压在载体衬底100上的层压膜，或可以是类似的。释放层102的顶面可以是齐平的并且可以具有高度的共面性。
在图2中，形成介电层104和金属化图案106(有时称为再分布层或再分布线)。介电层104形成在释放层102上。介电层104的底面可以与释放层102的顶面接触。在一些实施例中，介电层104由诸如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等的聚合物形成。在其它实施例中，介电层104由氮化物，诸如氮化硅；氧化物，诸如氧化硅、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)等；等形成。可以通过诸如旋涂、化学汽相沉积(CVD)、层压等或它们的组合的任何可接受的沉积工艺形成介电层104。
在介电层104上形成金属化图案106。作为形成金属化图案106的实例，在介电层104上方形成晶种层(未示出)。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和位于钛层上方的铜层。可以使用例如PVD等形成晶种层。之后，在晶种层上形成并且图案化光刻胶。光刻胶可以通过旋涂等形成，并且可以暴露于光以用于图案化。光刻胶的图案对应于金属化图案106。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中和晶种层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括如铜、钛、钨、铝等的金属。之后，去除光刻胶和晶种层的其上未形成导电材料的部分。可以通过可接受的灰化或剥离工艺(诸如使用氧等离子体等)去除光刻胶。一旦去除光刻胶，则诸如通过使用可接受的蚀刻工艺(诸如湿或干蚀刻)去除晶种层的暴露部分。晶种层的剩余部分和导电材料形成金属化图案106。
在图3中，在金属化图案106和介电层104上形成介电层108。在一些实施例中，介电层108由聚合物形成，聚合物可以是可以使用光刻掩模图案化的诸如PBO、聚酰亚胺、BCB等的光敏材料。在其它实施例中，介电层108由氮化物，诸如氮化硅；氧化物，诸如氧化硅、PSG、BSG、BPSG；等形成。可以通过旋涂、层压、CVD等或它们的组合形成介电层108。之后，图案化介电层108以形成暴露金属化图案106的部分的开口。可以通过可接受的工艺进行图案化，诸如当介电层是光敏材料时通过将介电层108暴露于光或通过例如使用各向异性蚀刻的蚀刻。
介电层104和108以及金属化图案106可以称为背侧再分布结构110。在所示的实施例中，背侧再分布结构110包括两个介电层104和108以及一个金属化图案106。在其它实施例中，背侧再分布结构110可以包括任何数量的介电层、金属化图案和导电通孔。通过重复用于形成金属化图案106和介电层108的工艺，可以在背侧再分布结构110中形成一个或多个额外的金属化图案和介电层。可以在通过在下面的介电层的开口中形成金属化图案的晶种层和导电材料的金属化图案的形成期间形成通孔(未示出)。因此，通孔可以互连并且电连接各个金属化图案。
之后，形成通孔112。作为形成通孔112的实例，在背侧再分布结构110上方(例如，在如图所示的介电层108和金属化图案106的暴露部分上方)形成晶种层。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和位于钛层上方的铜层。可以使用例如PVD等形成晶种层。在晶种层上形成并且图案化光刻胶。光刻胶可以通过旋涂等形成，并且可以暴露于光以用于图案化。光刻胶的图案对应于通孔。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中和晶种层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括如铜、钛、钨、铝等的金属。去除光刻胶和晶种层的其上未形成导电材料的部分。可以通过可接受的灰化或剥离工艺(诸如使用氧等离子体等)去除光刻胶。一旦去除光刻胶，则诸如通过使用可接受的蚀刻工艺(诸如湿或干蚀刻)去除晶种层的暴露部分。晶种层的剩余部分和导电材料形成通孔112。
在图4中，通过粘合剂116将集成电路管芯114粘合至介电层108。在所示的实施例中，在第一封装区域600中粘合一个集成电路管芯114；在其它实施例中，可以在每个区域中粘合更多或更少的集成电路管芯114。例如，在实施例中，可以第一封装区域600中粘合多个集成电路管芯114。集成电路管芯114可以是逻辑管芯(例如，中央处理单元、微控制器等)、存储器管芯(例如，动态随机存取存储器(DRAM)管芯、静态随机存取存储器(SRAM)管芯等)、电源管理管芯(例如，电源管理集成电路(PMIC)管芯)、射频(RF)管芯、传感器管芯、微电子机械系统(MEMS)管芯、信号处理管芯(例如，数字信号处理(DSP)管芯)、前端管芯(例如，模拟前端(AFE)管芯)等或它们的组合。而且，在一些实施例中，集成电路管芯114可以具有不同的尺寸(例如，不同的高度和/或表面积)，并且在其它实施例中，集成电路管芯114可以具有相同的尺寸(例如，相同的高度和/或表面积)。
在粘合至介电层108之前，可以根据可应用的制造工艺处理集成电路管芯114以在集成电路管芯114中形成集成电路。例如，集成电路管芯114每个均包括半导体衬底118，诸如掺杂或未掺杂的硅或绝缘体上半导体(SOI)衬底的有源层。半导体衬底可以包括其它半导体材料，诸如锗；化合物半导体，包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟；合金半导体，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP；或它们的组合。也可以使用诸如多层衬底或梯度衬底的其它衬底。诸如晶体管、二极管、电容器、电阻器等的器件可以形成在半导体衬底118中和/或上，并且可以通过由例如半导体衬底118上的一个或多个介电层中的金属化图案形成的互连结构120互连以形成集成电路。
集成电路管芯114还包括制成外部连接的焊盘122，诸如铝焊盘。焊盘122位于可以称为集成电路管芯114的相应的有源侧的位置上。钝化膜124位于集成电路管芯114上并且位于焊盘122的部分上。开口形成为穿过钝化膜124至焊盘122。诸如导电柱(例如，包括诸如铜的金属)的管芯连接件126位于穿过钝化膜124的开口中并且机械和电连接至相应的焊盘122。可以通过例如镀等形成管芯连接件126。管芯连接件126电连接集成电路管芯114的相应的集成电路。可以在管芯测试期间在管芯连接件126上形成焊料帽(未示出)。
介电材料128位于集成电路管芯114的有源侧上，诸如位于钝化膜124和管芯连接件126上。介电材料128横向密封管芯连接件126，并且介电材料128与相应的集成电路管芯114横向共末端。介电材料128可以是聚合物，诸如PBO、聚酰亚胺、BCB等；氮化物，诸如氮化硅等；氧化物，诸如氧化硅、PSG、BSG、BPSG等；等或它们的组合，并且可以例如通过旋涂、层压、CVD等形成。
粘合剂116位于集成电路管芯114的背侧上并且将集成电路管芯114粘合至背侧再分布结构110，诸如示出的介电层108。粘合剂116可以是任何合适的粘合剂、环氧树脂、管芯附着膜(DAF)等。粘合剂116可以施加至集成电路管芯114的背侧(诸如相应的半导体晶圆的背侧)或可以施加在载体衬底100的表面上方。集成电路管芯114可以诸如通过锯切或切割被分割并且使用例如拾取和放置工具通过粘合剂116粘合至介电层108。
在图5中，在各种组件上形成密封剂130。密封剂130可以是模塑料、环氧树脂等，并且可以通过压缩模塑、转移模塑等施加。在固化之后，密封剂130可以经历研磨工艺以暴露通孔112和管芯连接件126。在研磨工艺之后，通孔112、管芯连接件126和密封剂130的顶面共面。在一些实施例中，例如，如果已经暴露通孔112和管芯连接件126，则可以省略研磨。
在图6A至图21B中，形成前侧再分布结构131。如将要示出的，前侧再分布结构131包括介电层133、146、160和174以及金属化图案142、156和170(有时称为再分布层或再分布线)。在图6A至图21B中，以“A”符号结尾的图是示出第一封装区域600的截面图，并且以“B”符号结尾的图是示出集成电路管芯114上方的前侧再分布结构131的区域650的更多细节的截面图。在前侧再分布结构131的区域650中，形成堆叠通孔结构132。堆叠通孔结构132具有垂直对准的导电通孔(例如，垂直于密封剂130的主表面的线穿过多个导电通孔的每个延伸)。在图6A至图21B中，一些部件(诸如晶种层，下面讨论的)可能仅显示在“A”或“B”图的一个中，并且为了简单起见可以从相应的“B”或“A”图省略。
在图6A和图6B中，可以在密封剂130、通孔112和管芯连接件126上沉积介电层133。在一些实施例中，介电层133由聚合物形成，聚合物可以是可以使用光刻掩模图案化的诸如PBO、聚酰亚胺、BCB等的光敏材料。在其它实施例中，介电层133由氮化物，诸如氮化硅；氧化物，诸如氧化硅、PSG、BSG、BPSG；等形成。可以通过旋涂、层压、CVD等或它们的组合形成介电层133。
之后，图案化介电层133。图案化形成暴露通孔112和管芯连接件126的部分的开口134。可以通过可接受的工艺图案化，诸如当介电层133是光敏材料时通过将介电层133暴露于光或通过例如使用各向异性蚀刻的蚀刻。如果介电层133是光敏材料，则可以在曝光之后显影介电层133。
之后，在介电层133上方和穿过介电层133延伸的开口134中形成晶种层136。在一些实施例中，晶种层136是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层136包括钛层和位于钛层上方的铜层。可以使用例如PVD等形成晶种层136。
在图7A和图7B中，在晶种层136上形成并且图案化光刻胶138。光刻胶138可以通过旋涂等形成，并且可以暴露于光以用于图案化。光刻胶138的图案对应于金属化图案142。图案化形成穿过光刻胶138的开口140以暴露晶种层136。
在图8A和图8B中，在光刻胶138的开口140中和晶种层136的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括如铜、钛、钨、铝等的金属。在实施例中，通过共形镀工艺形成导电材料。共形镀工艺可以是以小于约2.2A/dm2的电流密度(诸如电流密度在从约0.3A/dm2至约0.9A/dm2)实施的铜电镀工艺。镀液可以包含例如硫酸铜，并且可以具有诸如促进剂、抑制剂、流平剂等的添加剂。这种镀液和电流密度允许镀工艺成为共形镀工艺。因为金属化图案142用共形镀工艺形成，所以沿着介电层133的顶面延伸的金属化图案142的部分可以与沿着开口134的侧面和底面延伸的金属化图案142的部分具有大致相同的厚度。
导电材料和下面的部分晶种层136的组合形成金属化图案142。金属化图案142的部分形成堆叠通孔结构132的第一层。金属化图案142包括导电通孔143。导电通孔143形成在穿过介电层133至例如通孔112和/或管芯连接件126的开口134中。此外，由于共形镀工艺，在导电通孔143中形成凹槽144。
在图9A和图9B中，去除光刻胶138和晶种层136的其上未形成导电材料的部分。可以通过可接受的灰化或剥离工艺(诸如使用氧等离子体等)去除光刻胶138。一旦去除光刻胶138，则诸如通过使用可接受的蚀刻工艺(诸如湿或干蚀刻)去除晶种层136的暴露部分。
在图10A和图10B中，在介电层133和金属化图案142上沉积介电层146。在一些实施例中，介电层146由聚合物形成，聚合物可以是可以使用光刻掩模图案化的诸如PBO、聚酰亚胺、BCB等的光敏材料。在其它实施例中，介电层146由氮化物，诸如氮化硅；氧化物，诸如氧化硅、PSG、BSG、BPSG；等形成。可以通过旋涂、层压、CVD等或它们的组合形成介电层146。
之后，图案化介电层146。图案化形成暴露金属化图案142的部分的开口148。具体地，开口148暴露凹槽144。可以通过可接受的工艺图案化，诸如当介电层是光敏材料时通过将介电层146暴露于光或通过例如使用各向异性蚀刻的蚀刻。如果介电层146是光敏材料，则可以在曝光之后显影介电层146。
之后，在介电层146上方和开口148中形成晶种层150。在一些实施例中，晶种层150是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层150包括钛层和位于钛层上方的铜层。可以使用例如PVD等形成晶种层150。晶种层150沿着介电层146的顶面、沿着开口148的侧面、沿着金属化图案142的由开口148暴露的最上表面、沿着导电通孔143的限定凹槽144的侧面的部分并且沿着导电通孔143的限定凹槽144的底面的部分延伸。
在图11A和图11B中，在晶种层150上形成并且图案化光刻胶152。光刻胶152可以通过旋涂等形成，并且可以暴露于光以用于图案化。光刻胶152的图案对应于金属化图案156。图案化形成穿过光刻胶的开口154以暴露晶种层150。开口154暴露介电层146的开口148。
在图12A和图12B中，在光刻胶152的开口154中的晶种层150的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括如铜、钛、钨、铝等的金属。在实施例中，通过共形镀工艺形成导电材料(与金属化图案142类似)。
导电材料和下面的部分晶种层150的组合形成金属化图案156。金属化图案156的部分形成堆叠通孔结构132的第二层。金属化图案156包括导电通孔157。导电通孔157形成在穿过介电层146至金属化图案142的开口148中。具体地，导电通孔157延伸至导电通孔143的凹槽144内。此外，由于共形镀工艺，在导电通孔157中形成凹槽158。
在图13A和图13B中，去除光刻胶152和晶种层150的其上未形成导电材料的部分。可以通过可接受的灰化或剥离工艺(诸如使用氧等离子体等)去除光刻胶152。一旦去除光刻胶152，则诸如通过使用可接受的蚀刻工艺(诸如湿或干蚀刻)去除晶种层150的暴露部分。
通过形成具有凹槽144的导电通孔143，金属化图案142和156的界面可以是非平面的(例如，交错的)。此外，金属化图案142和156的界面可以占据与介电层133和146的界面偏移(例如，与该界面不同的平面)的多个平面。封装应力可以集中在介电层133和146的界面处。通过使介电层133和146的界面与金属化图案142和156的多个界面平面偏移，可以避免进一步的封装应力集中，从而减少在金属化图案142和156的界面处形成裂缝的可能性。
在图14A和图14B中，在介电层146和金属化图案156上沉积介电层160。在一些实施例中，介电层160由聚合物形成，聚合物可以是可以使用光刻掩模图案化的诸如PBO、聚酰亚胺、BCB等的光敏材料。在其它实施例中，介电层160由氮化物，诸如氮化硅；氧化物，诸如氧化硅、PSG、BSG、BPSG；等形成。可以通过旋涂、层压、CVD等或它们的组合形成介电层160。
之后，图案化介电层160。图案化形成暴露金属化图案156的部分的开口162。具体地，开口162暴露凹槽158。可以通过可接受的工艺图案化，诸如当介电层是光敏材料时通过将介电层160暴露于光或通过例如使用各向异性蚀刻的蚀刻。如果介电层160是光敏材料，则可以在曝光之后显影介电层160。
之后，在介电层160上方和开口162中形成晶种层164。在一些实施例中，晶种层164是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层164包括钛层和位于钛层上方的铜层。可以使用例如PVD等形成晶种层164。晶种层164沿着介电层160的顶面、沿着开口162的侧面、沿着金属化图案156的由开口162暴露的最上表面、沿着导电通孔157的限定凹槽158的侧面的部分并且沿着导电通孔157的限定凹槽158的底面的部分延伸。
在图15A和图15B中，在晶种层164上形成并且图案化光刻胶166。光刻胶166可以通过旋涂等形成，并且可以暴露于光以用于图案化。光刻胶166的图案对应于金属化图案170。图案化形成穿过光刻胶的开口168以暴露晶种层164。开口168暴露介电层160的开口162。
在图16A和图16B中，在晶种层164的暴露部分上和光刻胶166的开口168中形成导电材料。可以通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括如铜、钛、钨、铝等的金属。在实施例中，通过共形镀工艺形成导电材料(与金属化图案156类似)。
导电材料和下面的部分晶种层164的组合形成金属化图案170。金属化图案170的部分形成堆叠通孔结构132的第三层。金属化图案170包括导电通孔171。导电通孔171形成在穿过介电层160至金属化图案156的开口162中。具体地，导电通孔171延伸至导电通孔157的凹槽158内。此外，由于共形镀工艺，在导电通孔171中形成凹槽172。
在图17A和图17B中，去除光刻胶166和晶种层164的其上未形成导电材料的部分。可以通过可接受的灰化或剥离工艺(诸如使用氧等离子体等)去除光刻胶166。一旦去除光刻胶166，则诸如通过使用可接受的蚀刻工艺(诸如湿或干蚀刻)去除晶种层164的暴露部分。
在图18A和图18B中，在介电层160和金属化图案170上沉积介电层174。在一些实施例中，介电层174由聚合物形成，聚合物可以是可以使用光刻掩模图案化的诸如PBO、聚酰亚胺、BCB等的光敏材料。在其它实施例中，介电层174由氮化物，诸如氮化硅；氧化物，诸如氧化硅、PSG、BSG、BPSG；等形成。可以通过旋涂、层压、CVD等或它们的组合形成介电层174。
之后，图案化介电层174。图案化形成暴露金属化图案170的部分的开口176。具体地，开口176暴露凹槽172。可以通过可接受的工艺图案化，诸如当介电层是光敏材料时通过将介电层174暴露于光或通过例如使用各向异性蚀刻的蚀刻。如果介电层174是光敏材料，则可以在曝光之后显影介电层174。
之后，在介电层174上方和开口176中形成晶种层178。在一些实施例中，晶种层178是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层178包括钛层和位于钛层上方的铜层。可以使用例如PVD等形成晶种层178。晶种层178沿着介电层174的顶面、沿着开口176的侧面、沿着金属化图案170的由开口176暴露的最上表面、沿着导电通孔171的限定凹槽172的侧面的部分并且沿着导电通孔171的限定凹槽172的底面的部分延伸。
在图19A和图19B中，在晶种层178上形成并且图案化光刻胶180。光刻胶180可以通过旋涂等形成，并且可以暴露于光以用于图案化。光刻胶180的图案对应于焊盘184。图案化形成穿过光刻胶的开口182以暴露晶种层178。开口182暴露介电层174的开口176。光刻胶180中的开口182的图案对应于将随后形成在前侧再分布结构131的外侧上的焊盘。
在图20A和图20B中，在晶种层178的暴露部分上和光刻胶180的开口182中形成导电材料。可以通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括如铜、钛、钨、铝等的金属。在实施例中，可以通过间隙填充镀工艺形成导电材料，该间隙填充镀工艺具有与共形镀工艺不同的镀工艺参数。间隙填充镀工艺可以是以在从约2.0A/dm2至约6.0A/dm2(诸如大于约2.2A/dm2)的电流密度实施的铜电镀工艺。镀液可以包含例如硫酸铜，并且可以具有诸如促进剂、抑制剂、流平剂等的添加剂。这种镀液和电流密度允许镀工艺成为间隙填充镀工艺。用于间隙填充镀工艺的镀液可以与用于共形镀工艺的镀液类似或不同。
导电材料和下面的部分晶种层178的组合形成焊盘184。焊盘184的部分形成堆叠通孔结构132的第四层。焊盘184包括导电通孔185。导电通孔185形成在穿过介电层174至金属化图案170的开口176中。具体地，导电通孔185延伸至导电通孔171的凹槽172内。此外，由于间隙填充镀工艺，焊盘184不具有与堆叠通孔结构132中的其它通孔一样深的凹槽186，并且可能由于下面的开口176的形状，仅具有凹槽186。焊盘184用于连接至随后形成的导电连接件并且可以称为凸块下金属(UBM)。
在图21A和图21B中，去除光刻胶180和晶种层178的其上未形成导电材料的部分。可以通过可接受的灰化或剥离工艺(诸如使用氧等离子体等)去除光刻胶180。一旦去除光刻胶180，则诸如通过使用可接受的蚀刻工艺(诸如湿或干蚀刻)去除晶种层178的暴露部分。
前侧再分布结构131和堆叠通孔结构132示出为实例。可以在前侧再分布结构131中形成更多或更少的介电层和金属化图案。如果要形成更少的介电层和金属化图案，则可以省略以上讨论的步骤和工艺。如果要形成更多的介电层和金属化图案，则可以重复以上讨论的步骤和工艺。本领域普通技术人员将容易理解，可以省略或重复哪些步骤和工艺。
在图22中，在焊盘184上形成导电连接件187。导电连接件187可以是BGA连接件、焊球、金属柱、可控塌陷芯片连接(C4)凸块、微凸块、化学镀镍-化学镀钯浸金技术(ENEPIG)形成的凸块等。导电连接件187可以包括诸如焊料、铜、铝、金、镍、银、钯、锡等或它们的组合的导电材料。在一些实施例中，可以通过首先由诸如蒸发、电镀、印刷、焊料转移、球植等常用的方法形成焊料层来形成导电连接件187。一旦已经在结构上形成焊料层，则可以实施回流以将材料成形为期望的凸块形状。在另一实施例中，导电连接件187是通过溅射、印刷、电镀、化学镀、CVD等形成的金属柱(诸如铜柱)。金属柱可以是无焊料的并且具有基本垂直的侧壁。在这种实施例中，可以在导电连接件187的顶部上形成金属覆盖层(未示出)。金属覆盖层可以包括镍、锡、锡铅、金、银、钯、铟、镍-钯-金、镍-金等或它们的组合，并且可以通过镀工艺形成。
此外，将集成无源器件(IPD)188附接至前侧再分布结构131。IPD 188电连接至堆叠通孔结构132，并且堆叠通孔结构132可以电连接至集成电路管芯114。在实施例中，堆叠通孔结构132的最下面的通孔(例如，金属化图案142)电和物理连接至集成电路管芯114的一个管芯连接件126，并且堆叠通孔结构132的最上通孔(例如，焊盘184)电和物理连接至IPD 188。
在接合至前侧再分布结构131之前，可以根据可应用的制造工艺处理IPD 188。例如，IPD 188可以包括IPD 188的主结构中的一个或多个无源器件。主结构可以包括衬底和/或密封剂。在包括衬底的实施例中，衬底可以是半导体衬底，诸如掺杂或未掺杂的硅或SOI衬底的有源层。半导体衬底可以包括其它半导体材料，诸如锗；化合物半导体，包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟；合金半导体，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP；或它们的组合。也可以使用诸如多层衬底或梯度衬底的其它衬底。无源器件可以包括电容器、电阻器、电感器等或它们的组合。无源器件可以形成在半导体衬底中和/或半导体衬底上和/或密封剂内，并且可以通过由例如主结构上的一个或多个介电层中的金属化图案形成的互连结构互连，以形成IPD 188。IPD 188可以是表面安装器件(SMD)、2端子IPD、多端子IPD或其它类型的无源器件。IPD 188利用导电连接件189电和物理连接至堆叠通孔结构132的焊盘184，从而将前侧再分布结构131连接至IPD188。导电连接件189可以与导电连接件187类似，或可以不同。
在图23中，实施载体衬底脱粘以将载体衬底100从背侧再分布结构110(例如，介电层104)分离(脱粘)。根据一些实施例，脱粘包括将诸如激光或UV光的光投射到释放层102上，使得释放层102在光的热量下分解，并且可以去除载体衬底100。之后，翻转该结构并且放置在带192上。
此外，穿过介电层104形成暴露金属化图案106的部分的开口194。可以例如使用激光钻孔、蚀刻等形成开口。
图24至图26示出了根据一些实施例的用于形成封装结构500的工艺期间的中间步骤的截面图。封装结构500可以称为叠层封装(PoP)结构。
在图24中，将第二封装件300附接至第一封装件200。第二封装件300包括衬底302和连接至衬底302的一个或多个堆叠管芯308(308A和308B)。虽然示出了管芯308(308A和308B)的单个堆叠件，但是在其它实施例中，多个堆叠管芯308(每个均具有一个或多个堆叠管芯)可以并排设置为连接至衬底302的同一表面。衬底302可以由诸如硅、锗、金刚石等的半导体材料制成。在一些实施例中，也可以使用诸如硅锗、碳化硅、砷化镓、砷化铟、磷化铟、碳化硅锗、磷砷化镓、磷化镓铟、这些的组合等的化合物材料。此外，衬底302可以是绝缘体上硅(SOI)衬底。通常，SOI衬底包括诸如外延硅、锗、硅锗、SOI、绝缘体上硅锗(SGOI)或它们的组合的半导体材料层。在一个可选实施例中，衬底302是基于诸如玻璃纤维增强树脂芯的绝缘芯。芯材料的一个实例是诸如FR4的玻璃纤维树脂。芯材料的可选物质包括双马来酰亚胺-三嗪(BT)树脂或者其它印刷电路板(PCB)材料或薄膜。对于衬底302，可以使用诸如味之素积聚膜(ABF)或其它层压材料的积聚膜。
衬底302可以包括有源和无源器件(未示出)。如本领域普通技术人员将意识到，诸如晶体管、电容器、电阻器、这些的组合等的多种器件可以用于生成用于第二封装件300的设计的结构和功能需求。可以使用任何合适的方法形成该器件。
衬底302也可以包括金属化层(未示出)和通孔306。金属化层可以形成在有源和无源器件上方并且被设计为连接各个器件以形成功能电路。金属化层可以由电介质(例如，低k介电材料)和导电材料(例如，铜)(其具有互连导电材料层的通孔)的交替层形成，并且可以通过任何合适的工艺(诸如沉积、镶嵌、双镶嵌等)形成。在一些实施例中，衬底302基本没有有源和无源器件。
衬底302可以具有位于衬底302的第一侧上以连接至堆叠管芯308的接合焊盘303，以及位于衬底302的第二侧上以连接至导电连接件314的接合焊盘304，衬底302的第二侧与第一侧相对。在一些实施例中，通过在衬底302的第一侧和第二侧上的介电层(未示出)中形成凹槽(未示出)来形成接合焊盘303和304。凹槽可以形成为允许接合焊盘303和304嵌入至介电层内。在其它实施例中，由于接合焊盘303和304可以形成在介电层上，因此省略凹槽。在一些实施例中，接合焊盘303和304包括由铜、钛、镍、金、钯等或它们的组合制成的薄晶种层(未示出)。可以在薄晶种层上方沉积接合焊盘303和304的导电材料。可以通过电化学镀工艺、化学镀工艺、CVD、ALD、PVD等或它们的组合来形成导电材料。在实施例中，接合焊盘303和304的导电材料是铜、钨、铝、银、金等或它们的组合。
在实施例中，接合焊盘303和304是UBM，其包括三个导电材料层，诸如钛层、铜层和镍层。然而，本领域普通技术人员将意识到，存在适合于形成接合焊盘303和304的许多合适的材料和层布置，诸如铬/铬-铜合金/铜/金的布置、钛/钛钨/铜的布置或铜/镍/金的布置。可以用于接合焊盘303和304的任何合适的材料或材料层均完全旨在包括在本申请的范围内。在一些实施例中，通孔306穿过衬底302延伸并且将至少一个接合焊盘303连接至至少一个接合焊盘304。
在示出的实施例中，通过引线接合310将堆叠管芯308连接至衬底302，但是也可以使用诸如导电凸块的其它连接。在实施例中，堆叠管芯308是堆叠的存储器管芯。例如，堆叠管芯308可以是诸如低功率(LP)双数据率(DDR)存储器模块(诸如LPDDR1、LPDDR2、LPDDR3、LPDDR4等存储器模块)的存储器管芯。
堆叠管芯308和引线接合310可以由模塑材料312密封。可以例如使用压缩模塑将模塑材料312模塑在堆叠管芯308和引线接合310上。在一些实施例中，模塑材料312是模塑料、聚合物、环氧树脂、氧化硅填充材料等或它们的组合。可以实施固化步骤以固化模塑材料312，其中，固化工艺可以是热固化、UV固化等或它们的组合。
在一些实施例中，将堆叠管芯308和引线接合310埋在模塑材料312中，并且在模塑材料312的固化之后，实施诸如研磨的平坦化步骤以去除模塑材料312的过量部分并且为第二封装件300提供基本平坦的表面。
在形成第二封装件300之后，通过功能连接件314、接合焊盘304和金属化图案106将第二封装件300机械和电接合至第一封装件200。在一些实施例中，可以通过引线接合310、接合焊盘303和304、通孔306、功能连接件314和通孔112将堆叠管芯308连接至集成电路管芯114。
功能连接件314可以与以上描述的导电连接件187类似，并且此处不再重复描述，但是功能连接件314和导电连接件187不需要相同。功能连接件314可以在开口194中设置在衬底302的与堆叠管芯308相对的侧上。在一些实施例中，阻焊剂318也可以形成在衬底302的与堆叠管芯308相对的侧上。功能连接件314可以设置在阻焊剂318中的开口中以电和机械连接至衬底302中的导电部件(例如，接合焊盘304)。阻焊剂318可以用于保护衬底302的区免受外部损坏。
在一些实施例中，在接合功能连接件314之前，功能连接件314涂覆有焊剂(未示出)，诸如免洗焊剂。功能连接件314可以浸入焊剂中，或可以将焊剂喷射到功能连接件314上。在另一实施例中，可以将焊剂施加至金属化图案106的表面。
在一些实施例中，功能连接件314可以具有形成在其上的可选环氧树脂焊剂(未示出)，然后回流在将第二封装件300附接至第一封装件200之后剩余的环氧树脂焊剂的至少一些环氧树脂部分。该剩余的环氧树脂部分可以用作底部填充物，以减小应力并且保护由功能连接件314的回流产生的接头。
可以在第一封装件200和第二封装件300之间以及围绕功能连接件314形成底部填充物(未示出)。底部填充物可以在附接第一封装件200之后通过毛细管流动工艺形成，或可以在附接第一封装件200之前通过合适的沉积方法形成。
第二封装件300和第一封装件200之间的接合可以是焊料接合。在实施例中，通过回流工艺将第二封装件300接合至第一封装件200。在该回流工艺期间，功能连接件314与接合焊盘304和金属化图案106接触，以将第二封装件300物理和电连接至第一封装件200。在接合工艺之后，金属间化合物(IMC，未示出)可以形成在金属化图案106和功能连接件314的界面处并且也形成在功能连接件314和接合焊盘304之间的界面(未示出)处。
在图25中，通过沿着划线区域(例如，在邻近的封装区域之间)的锯切190来实施分割工艺。锯切190分割第一封装区域600与其它封装区域(未示出)。产生来自第一封装区域600的分割的第一封装件200。
在图26中，使用导电连接件187将第一封装件200安装至封装衬底400。封装衬底400可以由诸如硅、锗、金刚石等的半导体材料制成。可选地，也可以使用诸如硅锗、碳化硅、砷化镓、砷化铟、磷化铟、碳化硅锗、磷砷化镓、磷化镓铟、这些的组合等的化合物材料。此外，封装衬底400可以是SOI衬底。通常，SOI衬底包括诸如外延硅、锗、硅锗、SOI、SGOI或它们的组合的半导体材料层。在一个可选实施例中，封装衬底400是基于诸如玻璃纤维增强树脂芯的绝缘芯。芯材料的一个实例是诸如FR4的玻璃纤维树脂。芯材料的可选物质包括双马来酰亚胺-三嗪(BT)树脂或者其PCB材料或薄膜。对于封装衬底400，可以使用诸如ABF或其它层压材料的积聚膜。
封装衬底400可以包括有源和无源器件(未示出)。如本领域普通技术人员将意识到，诸如晶体管、电容器、电阻器、这些的组合等的多种器件可以用于生成用于封装结构500的设计的结构和功能需求。可以使用任何合适的方法形成该器件。
封装衬底400也可以包括金属化层和通孔(未示出)以及位于金属化层和通孔上方的接合焊盘402。金属化层可以形成在有源和无源器件上方并且被设计为连接各个器件以形成功能电路。金属化层可以由电介质(例如，低k介电材料)和导电材料(例如，铜)(其具有互连导电材料层的通孔)的交替层形成，并且可以通过任何合适的工艺(诸如沉积、镶嵌、双镶嵌等)形成。在一些实施例中，封装衬底400基本没有有源和无源器件。
在一些实施例中，回流导电连接件187以将第一封装件200附接至接合焊盘402。导电连接件187将包括封装衬底400中的金属化层的封装衬底400电和/或物理连接至第一封装件200。在一些实施例中，在安装在封装衬底400上之前，可以将无源器件(例如，未示出的表面安装器件(SMD))附接至第一封装件200(例如，接合至接合焊盘402)。在这种实施例中，无源器件可以与导电连接件187接合至第一封装件200的同一表面。
导电连接件187可以具有形成在其上的环氧树脂焊剂(未示出)，然后回流在将第一封装件200附接至封装衬底400之后剩余的环氧树脂焊剂的至少一些环氧树脂部分。该剩余的环氧树脂部分可以用作底部填充物以减小应力并且保护由导电连接件187的回流产生的接头。在一些实施例中，底部填充物(未示出)可以形成在第一封装件200和封装衬底400之间并且围绕导电连接件187。底部填充物可以在附接第一封装件200之后通过毛细管流动工艺形成，或可以在附接第一封装件200之前通过合适的沉积方法形成。
图27至图42示出了根据一些其它实施例的堆叠通孔结构132的形成。图27至图42示出了区域650。在图27至图42的实施例中，在导电柱周围形成堆叠通孔结构132的通孔。
在图27中，在密封剂130、通孔112和集成电路管芯114(例如，管芯连接件126)上沉积介电层133。之后，图案化介电层133以形成开口134。之后，在介电层133上方和穿过介电层133延伸的开口134中形成晶种层136。
在图28中，在晶种层136上形成并且图案化光刻胶138。之后，图案化光刻胶138，以形成穿过光刻胶138的开口140以暴露晶种层136。开口140的宽度小于开口134的宽度。
在图29中，在晶种层136的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括如铜、钛、钨、铝等的金属。导电材料和下面的部分晶种层136的组合形成导电柱702。
在图30中，去除光刻胶138和晶种层136的其上未形成导电材料的部分。
在图31中，在介电层133上和导电柱702周围沉积介电层146。之后，图案化介电层146。图案化形成暴露开口134的开口148。之后，在介电层146上方、穿过介电层146的开口148中和穿过介电层133的开口134中形成晶种层150。晶种层150沿着导电柱702的侧面延伸。
在图32中，在晶种层150上形成并且图案化光刻胶152。图案化形成穿过光刻胶的开口154以暴露晶种层150。开口154围绕导电柱702。图案化的光刻胶152的部分设置在导电柱702上方。
在图33中，在晶种层150的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括如铜、钛、钨、铝等的金属。导电材料和下面的部分晶种层150的组合在导电柱702周围形成导电通孔704。导电通孔704穿过介电层133和146延伸。
在图34中，去除光刻胶152和晶种层150的其上未形成导电材料的部分。
在图35中，在介电层146和导电通孔704上沉积介电层160。之后，图案化介电层160。图案化形成暴露导电通孔704的部分和导电柱702的开口162。之后，在介电层160上方、穿过介电层160的开口162中形成晶种层164。晶种层164沿着导电柱702的侧壁和顶面延伸。
在图36中，在晶种层164上形成并且图案化光刻胶166。图案化形成穿过光刻胶的开口168以暴露晶种层164。开口168在导电柱702上方，并且可以具有约等于导电柱702的宽度的宽度。
在图37中，在晶种层164的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括如铜、钛、钨、铝等的金属。导电材料和下面的部分晶种层164的组合在导电柱702上形成导电柱706。
在图38中，去除光刻胶166和晶种层164的其上未形成导电材料的部分。未去除晶种层164的沿着导电柱702的侧壁和顶面的部分。
在图39中，在介电层160和导电通孔704上以及导电柱702和706周围沉积介电层174。图案化介电层174。图案化形成暴露导电通孔704的部分和导电柱702和706的开口176。之后，在介电层174上方以及穿过介电层174的开口176中形成晶种层178。晶种层178沿着导电柱702和706的侧壁延伸，并且沿着导电柱706的顶面延伸。
在图40中，在晶种层178上形成并且图案化光刻胶180。图案化形成穿过光刻胶180的开口182以暴露晶种层178。开口182在导电柱702和706上方。
在图41中，在晶种层178的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括如铜、钛、钨、铝等的金属。导电材料和下面的部分晶种层178的组合形成焊盘184，其包括导电柱702和706周围的导电通孔708。导电通孔708穿过介电层160和174延伸。导电通孔708可以在导电柱702和706上方延伸。
在图42中，去除光刻胶180和晶种层178的其上未形成导电材料的部分。
实施例可以实现许多优势。通过使介电层133和146的界面与金属化图案142和156的多个界面平面偏移，可以避免进一步的封装应力集中，从而减少在金属化图案142和156的界面处形成裂缝的可能性。此外，晶种层136、150、164和178可以用作邻近的堆叠通孔之间的扩散阻挡层。在形成导电柱702和706的实施例中，导电柱702和706可以用作核心结构，增强堆叠通孔结构132。
在实施例中，器件包括：模塑料；密封在模塑料中的集成电路管芯；邻近集成电路管芯的通孔；以及位于集成电路管芯、模塑料和通孔上方的再分布结构，再分布结构电连接至集成电路管芯和通孔，再分布结构包括：设置在模塑料上方的第一介电层；穿过第一介电层延伸的第一导电通孔；设置在第一介电层和第一导电通孔上方的第二介电层；以及穿过第二介电层延伸并且延伸至第一导电通孔的部分内的第二导电通孔，第一导电通孔和第二导电通孔之间的界面是非平面的。
在一些实施例中，第一导电通孔和第二导电通孔之间的界面具有位于第一平面的第一部分和位于第二平面的第二部分，第一平面靠近集成电路管芯，第二平面远离集成电路管芯，并且第一介电层和第二介电层之间的界面位于第一平面和第二平面之间的第三平面。在一些实施例中，再分布结构还包括：位于第二介电层和第二导电通孔上方的第三介电层；以及穿过第三介电层延伸并且延伸至第二导电通孔的部分内的第三导电通孔，第二导电通孔和第三导电通孔之间的界面是非平面的。在一些实施例中，该器件还包括：附接至第三导电通孔的集成无源器件(IPD)。
在实施例中，方法包括：将集成电路管芯密封在模塑料中，集成电路管芯具有管芯连接件；在模塑料上方沉积第一介电层；穿过第一介电层图案化第一开口，以暴露集成电路管芯的管芯连接件；在第一介电层上方和第一开口中沉积第一晶种层；在第一晶种层上镀穿过第一介电层延伸的第一导电通孔，第一导电通孔在第一导电通孔的穿过第一介电层延伸的部分中具有第一凹槽；在第一介电层和第一导电通孔上方沉积第二介电层；在第二介电层中图案化第二开口，第二开口暴露第一导电通孔的第一凹槽；在第二介电层上方、第二开口中和第一凹槽中沉积第二晶种层；以及在第二晶种层上镀第二导电通孔，第二导电通孔延伸至第一导电通孔的第一凹槽内并且穿过第二介电层延伸，第二导电通孔在第二导电通孔的穿过第二介电层延伸的部分中具有第二凹槽。
在一些实施例中，第二晶种层具有位于第一平面的第一部分和位于第二平面的第二部分，位于第一介电层和第二介电层之间的第二界面位于第三平面，以及第一平面靠近集成电路管芯，第二平面远离集成电路管芯，并且第三平面位于第一平面和第二平面之间。在一些实施例中，第二晶种层沿着第二介电层的顶面、第二开口的侧面、第一导电通孔的最上表面、第一导电通孔的限定第一凹槽的侧面的部分以及第一导电通孔的限定第一凹槽的底面的部分延伸。在一些实施例中，第二介电层和第二晶种层之间的界面是非平面的。在一些实施例中，该方法还包括：在第二介电层和第二导电通孔上方沉积第三介电层；在第三介电层中图案化第三开口，第三开口暴露第二导电通孔的第二凹槽；在第三介电层上方、第三开口中和第二凹槽中沉积第三晶种层；以及在第三晶种层上镀第三导电通孔，第三导电通孔延伸至第二导电通孔的第二凹槽内并且穿过第三介电层延伸。在一些实施例中，第二导电通孔穿过第二介电层延伸，并且至少部分地延伸至第一介电层和第三介电层内。在一些实施例中，该方法还包括：将集成无源器件(IPD)附接至第三导电通孔。在一些实施例中，利用间隙填充镀工艺来实施在第二晶种层上镀第三导电通孔。在一些实施例中，间隙填充镀工艺包括以在从2.0A/dm2至6.0A/dm2的镀电流密度以及包含硫酸铜的镀液实施的镀工艺。在一些实施例中，利用共形镀工艺来实施在第二晶种层上镀第二导电通孔。在一些实施例中，共形镀工艺包括以在从0.3A/dm2至0.9A/dm2的镀电流密度以及包含硫酸铜的镀液实施的镀工艺。
在实施例中，方法包括：将集成电路管芯密封在模塑料中，集成电路管芯具有管芯连接件；在模塑料上方沉积第一介电层；穿过第一介电层图案化第一开口；在集成电路管芯的管芯连接件上的第一开口中形成第一导电柱；在第一介电层上方沉积第二介电层；在第二介电层中图案化第二开口，第二开口暴露第一开口；以及在第一开口和第二开口中的第一导电柱周围形成第一导电通孔。
在一些实施例中，该方法还包括：在第二介电层上方沉积第三介电层；在第三介电层中图案化第三开口，第三开口暴露第一导电通孔；在第一导电柱上的第三开口中形成第二导电柱；在第三介电层上方沉积第四介电层；在第四介电层中图案化第四开口，第四开口暴露第三开口；以及在第三开口和第四开口中的第二导电柱周围形成第二导电通孔。在一些实施例中，该方法还包括：将集成无源器件(IPD)附接至第二导电通孔。在一些实施例中，在沉积第三介电层之后，第一导电通孔穿过第一介电层、穿过第二介电层并且部分地延伸至第三介电层内。在一些实施例中，还在第一导电柱周围形成第二导电通孔。
上面概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解，它们可以容易地使用本发明作为基础来设计或修改用于实施与本人所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。

Claims (20)

1.一种半导体器件，包括：
模塑料；
集成电路管芯，密封在所述模塑料中；
通孔，邻近所述集成电路管芯；以及
再分布结构，位于所述集成电路管芯、所述模塑料和所述通孔上方，所述再分布结构电连接至所述集成电路管芯和所述通孔，所述再分布结构包括：
第一介电层，设置在所述模塑料上方；
第一金属化图案，包括位于所述第一介电层的表面上的第一金属水平部分和延伸穿过所述第一介电层的第一导电通孔；
第二介电层，设置在所述第一介电层和所述第一导电通孔上方；和
第二金属化图案，包括位于所述第二介电层的表面上的第二金属水平部分和延伸穿过所述第二介电层并且延伸至所述第一导电通孔的部分内的第二导电通孔，所述第一金属化图案和所述第二金属化图案之间的界面是非平面的，其中，所述第一金属化图案和所述第二金属化图案之间的界面具有位于第一平面的第一部分和位于第二平面的第二部分，所述第一平面靠近所述集成电路管芯，所述第二平面远离所述集成电路管芯，并且其中，所述第一介电层和所述第二介电层之间的界面位于所述第一平面和所述第二平面之间的第三平面，所述第一平面、所述第二平面彼此平行。
2.根据权利要求1所述的半导体器件，其中，所述第一平面、所述第二平面和所述第三平面均平行于所述集成电路管芯的表面。
3.根据权利要求1所述的半导体器件，其中，所述再分布结构还包括：
第三介电层，位于所述第二介电层和所述第二导电通孔上方；以及
第三导电通孔，穿过所述第三介电层延伸并且延伸至所述第二导电通孔的部分内，所述第二导电通孔和所述第三导电通孔之间的界面是非平面的。
4.根据权利要求3所述的半导体器件，还包括：
集成无源器件(IPD)，附接至所述第三导电通孔。
5.一种形成半导体封装件的方法，包括：
将集成电路管芯密封在模塑料中，所述集成电路管芯具有管芯连接件；
在所述模塑料上方沉积第一介电层；
穿过所述第一介电层图案化第一开口，所述第一开口暴露所述集成电路管芯的所述管芯连接件；
在所述第一介电层上方和所述第一开口中沉积第一晶种层；
在所述第一晶种层上镀第一导电通孔，所述第一导电通孔穿过所述第一介电层延伸，所述第一导电通孔在穿过所述第一介电层延伸的所述第一导电通孔的部分中具有第一凹槽；
在所述第一介电层和所述第一导电通孔上方沉积第二介电层；
在所述第二介电层中图案化第二开口，所述第二开口暴露所述第一导电通孔的所述第一凹槽；
在所述第二介电层上方、所述第二开口中和所述第一凹槽中沉积第二晶种层；以及
在所述第二晶种层上镀第二导电通孔，所述第二导电通孔延伸至所述第一导电通孔的所述第一凹槽内并且穿过所述第二介电层延伸，所述第二导电通孔在穿过所述第二介电层延伸的所述第二导电通孔的部分中具有第二凹槽，
其中，所述第二晶种层具有位于第一平面的第一部分和位于第二平面的第二部分，其中，所述第一介电层和所述第二介电层之间的第二界面位于第三平面，并且其中，所述第一平面靠近所述集成电路管芯，所述第二平面远离所述集成电路管芯，并且所述第三平面位于所述第一平面和所述第二平面之间，所述第一平面、所述第二平面彼此平行。
6.根据权利要求5所述的方法，其中，所述第一平面、所述第二平面和所述第三平面均平行于所述集成电路管芯的表面。
7.根据权利要求5所述的方法，其中，所述第二晶种层沿着所述第二介电层的顶面、所述第二开口的侧面、所述第一导电通孔的最上表面、所述第一导电通孔的限定所述第一凹槽的侧面的部分以及所述第一导电通孔的限定所述第一凹槽的底面的部分延伸。
8.根据权利要求5所述的方法，其中，所述第二介电层和所述第二晶种层之间的界面是非平面的。
9.根据权利要求5所述的方法，还包括：
在所述第二介电层和所述第二导电通孔上方沉积第三介电层；
在所述第三介电层中图案化第三开口，所述第三开口暴露所述第二导电通孔的所述第二凹槽；
在所述第三介电层上方、所述第三开口中和所述第二凹槽中沉积第三晶种层；以及
在所述第三晶种层上镀第三导电通孔，所述第三导电通孔延伸至所述第二导电通孔的所述第二凹槽内并且穿过所述第三介电层延伸。
10.根据权利要求9所述的方法，其中，所述第二导电通孔穿过所述第二介电层延伸，并且至少部分地延伸至所述第一介电层和所述第三介电层内。
11.根据权利要求9所述的方法，还包括：
将集成无源器件(IPD)附接至所述第三导电通孔。
12.根据权利要求9所述的方法，其中，利用间隙填充镀工艺来实施在所述第二晶种层上镀所述第三导电通孔。
13.根据权利要求12所述的方法，其中，所述间隙填充镀工艺包括以在从2.0A/dm2至6.0A/dm2的镀电流密度以及包含硫酸铜的镀液实施的镀工艺。
14.根据权利要求5所述的方法，其中，利用共形镀工艺来实施在所述第二晶种层上镀所述第二导电通孔。
15.根据权利要求14所述的方法，其中，所述共形镀工艺包括以在从0.3A/dm2至0.9A/dm2的镀电流密度以及包含硫酸铜的镀液实施的镀工艺。
16.一种形成半导体封装件的方法，包括：
将集成电路管芯密封在模塑料中，所述集成电路管芯具有管芯连接件；
在所述模塑料上方沉积第一介电层；
穿过所述第一介电层图案化第一开口；
在所述集成电路管芯的所述管芯连接件上的所述第一开口中形成第一导电柱；
在所述第一介电层上方沉积第二介电层；
在所述第二介电层中图案化第二开口，所述第二开口暴露所述第一开口；以及
在所述第一开口和所述第二开口中的所述第一导电柱周围形成第一导电通孔。
17.根据权利要求16所述的方法，还包括：
在所述第二介电层上方沉积第三介电层；
在所述第三介电层中图案化第三开口，所述第三开口暴露所述第一导电通孔；
在所述第一导电柱上的所述第三开口中形成第二导电柱；
在所述第三介电层上方沉积第四介电层；
在所述第四介电层中图案化第四开口，所述第四开口暴露所述第三开口；以及
在所述第三开口和所述第四开口中的所述第二导电柱周围形成第二导电通孔。
18.根据权利要求17所述的方法，还包括：
将集成无源器件(IPD)附接至所述第二导电通孔。
19.根据权利要求17所述的方法，其中，在沉积所述第三介电层之后，所述第一导电通孔穿过所述第一介电层、穿过所述第二介电层延伸并且部分地延伸至所述第三介电层内。
20.根据权利要求17所述的方法，其中，还在所述第一导电柱周围形成所述第二导电通孔。
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